1 /* linux/arch/arm/mach-s3c2412/dma.c
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2412 DMA selection
8 * http://armlinux.simtec.co.uk/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/serial_core.h>
23 #include <plat/dma-s3c24xx.h>
26 #include <plat/regs-serial.h>
27 #include <mach/regs-gpio.h>
28 #include <plat/regs-dma.h>
29 #include <mach/regs-lcd.h>
30 #include <plat/regs-spi.h>
32 #define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
34 static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings
[] = {
37 .channels
= MAP(S3C2412_DMAREQSEL_XDREQ0
),
38 .channels_rx
= MAP(S3C2412_DMAREQSEL_XDREQ0
),
42 .channels
= MAP(S3C2412_DMAREQSEL_XDREQ1
),
43 .channels_rx
= MAP(S3C2412_DMAREQSEL_XDREQ1
),
47 .channels
= MAP(S3C2412_DMAREQSEL_SDI
),
48 .channels_rx
= MAP(S3C2412_DMAREQSEL_SDI
),
52 .channels
= MAP(S3C2412_DMAREQSEL_SPI0TX
),
53 .channels_rx
= MAP(S3C2412_DMAREQSEL_SPI0RX
),
57 .channels
= MAP(S3C2412_DMAREQSEL_SPI1TX
),
58 .channels_rx
= MAP(S3C2412_DMAREQSEL_SPI1RX
),
62 .channels
= MAP(S3C2412_DMAREQSEL_UART0_0
),
63 .channels_rx
= MAP(S3C2412_DMAREQSEL_UART0_0
),
67 .channels
= MAP(S3C2412_DMAREQSEL_UART1_0
),
68 .channels_rx
= MAP(S3C2412_DMAREQSEL_UART1_0
),
72 .channels
= MAP(S3C2412_DMAREQSEL_UART2_0
),
73 .channels_rx
= MAP(S3C2412_DMAREQSEL_UART2_0
),
75 [DMACH_UART0_SRC2
] = {
77 .channels
= MAP(S3C2412_DMAREQSEL_UART0_1
),
78 .channels_rx
= MAP(S3C2412_DMAREQSEL_UART0_1
),
80 [DMACH_UART1_SRC2
] = {
82 .channels
= MAP(S3C2412_DMAREQSEL_UART1_1
),
83 .channels_rx
= MAP(S3C2412_DMAREQSEL_UART1_1
),
85 [DMACH_UART2_SRC2
] = {
87 .channels
= MAP(S3C2412_DMAREQSEL_UART2_1
),
88 .channels_rx
= MAP(S3C2412_DMAREQSEL_UART2_1
),
92 .channels
= MAP(S3C2412_DMAREQSEL_TIMER
),
93 .channels_rx
= MAP(S3C2412_DMAREQSEL_TIMER
),
97 .channels
= MAP(S3C2412_DMAREQSEL_I2SRX
),
98 .channels_rx
= MAP(S3C2412_DMAREQSEL_I2SRX
),
102 .channels
= MAP(S3C2412_DMAREQSEL_I2STX
),
103 .channels_rx
= MAP(S3C2412_DMAREQSEL_I2STX
),
107 .channels
= MAP(S3C2412_DMAREQSEL_USBEP1
),
108 .channels_rx
= MAP(S3C2412_DMAREQSEL_USBEP1
),
112 .channels
= MAP(S3C2412_DMAREQSEL_USBEP2
),
113 .channels_rx
= MAP(S3C2412_DMAREQSEL_USBEP2
),
117 .channels
= MAP(S3C2412_DMAREQSEL_USBEP3
),
118 .channels_rx
= MAP(S3C2412_DMAREQSEL_USBEP3
),
122 .channels
= MAP(S3C2412_DMAREQSEL_USBEP4
),
123 .channels_rx
= MAP(S3C2412_DMAREQSEL_USBEP4
),
127 static void s3c2412_dma_direction(struct s3c2410_dma_chan
*chan
,
128 struct s3c24xx_dma_map
*map
,
129 enum dma_data_direction dir
)
133 if (dir
== DMA_FROM_DEVICE
)
134 chsel
= map
->channels_rx
[0];
136 chsel
= map
->channels
[0];
138 chsel
&= ~DMA_CH_VALID
;
139 chsel
|= S3C2412_DMAREQSEL_HW
;
141 writel(chsel
, chan
->regs
+ S3C2412_DMA_DMAREQSEL
);
144 static void s3c2412_dma_select(struct s3c2410_dma_chan
*chan
,
145 struct s3c24xx_dma_map
*map
)
147 s3c2412_dma_direction(chan
, map
, chan
->source
);
150 static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel
= {
151 .select
= s3c2412_dma_select
,
152 .direction
= s3c2412_dma_direction
,
154 .map
= s3c2412_dma_mappings
,
155 .map_size
= ARRAY_SIZE(s3c2412_dma_mappings
),
158 static int __init
s3c2412_dma_add(struct device
*dev
,
159 struct subsys_interface
*sif
)
162 return s3c24xx_dma_init_map(&s3c2412_dma_sel
);
165 static struct subsys_interface s3c2412_dma_interface
= {
166 .name
= "s3c2412_dma",
167 .subsys
= &s3c2412_subsys
,
168 .add_dev
= s3c2412_dma_add
,
171 static int __init
s3c2412_dma_init(void)
173 return subsys_interface_register(&s3c2412_dma_interface
);
176 arch_initcall(s3c2412_dma_init
);