2 * Copyright (C) ST-Ericsson SA 2010
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * Author: Lee Jones <lee.jones@linaro.org> for ST-Ericsson
6 * License terms: GNU General Public License (GPL) version 2
9 #include <linux/platform_device.h>
11 #include <linux/mfd/dbx500-prcmu.h>
12 #include <linux/clksrc-dbx500-prcmu.h>
13 #include <linux/sys_soc.h>
14 #include <linux/err.h>
15 #include <linux/slab.h>
16 #include <linux/stat.h>
18 #include <linux/of_irq.h>
19 #include <linux/irq.h>
20 #include <linux/irqchip.h>
21 #include <linux/irqchip/arm-gic.h>
22 #include <linux/platform_data/clk-ux500.h>
23 #include <linux/platform_data/arm-ux500-pm.h>
25 #include <asm/mach/map.h>
30 #include "board-mop500.h"
31 #include "db8500-regs.h"
35 * FIXME: Should we set up the GPIO domain here?
37 * The problem is that we cannot put the interrupt resources into the platform
38 * device until the irqdomain has been added. Right now, we set the GIC interrupt
39 * domain from init_irq(), then load the gpio driver from
40 * core_initcall(nmk_gpio_init) and add the platform devices from
41 * arch_initcall(customize_machine).
43 * This feels fragile because it depends on the gpio device getting probed
44 * _before_ any device uses the gpio interrupts.
46 void __init
ux500_init_irq(void)
48 void __iomem
*dist_base
;
49 void __iomem
*cpu_base
;
51 gic_arch_extn
.flags
= IRQCHIP_SKIP_SET_WAKE
| IRQCHIP_MASK_ON_SUSPEND
;
53 if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
54 dist_base
= __io_address(U8500_GIC_DIST_BASE
);
55 cpu_base
= __io_address(U8500_GIC_CPU_BASE
);
60 if (of_have_populated_dt())
64 gic_init(0, 29, dist_base
, cpu_base
);
67 * Init clocks here so that they are available for system timer
70 if (cpu_is_u8500_family()) {
71 prcmu_early_init(U8500_PRCMU_BASE
, SZ_8K
- 1);
72 ux500_pm_init(U8500_PRCMU_BASE
, SZ_8K
- 1);
73 u8500_clk_init(U8500_CLKRST1_BASE
, U8500_CLKRST2_BASE
,
74 U8500_CLKRST3_BASE
, U8500_CLKRST5_BASE
,
76 } else if (cpu_is_u9540()) {
77 prcmu_early_init(U8500_PRCMU_BASE
, SZ_8K
- 1);
78 ux500_pm_init(U8500_PRCMU_BASE
, SZ_8K
- 1);
79 u8500_clk_init(U8500_CLKRST1_BASE
, U8500_CLKRST2_BASE
,
80 U8500_CLKRST3_BASE
, U8500_CLKRST5_BASE
,
82 } else if (cpu_is_u8540()) {
83 prcmu_early_init(U8500_PRCMU_BASE
, SZ_8K
+ SZ_4K
- 1);
84 ux500_pm_init(U8500_PRCMU_BASE
, SZ_8K
+ SZ_4K
- 1);
89 void __init
ux500_init_late(void)
94 static const char * __init
ux500_get_machine(void)
96 return kasprintf(GFP_KERNEL
, "DB%4x", dbx500_partnumber());
99 static const char * __init
ux500_get_family(void)
101 return kasprintf(GFP_KERNEL
, "ux500");
104 static const char * __init
ux500_get_revision(void)
106 unsigned int rev
= dbx500_revision();
109 return kasprintf(GFP_KERNEL
, "%s", "ED");
110 else if (rev
>= 0xA0)
111 return kasprintf(GFP_KERNEL
, "%d.%d",
112 (rev
>> 4) - 0xA + 1, rev
& 0xf);
114 return kasprintf(GFP_KERNEL
, "%s", "Unknown");
117 static ssize_t
ux500_get_process(struct device
*dev
,
118 struct device_attribute
*attr
,
121 if (dbx500_id
.process
== 0x00)
122 return sprintf(buf
, "Standard\n");
124 return sprintf(buf
, "%02xnm\n", dbx500_id
.process
);
127 static void __init
soc_info_populate(struct soc_device_attribute
*soc_dev_attr
,
130 soc_dev_attr
->soc_id
= soc_id
;
131 soc_dev_attr
->machine
= ux500_get_machine();
132 soc_dev_attr
->family
= ux500_get_family();
133 soc_dev_attr
->revision
= ux500_get_revision();
136 struct device_attribute ux500_soc_attr
=
137 __ATTR(process
, S_IRUGO
, ux500_get_process
, NULL
);
139 struct device
* __init
ux500_soc_device_init(const char *soc_id
)
141 struct device
*parent
;
142 struct soc_device
*soc_dev
;
143 struct soc_device_attribute
*soc_dev_attr
;
145 soc_dev_attr
= kzalloc(sizeof(*soc_dev_attr
), GFP_KERNEL
);
147 return ERR_PTR(-ENOMEM
);
149 soc_info_populate(soc_dev_attr
, soc_id
);
151 soc_dev
= soc_device_register(soc_dev_attr
);
152 if (IS_ERR(soc_dev
)) {
157 parent
= soc_device_to_device(soc_dev
);
158 device_create_file(parent
, &ux500_soc_attr
);