1 comment "Processor Type"
3 # Select CPU types depending on the architecture selected. This selects
4 # which CPUs we support in the kernel image, and the compiler instruction
9 bool "Support ARM7TDMI processor"
14 select CPU_PABRT_LEGACY
16 A 32-bit RISC microprocessor based on the ARM7 processor core
17 which has no memory control unit and cache.
19 Say Y if you want support for the ARM7TDMI processor.
24 bool "Support ARM720T processor" if ARCH_INTEGRATOR
29 select CPU_COPY_V4WT if MMU
31 select CPU_PABRT_LEGACY
32 select CPU_TLB_V4WT if MMU
34 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
35 MMU built around an ARM7TDMI core.
37 Say Y if you want support for the ARM720T processor.
42 bool "Support ARM740T processor" if ARCH_INTEGRATOR
48 select CPU_PABRT_LEGACY
50 A 32-bit RISC processor with 8KB cache or 4KB variants,
51 write buffer and MPU(Protection Unit) built around
54 Say Y if you want support for the ARM740T processor.
59 bool "Support ARM9TDMI processor"
64 select CPU_PABRT_LEGACY
66 A 32-bit RISC microprocessor based on the ARM9 processor core
67 which has no memory control unit and cache.
69 Say Y if you want support for the ARM9TDMI processor.
74 bool "Support ARM920T processor" if ARCH_INTEGRATOR
79 select CPU_COPY_V4WB if MMU
81 select CPU_PABRT_LEGACY
82 select CPU_TLB_V4WBI if MMU
84 The ARM920T is licensed to be produced by numerous vendors,
85 and is used in the Cirrus EP93xx and the Samsung S3C2410.
87 Say Y if you want support for the ARM920T processor.
92 bool "Support ARM922T processor" if ARCH_INTEGRATOR
97 select CPU_COPY_V4WB if MMU
99 select CPU_PABRT_LEGACY
100 select CPU_TLB_V4WBI if MMU
102 The ARM922T is a version of the ARM920T, but with smaller
103 instruction and data caches. It is used in Altera's
104 Excalibur XA device family and Micrel's KS8695 Centaur.
106 Say Y if you want support for the ARM922T processor.
111 bool "Support ARM925T processor" if ARCH_OMAP1
114 select CPU_CACHE_V4WT
115 select CPU_CACHE_VIVT
116 select CPU_COPY_V4WB if MMU
118 select CPU_PABRT_LEGACY
119 select CPU_TLB_V4WBI if MMU
121 The ARM925T is a mix between the ARM920T and ARM926T, but with
122 different instruction and data caches. It is used in TI's OMAP
125 Say Y if you want support for the ARM925T processor.
130 bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
132 select CPU_ABRT_EV5TJ
133 select CPU_CACHE_VIVT
134 select CPU_COPY_V4WB if MMU
136 select CPU_PABRT_LEGACY
137 select CPU_TLB_V4WBI if MMU
139 This is a variant of the ARM920. It has slightly different
140 instruction sequences for cache and TLB operations. Curiously,
141 there is no documentation on it at the ARM corporate website.
143 Say Y if you want support for the ARM926T processor.
152 select CPU_CACHE_VIVT
153 select CPU_COPY_FA if MMU
155 select CPU_PABRT_LEGACY
156 select CPU_TLB_FA if MMU
158 The FA526 is a version of the ARMv4 compatible processor with
159 Branch Target Buffer, Unified TLB and cache line size 16.
161 Say Y if you want support for the FA526 processor.
166 bool "Support ARM940T processor" if ARCH_INTEGRATOR
169 select CPU_ABRT_NOMMU
170 select CPU_CACHE_VIVT
172 select CPU_PABRT_LEGACY
174 ARM940T is a member of the ARM9TDMI family of general-
175 purpose microprocessors with MPU and separate 4KB
176 instruction and 4KB data cases, each with a 4-word line
179 Say Y if you want support for the ARM940T processor.
184 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
187 select CPU_ABRT_NOMMU
188 select CPU_CACHE_VIVT
190 select CPU_PABRT_LEGACY
192 ARM946E-S is a member of the ARM9E-S family of high-
193 performance, 32-bit system-on-chip processor solutions.
194 The TCM and ARMv5TE 32-bit instruction set is supported.
196 Say Y if you want support for the ARM946E-S processor.
199 # ARM1020 - needs validating
201 bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
204 select CPU_CACHE_V4WT
205 select CPU_CACHE_VIVT
206 select CPU_COPY_V4WB if MMU
208 select CPU_PABRT_LEGACY
209 select CPU_TLB_V4WBI if MMU
211 The ARM1020 is the 32K cached version of the ARM10 processor,
212 with an addition of a floating-point unit.
214 Say Y if you want support for the ARM1020 processor.
217 # ARM1020E - needs validating
219 bool "Support ARM1020E processor" if ARCH_INTEGRATOR
223 select CPU_CACHE_V4WT
224 select CPU_CACHE_VIVT
225 select CPU_COPY_V4WB if MMU
227 select CPU_PABRT_LEGACY
228 select CPU_TLB_V4WBI if MMU
232 bool "Support ARM1022E processor" if ARCH_INTEGRATOR
235 select CPU_CACHE_VIVT
236 select CPU_COPY_V4WB if MMU # can probably do better
238 select CPU_PABRT_LEGACY
239 select CPU_TLB_V4WBI if MMU
241 The ARM1022E is an implementation of the ARMv5TE architecture
242 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
243 embedded trace macrocell, and a floating-point unit.
245 Say Y if you want support for the ARM1022E processor.
250 bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
252 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
253 select CPU_CACHE_VIVT
254 select CPU_COPY_V4WB if MMU # can probably do better
256 select CPU_PABRT_LEGACY
257 select CPU_TLB_V4WBI if MMU
259 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
260 based upon the ARM10 integer core.
262 Say Y if you want support for the ARM1026EJ-S processor.
267 bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
268 select CPU_32v3 if ARCH_RPC
269 select CPU_32v4 if !ARCH_RPC
271 select CPU_CACHE_V4WB
272 select CPU_CACHE_VIVT
273 select CPU_COPY_V4WB if MMU
275 select CPU_PABRT_LEGACY
276 select CPU_TLB_V4WB if MMU
278 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
279 is available at five speeds ranging from 100 MHz to 233 MHz.
280 More information is available at
281 <http://developer.intel.com/design/strong/sa110.htm>.
283 Say Y if you want support for the SA-110 processor.
291 select CPU_CACHE_V4WB
292 select CPU_CACHE_VIVT
294 select CPU_PABRT_LEGACY
295 select CPU_TLB_V4WB if MMU
302 select CPU_CACHE_VIVT
304 select CPU_PABRT_LEGACY
305 select CPU_TLB_V4WBI if MMU
307 # XScale Core Version 3
312 select CPU_CACHE_VIVT
314 select CPU_PABRT_LEGACY
315 select CPU_TLB_V4WBI if MMU
318 # Marvell PJ1 (Mohawk)
323 select CPU_CACHE_VIVT
324 select CPU_COPY_V4WB if MMU
326 select CPU_PABRT_LEGACY
327 select CPU_TLB_V4WBI if MMU
334 select CPU_CACHE_VIVT
335 select CPU_COPY_FEROCEON if MMU
337 select CPU_PABRT_LEGACY
338 select CPU_TLB_FEROCEON if MMU
340 config CPU_FEROCEON_OLD_ID
341 bool "Accept early Feroceon cores with an ARM926 ID"
342 depends on CPU_FEROCEON && !CPU_ARM926T
345 This enables the usage of some old Feroceon cores
346 for which the CPU ID is equal to the ARM926 ID.
347 Relevant for Feroceon-1850 and early Feroceon-2850.
361 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
365 select CPU_CACHE_VIPT
366 select CPU_COPY_V6 if MMU
368 select CPU_HAS_ASID if MMU
370 select CPU_TLB_V6 if MMU
374 bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
379 select CPU_CACHE_VIPT
380 select CPU_COPY_V6 if MMU
382 select CPU_HAS_ASID if MMU
384 select CPU_TLB_V6 if MMU
388 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
393 select CPU_CACHE_VIPT
394 select CPU_COPY_V6 if MMU
396 select CPU_HAS_ASID if MMU
398 select CPU_TLB_V7 if MMU
402 # There are no CPUs available with MMU that don't implement an ARM ISA:
405 Select this if your CPU doesn't support the 32 bit ARM instructions.
407 # Figure out what processor architecture version we should be using.
408 # This defines the compiler instruction set which depends on the machine type.
411 select CPU_USE_DOMAINS if MMU
412 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
413 select TLS_REG_EMUL if SMP || !MMU
417 select CPU_USE_DOMAINS if MMU
418 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
419 select TLS_REG_EMUL if SMP || !MMU
423 select CPU_USE_DOMAINS if MMU
424 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
425 select TLS_REG_EMUL if SMP || !MMU
429 select CPU_USE_DOMAINS if MMU
430 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
431 select TLS_REG_EMUL if SMP || !MMU
435 select CPU_USE_DOMAINS if CPU_V6 && MMU
436 select TLS_REG_EMUL if !CPU_32v6K && !MMU
445 config CPU_ABRT_NOMMU
460 config CPU_ABRT_EV5TJ
469 config CPU_PABRT_LEGACY
482 config CPU_CACHE_V4WT
485 config CPU_CACHE_V4WB
494 config CPU_CACHE_VIVT
497 config CPU_CACHE_VIPT
504 # The copy-page model
511 config CPU_COPY_FEROCEON
520 # This selects the TLB model
524 ARM Architecture Version 4 TLB with writethrough cache.
529 ARM Architecture Version 4 TLB with writeback cache.
534 ARM Architecture Version 4 TLB with writeback cache and invalidate
535 instruction cache entry.
537 config CPU_TLB_FEROCEON
540 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
545 Faraday ARM FA526 architecture, unified TLB with writeback cache
546 and invalidate instruction cache entry. Branch target buffer is
555 config VERIFY_PERMISSION_FAULT
562 This indicates whether the CPU has the ASID register; used to
563 tag TLB and possibly cache entries.
568 Processor has the CP15 register.
574 Processor has the CP15 register, which has MMU related registers.
580 Processor has the CP15 register, which has MPU related registers.
582 config CPU_USE_DOMAINS
585 This option enables or disables the use of domain switching
586 via the set_fs() function.
589 # CPU supports 36-bit I/O
594 comment "Processor Features"
597 bool "Support for the Large Physical Address Extension"
598 depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
599 !CPU_32v4 && !CPU_32v3
601 Say Y if you have an ARMv7 processor supporting the LPAE page
602 table format and you would like to access memory beyond the
603 4GB limit. The resulting kernel image will not run on
604 processors without the LPA extension.
608 config ARCH_PHYS_ADDR_T_64BIT
611 config ARCH_DMA_ADDR_T_64BIT
615 bool "Support Thumb user binaries" if !CPU_THUMBONLY
616 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON
619 Say Y if you want to include kernel support for running user space
622 The Thumb instruction set is a compressed form of the standard ARM
623 instruction set resulting in smaller binaries at the expense of
624 slightly less efficient code.
626 If you don't know what this all is, saying Y is a safe choice.
629 bool "Enable ThumbEE CPU extension"
632 Say Y here if you have a CPU with the ThumbEE extension and code to
633 make use of it. Say N for code that can run on CPUs without ThumbEE.
640 Enable the kernel to make use of the ARM Virtualization
641 Extensions to install hypervisors without run-time firmware
644 A compliant bootloader is required in order to make maximum
645 use of this feature. Refer to Documentation/arm/Booting for
649 bool "Emulate SWP/SWPB instructions"
650 depends on !CPU_USE_DOMAINS && CPU_V7
652 select HAVE_PROC_CPU if PROC_FS
654 ARMv6 architecture deprecates use of the SWP/SWPB instructions.
655 ARMv7 multiprocessing extensions introduce the ability to disable
656 these instructions, triggering an undefined instruction exception
657 when executed. Say Y here to enable software emulation of these
658 instructions for userspace (not kernel) using LDREX/STREX.
659 Also creates /proc/cpu/swp_emulation for statistics.
661 In some older versions of glibc [<=2.8] SWP is used during futex
662 trylock() operations with the assumption that the code will not
663 be preempted. This invalid assumption may be more likely to fail
664 with SWP emulation enabled, leading to deadlock of the user
667 NOTE: when accessing uncached shared regions, LDREX/STREX rely
668 on an external transaction monitoring block called a global
669 monitor to maintain update atomicity. If your system does not
670 implement a global monitor, this option can cause programs that
671 perform SWP operations to uncached memory to deadlock.
675 config CPU_BIG_ENDIAN
676 bool "Build big-endian kernel"
677 depends on ARCH_SUPPORTS_BIG_ENDIAN
679 Say Y if you plan on running a kernel in big-endian mode.
680 Note that your board must be properly built and your board
681 port must properly enable any big-endian related features
682 of your chipset/board/processor.
684 config CPU_ENDIAN_BE8
686 depends on CPU_BIG_ENDIAN
687 default CPU_V6 || CPU_V6K || CPU_V7
689 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
691 config CPU_ENDIAN_BE32
693 depends on CPU_BIG_ENDIAN
694 default !CPU_ENDIAN_BE8
696 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
698 config CPU_HIGH_VECTOR
699 depends on !MMU && CPU_CP15 && !CPU_ARM740T
700 bool "Select the High exception vector"
702 Say Y here to select high exception vector(0xFFFF0000~).
703 The exception vector can vary depending on the platform
704 design in nommu mode. If your platform needs to select
705 high exception vector, say Y.
706 Otherwise or if you are unsure, say N, and the low exception
707 vector (0x00000000~) will be used.
709 config CPU_ICACHE_DISABLE
710 bool "Disable I-Cache (I-bit)"
711 depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
713 Say Y here to disable the processor instruction cache. Unless
714 you have a reason not to or are unsure, say N.
716 config CPU_DCACHE_DISABLE
717 bool "Disable D-Cache (C-bit)"
720 Say Y here to disable the processor data cache. Unless
721 you have a reason not to or are unsure, say N.
723 config CPU_DCACHE_SIZE
725 depends on CPU_ARM740T || CPU_ARM946E
726 default 0x00001000 if CPU_ARM740T
727 default 0x00002000 # default size for ARM946E-S
729 Some cores are synthesizable to have various sized cache. For
730 ARM946E-S case, it can vary from 0KB to 1MB.
731 To support such cache operations, it is efficient to know the size
733 If your SoC is configured to have a different size, define the value
734 here with proper conditions.
736 config CPU_DCACHE_WRITETHROUGH
737 bool "Force write through D-cache"
738 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
739 default y if CPU_ARM925T
741 Say Y here to use the data cache in writethrough mode. Unless you
742 specifically require this or are unsure, say N.
744 config CPU_CACHE_ROUND_ROBIN
745 bool "Round robin I and D cache replacement algorithm"
746 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
748 Say Y here to use the predictable round-robin cache replacement
749 policy. Unless you specifically require this or are unsure, say N.
751 config CPU_BPREDICT_DISABLE
752 bool "Disable branch prediction"
753 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
755 Say Y here to disable branch prediction. If unsure, say N.
760 An SMP system using a pre-ARMv6 processor (there are apparently
761 a few prototypes like that in existence) and therefore access to
762 that required register must be emulated.
764 config NEEDS_SYSCALL_FOR_CMPXCHG
767 SMP on a pre-ARMv6 processor? Well OK then.
768 Forget about fast user space cmpxchg support.
769 It is just not possible.
771 config DMA_CACHE_RWFO
772 bool "Enable read/write for ownership DMA cache maintenance"
773 depends on CPU_V6K && SMP
776 The Snoop Control Unit on ARM11MPCore does not detect the
777 cache maintenance operations and the dma_{map,unmap}_area()
778 functions may leave stale cache entries on other CPUs. By
779 enabling this option, Read or Write For Ownership in the ARMv6
780 DMA cache maintenance functions is performed. These LDR/STR
781 instructions change the cache line state to shared or modified
782 so that the cache operation has the desired effect.
784 Note that the workaround is only valid on processors that do
785 not perform speculative loads into the D-cache. For such
786 processors, if cache maintenance operations are not broadcast
787 in hardware, other workarounds are needed (e.g. cache
788 maintenance broadcasting in software via FIQ).
793 config OUTER_CACHE_SYNC
796 The outer cache has a outer_cache_fns.sync function pointer
797 that can be used to drain the write buffer of the outer cache.
799 config CACHE_FEROCEON_L2
800 bool "Enable the Feroceon L2 cache controller"
801 depends on ARCH_KIRKWOOD || ARCH_MV78XX0
805 This option enables the Feroceon L2 cache controller.
807 config CACHE_FEROCEON_L2_WRITETHROUGH
808 bool "Force Feroceon L2 cache write through"
809 depends on CACHE_FEROCEON_L2
811 Say Y here to use the Feroceon L2 cache in writethrough mode.
812 Unless you specifically require this, say N for writeback mode.
814 config MIGHT_HAVE_CACHE_L2X0
817 This option should be selected by machines which have a L2x0
818 or PL310 cache controller, but where its use is optional.
820 The only effect of this option is to make CACHE_L2X0 and
821 related options available to the user for configuration.
823 Boards or SoCs which always require the cache controller
824 support to be present should select CACHE_L2X0 directly
825 instead of this option, thus preventing the user from
826 inadvertently configuring a broken kernel.
829 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
830 default MIGHT_HAVE_CACHE_L2X0
832 select OUTER_CACHE_SYNC
834 This option enables the L2x0 PrimeCell.
838 depends on CACHE_L2X0
839 default y if CPU_V7 && !(CPU_V6 || CPU_V6K)
841 This option enables optimisations for the PL310 cache
845 bool "Enable the Tauros2 L2 cache controller"
846 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
850 This option enables the Tauros2 L2 cache controller (as
854 bool "Enable the L2 cache on XScale3"
859 This option enables the L2 cache on XScale3.
861 config ARM_L1_CACHE_SHIFT_6
865 Setting ARM L1 cache line size to 64 Bytes.
867 config ARM_L1_CACHE_SHIFT
869 default 6 if ARM_L1_CACHE_SHIFT_6
872 config ARM_DMA_MEM_BUFFERABLE
873 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
874 depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
875 MACH_REALVIEW_PB11MP)
876 default y if CPU_V6 || CPU_V6K || CPU_V7
878 Historically, the kernel has used strongly ordered mappings to
879 provide DMA coherent memory. With the advent of ARMv7, mapping
880 memory with differing types results in unpredictable behaviour,
881 so on these CPUs, this option is forced on.
883 Multiple mappings with differing attributes is also unpredictable
884 on ARMv6 CPUs, but since they do not have aggressive speculative
885 prefetch, no harm appears to occur.
887 However, drivers may be missing the necessary barriers for ARMv6,
888 and therefore turning this on may result in unpredictable driver
889 behaviour. Therefore, we offer this as an option.
891 You are recommended say 'Y' here and debug any affected drivers.
893 config ARCH_HAS_BARRIERS
896 This option allows the use of custom mandatory barriers
897 included via the mach/barriers.h file.