2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
14 #include <linux/bug.h>
15 #include <linux/compiler.h>
16 #include <linux/kexec.h>
17 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
21 #include <linux/sched.h>
22 #include <linux/smp.h>
23 #include <linux/spinlock.h>
24 #include <linux/kallsyms.h>
25 #include <linux/bootmem.h>
26 #include <linux/interrupt.h>
27 #include <linux/ptrace.h>
28 #include <linux/kgdb.h>
29 #include <linux/kdebug.h>
30 #include <linux/kprobes.h>
31 #include <linux/notifier.h>
32 #include <linux/kdb.h>
33 #include <linux/irq.h>
34 #include <linux/perf_event.h>
36 #include <asm/bootinfo.h>
37 #include <asm/branch.h>
38 #include <asm/break.h>
43 #include <asm/fpu_emulator.h>
44 #include <asm/mipsregs.h>
45 #include <asm/mipsmtregs.h>
46 #include <asm/module.h>
47 #include <asm/pgtable.h>
48 #include <asm/ptrace.h>
49 #include <asm/sections.h>
50 #include <asm/tlbdebug.h>
51 #include <asm/traps.h>
52 #include <asm/uaccess.h>
53 #include <asm/watch.h>
54 #include <asm/mmu_context.h>
55 #include <asm/types.h>
56 #include <asm/stacktrace.h>
59 extern void check_wait(void);
60 extern asmlinkage
void r4k_wait(void);
61 extern asmlinkage
void rollback_handle_int(void);
62 extern asmlinkage
void handle_int(void);
63 extern u32 handle_tlbl
[];
64 extern u32 handle_tlbs
[];
65 extern u32 handle_tlbm
[];
66 extern asmlinkage
void handle_adel(void);
67 extern asmlinkage
void handle_ades(void);
68 extern asmlinkage
void handle_ibe(void);
69 extern asmlinkage
void handle_dbe(void);
70 extern asmlinkage
void handle_sys(void);
71 extern asmlinkage
void handle_bp(void);
72 extern asmlinkage
void handle_ri(void);
73 extern asmlinkage
void handle_ri_rdhwr_vivt(void);
74 extern asmlinkage
void handle_ri_rdhwr(void);
75 extern asmlinkage
void handle_cpu(void);
76 extern asmlinkage
void handle_ov(void);
77 extern asmlinkage
void handle_tr(void);
78 extern asmlinkage
void handle_fpe(void);
79 extern asmlinkage
void handle_mdmx(void);
80 extern asmlinkage
void handle_watch(void);
81 extern asmlinkage
void handle_mt(void);
82 extern asmlinkage
void handle_dsp(void);
83 extern asmlinkage
void handle_mcheck(void);
84 extern asmlinkage
void handle_reserved(void);
86 void (*board_be_init
)(void);
87 int (*board_be_handler
)(struct pt_regs
*regs
, int is_fixup
);
88 void (*board_nmi_handler_setup
)(void);
89 void (*board_ejtag_handler_setup
)(void);
90 void (*board_bind_eic_interrupt
)(int irq
, int regset
);
91 void (*board_ebase_setup
)(void);
92 void __cpuinitdata(*board_cache_error_setup
)(void);
94 static void show_raw_backtrace(unsigned long reg29
)
96 unsigned long *sp
= (unsigned long *)(reg29
& ~3);
99 printk("Call Trace:");
100 #ifdef CONFIG_KALLSYMS
103 while (!kstack_end(sp
)) {
104 unsigned long __user
*p
=
105 (unsigned long __user
*)(unsigned long)sp
++;
106 if (__get_user(addr
, p
)) {
107 printk(" (Bad stack address)");
110 if (__kernel_text_address(addr
))
116 #ifdef CONFIG_KALLSYMS
118 static int __init
set_raw_show_trace(char *str
)
123 __setup("raw_show_trace", set_raw_show_trace
);
126 static void show_backtrace(struct task_struct
*task
, const struct pt_regs
*regs
)
128 unsigned long sp
= regs
->regs
[29];
129 unsigned long ra
= regs
->regs
[31];
130 unsigned long pc
= regs
->cp0_epc
;
135 if (raw_show_trace
|| !__kernel_text_address(pc
)) {
136 show_raw_backtrace(sp
);
139 printk("Call Trace:\n");
142 pc
= unwind_stack(task
, &sp
, pc
, &ra
);
148 * This routine abuses get_user()/put_user() to reference pointers
149 * with at least a bit of error checking ...
151 static void show_stacktrace(struct task_struct
*task
,
152 const struct pt_regs
*regs
)
154 const int field
= 2 * sizeof(unsigned long);
157 unsigned long __user
*sp
= (unsigned long __user
*)regs
->regs
[29];
161 while ((unsigned long) sp
& (PAGE_SIZE
- 1)) {
162 if (i
&& ((i
% (64 / field
)) == 0))
169 if (__get_user(stackdata
, sp
++)) {
170 printk(" (Bad stack address)");
174 printk(" %0*lx", field
, stackdata
);
178 show_backtrace(task
, regs
);
181 void show_stack(struct task_struct
*task
, unsigned long *sp
)
185 regs
.regs
[29] = (unsigned long)sp
;
189 if (task
&& task
!= current
) {
190 regs
.regs
[29] = task
->thread
.reg29
;
192 regs
.cp0_epc
= task
->thread
.reg31
;
193 #ifdef CONFIG_KGDB_KDB
194 } else if (atomic_read(&kgdb_active
) != -1 &&
196 memcpy(®s
, kdb_current_regs
, sizeof(regs
));
197 #endif /* CONFIG_KGDB_KDB */
199 prepare_frametrace(®s
);
202 show_stacktrace(task
, ®s
);
205 static void show_code(unsigned int __user
*pc
)
208 unsigned short __user
*pc16
= NULL
;
212 if ((unsigned long)pc
& 1)
213 pc16
= (unsigned short __user
*)((unsigned long)pc
& ~1);
214 for(i
= -3 ; i
< 6 ; i
++) {
216 if (pc16
? __get_user(insn
, pc16
+ i
) : __get_user(insn
, pc
+ i
)) {
217 printk(" (Bad address in epc)\n");
220 printk("%c%0*x%c", (i
?' ':'<'), pc16
? 4 : 8, insn
, (i
?' ':'>'));
224 static void __show_regs(const struct pt_regs
*regs
)
226 const int field
= 2 * sizeof(unsigned long);
227 unsigned int cause
= regs
->cp0_cause
;
230 show_regs_print_info(KERN_DEFAULT
);
233 * Saved main processor registers
235 for (i
= 0; i
< 32; ) {
239 printk(" %0*lx", field
, 0UL);
240 else if (i
== 26 || i
== 27)
241 printk(" %*s", field
, "");
243 printk(" %0*lx", field
, regs
->regs
[i
]);
250 #ifdef CONFIG_CPU_HAS_SMARTMIPS
251 printk("Acx : %0*lx\n", field
, regs
->acx
);
253 printk("Hi : %0*lx\n", field
, regs
->hi
);
254 printk("Lo : %0*lx\n", field
, regs
->lo
);
257 * Saved cp0 registers
259 printk("epc : %0*lx %pS\n", field
, regs
->cp0_epc
,
260 (void *) regs
->cp0_epc
);
261 printk(" %s\n", print_tainted());
262 printk("ra : %0*lx %pS\n", field
, regs
->regs
[31],
263 (void *) regs
->regs
[31]);
265 printk("Status: %08x ", (uint32_t) regs
->cp0_status
);
267 if (current_cpu_data
.isa_level
== MIPS_CPU_ISA_I
) {
268 if (regs
->cp0_status
& ST0_KUO
)
270 if (regs
->cp0_status
& ST0_IEO
)
272 if (regs
->cp0_status
& ST0_KUP
)
274 if (regs
->cp0_status
& ST0_IEP
)
276 if (regs
->cp0_status
& ST0_KUC
)
278 if (regs
->cp0_status
& ST0_IEC
)
281 if (regs
->cp0_status
& ST0_KX
)
283 if (regs
->cp0_status
& ST0_SX
)
285 if (regs
->cp0_status
& ST0_UX
)
287 switch (regs
->cp0_status
& ST0_KSU
) {
292 printk("SUPERVISOR ");
301 if (regs
->cp0_status
& ST0_ERL
)
303 if (regs
->cp0_status
& ST0_EXL
)
305 if (regs
->cp0_status
& ST0_IE
)
310 printk("Cause : %08x\n", cause
);
312 cause
= (cause
& CAUSEF_EXCCODE
) >> CAUSEB_EXCCODE
;
313 if (1 <= cause
&& cause
<= 5)
314 printk("BadVA : %0*lx\n", field
, regs
->cp0_badvaddr
);
316 printk("PrId : %08x (%s)\n", read_c0_prid(),
321 * FIXME: really the generic show_regs should take a const pointer argument.
323 void show_regs(struct pt_regs
*regs
)
325 __show_regs((struct pt_regs
*)regs
);
328 void show_registers(struct pt_regs
*regs
)
330 const int field
= 2 * sizeof(unsigned long);
334 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
335 current
->comm
, current
->pid
, current_thread_info(), current
,
336 field
, current_thread_info()->tp_value
);
337 if (cpu_has_userlocal
) {
340 tls
= read_c0_userlocal();
341 if (tls
!= current_thread_info()->tp_value
)
342 printk("*HwTLS: %0*lx\n", field
, tls
);
345 show_stacktrace(current
, regs
);
346 show_code((unsigned int __user
*) regs
->cp0_epc
);
350 static int regs_to_trapnr(struct pt_regs
*regs
)
352 return (regs
->cp0_cause
>> 2) & 0x1f;
355 static DEFINE_RAW_SPINLOCK(die_lock
);
357 void __noreturn
die(const char *str
, struct pt_regs
*regs
)
359 static int die_counter
;
361 #ifdef CONFIG_MIPS_MT_SMTC
362 unsigned long dvpret
;
363 #endif /* CONFIG_MIPS_MT_SMTC */
367 if (notify_die(DIE_OOPS
, str
, regs
, 0, regs_to_trapnr(regs
), SIGSEGV
) == NOTIFY_STOP
)
371 raw_spin_lock_irq(&die_lock
);
372 #ifdef CONFIG_MIPS_MT_SMTC
374 #endif /* CONFIG_MIPS_MT_SMTC */
376 #ifdef CONFIG_MIPS_MT_SMTC
377 mips_mt_regdump(dvpret
);
378 #endif /* CONFIG_MIPS_MT_SMTC */
380 printk("%s[#%d]:\n", str
, ++die_counter
);
381 show_registers(regs
);
382 add_taint(TAINT_DIE
, LOCKDEP_NOW_UNRELIABLE
);
383 raw_spin_unlock_irq(&die_lock
);
388 panic("Fatal exception in interrupt");
391 printk(KERN_EMERG
"Fatal exception: panic in 5 seconds");
393 panic("Fatal exception");
396 if (regs
&& kexec_should_crash(current
))
402 extern struct exception_table_entry __start___dbe_table
[];
403 extern struct exception_table_entry __stop___dbe_table
[];
406 " .section __dbe_table, \"a\"\n"
409 /* Given an address, look for it in the exception tables. */
410 static const struct exception_table_entry
*search_dbe_tables(unsigned long addr
)
412 const struct exception_table_entry
*e
;
414 e
= search_extable(__start___dbe_table
, __stop___dbe_table
- 1, addr
);
416 e
= search_module_dbetables(addr
);
420 asmlinkage
void do_be(struct pt_regs
*regs
)
422 const int field
= 2 * sizeof(unsigned long);
423 const struct exception_table_entry
*fixup
= NULL
;
424 int data
= regs
->cp0_cause
& 4;
425 int action
= MIPS_BE_FATAL
;
427 /* XXX For now. Fixme, this searches the wrong table ... */
428 if (data
&& !user_mode(regs
))
429 fixup
= search_dbe_tables(exception_epc(regs
));
432 action
= MIPS_BE_FIXUP
;
434 if (board_be_handler
)
435 action
= board_be_handler(regs
, fixup
!= NULL
);
438 case MIPS_BE_DISCARD
:
442 regs
->cp0_epc
= fixup
->nextinsn
;
451 * Assume it would be too dangerous to continue ...
453 printk(KERN_ALERT
"%s bus error, epc == %0*lx, ra == %0*lx\n",
454 data
? "Data" : "Instruction",
455 field
, regs
->cp0_epc
, field
, regs
->regs
[31]);
456 if (notify_die(DIE_OOPS
, "bus error", regs
, 0, regs_to_trapnr(regs
), SIGBUS
)
460 die_if_kernel("Oops", regs
);
461 force_sig(SIGBUS
, current
);
465 * ll/sc, rdhwr, sync emulation
468 #define OPCODE 0xfc000000
469 #define BASE 0x03e00000
470 #define RT 0x001f0000
471 #define OFFSET 0x0000ffff
472 #define LL 0xc0000000
473 #define SC 0xe0000000
474 #define SPEC0 0x00000000
475 #define SPEC3 0x7c000000
476 #define RD 0x0000f800
477 #define FUNC 0x0000003f
478 #define SYNC 0x0000000f
479 #define RDHWR 0x0000003b
481 /* microMIPS definitions */
482 #define MM_POOL32A_FUNC 0xfc00ffff
483 #define MM_RDHWR 0x00006b3c
484 #define MM_RS 0x001f0000
485 #define MM_RT 0x03e00000
488 * The ll_bit is cleared by r*_switch.S
492 struct task_struct
*ll_task
;
494 static inline int simulate_ll(struct pt_regs
*regs
, unsigned int opcode
)
496 unsigned long value
, __user
*vaddr
;
500 * analyse the ll instruction that just caused a ri exception
501 * and put the referenced address to addr.
504 /* sign extend offset */
505 offset
= opcode
& OFFSET
;
509 vaddr
= (unsigned long __user
*)
510 ((unsigned long)(regs
->regs
[(opcode
& BASE
) >> 21]) + offset
);
512 if ((unsigned long)vaddr
& 3)
514 if (get_user(value
, vaddr
))
519 if (ll_task
== NULL
|| ll_task
== current
) {
528 regs
->regs
[(opcode
& RT
) >> 16] = value
;
533 static inline int simulate_sc(struct pt_regs
*regs
, unsigned int opcode
)
535 unsigned long __user
*vaddr
;
540 * analyse the sc instruction that just caused a ri exception
541 * and put the referenced address to addr.
544 /* sign extend offset */
545 offset
= opcode
& OFFSET
;
549 vaddr
= (unsigned long __user
*)
550 ((unsigned long)(regs
->regs
[(opcode
& BASE
) >> 21]) + offset
);
551 reg
= (opcode
& RT
) >> 16;
553 if ((unsigned long)vaddr
& 3)
558 if (ll_bit
== 0 || ll_task
!= current
) {
566 if (put_user(regs
->regs
[reg
], vaddr
))
575 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
576 * opcodes are supposed to result in coprocessor unusable exceptions if
577 * executed on ll/sc-less processors. That's the theory. In practice a
578 * few processors such as NEC's VR4100 throw reserved instruction exceptions
579 * instead, so we're doing the emulation thing in both exception handlers.
581 static int simulate_llsc(struct pt_regs
*regs
, unsigned int opcode
)
583 if ((opcode
& OPCODE
) == LL
) {
584 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
,
586 return simulate_ll(regs
, opcode
);
588 if ((opcode
& OPCODE
) == SC
) {
589 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
,
591 return simulate_sc(regs
, opcode
);
594 return -1; /* Must be something else ... */
598 * Simulate trapping 'rdhwr' instructions to provide user accessible
599 * registers not implemented in hardware.
601 static int simulate_rdhwr(struct pt_regs
*regs
, int rd
, int rt
)
603 struct thread_info
*ti
= task_thread_info(current
);
605 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
,
608 case 0: /* CPU number */
609 regs
->regs
[rt
] = smp_processor_id();
611 case 1: /* SYNCI length */
612 regs
->regs
[rt
] = min(current_cpu_data
.dcache
.linesz
,
613 current_cpu_data
.icache
.linesz
);
615 case 2: /* Read count register */
616 regs
->regs
[rt
] = read_c0_count();
618 case 3: /* Count register resolution */
619 switch (current_cpu_data
.cputype
) {
629 regs
->regs
[rt
] = ti
->tp_value
;
636 static int simulate_rdhwr_normal(struct pt_regs
*regs
, unsigned int opcode
)
638 if ((opcode
& OPCODE
) == SPEC3
&& (opcode
& FUNC
) == RDHWR
) {
639 int rd
= (opcode
& RD
) >> 11;
640 int rt
= (opcode
& RT
) >> 16;
642 simulate_rdhwr(regs
, rd
, rt
);
650 static int simulate_rdhwr_mm(struct pt_regs
*regs
, unsigned short opcode
)
652 if ((opcode
& MM_POOL32A_FUNC
) == MM_RDHWR
) {
653 int rd
= (opcode
& MM_RS
) >> 16;
654 int rt
= (opcode
& MM_RT
) >> 21;
655 simulate_rdhwr(regs
, rd
, rt
);
663 static int simulate_sync(struct pt_regs
*regs
, unsigned int opcode
)
665 if ((opcode
& OPCODE
) == SPEC0
&& (opcode
& FUNC
) == SYNC
) {
666 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS
,
671 return -1; /* Must be something else ... */
674 asmlinkage
void do_ov(struct pt_regs
*regs
)
678 die_if_kernel("Integer overflow", regs
);
680 info
.si_code
= FPE_INTOVF
;
681 info
.si_signo
= SIGFPE
;
683 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
684 force_sig_info(SIGFPE
, &info
, current
);
687 int process_fpemu_return(int sig
, void __user
*fault_addr
)
689 if (sig
== SIGSEGV
|| sig
== SIGBUS
) {
690 struct siginfo si
= {0};
691 si
.si_addr
= fault_addr
;
693 if (sig
== SIGSEGV
) {
694 if (find_vma(current
->mm
, (unsigned long)fault_addr
))
695 si
.si_code
= SEGV_ACCERR
;
697 si
.si_code
= SEGV_MAPERR
;
699 si
.si_code
= BUS_ADRERR
;
701 force_sig_info(sig
, &si
, current
);
704 force_sig(sig
, current
);
712 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
714 asmlinkage
void do_fpe(struct pt_regs
*regs
, unsigned long fcr31
)
716 siginfo_t info
= {0};
718 if (notify_die(DIE_FP
, "FP exception", regs
, 0, regs_to_trapnr(regs
), SIGFPE
)
721 die_if_kernel("FP exception in kernel code", regs
);
723 if (fcr31
& FPU_CSR_UNI_X
) {
725 void __user
*fault_addr
= NULL
;
728 * Unimplemented operation exception. If we've got the full
729 * software emulator on-board, let's use it...
731 * Force FPU to dump state into task/thread context. We're
732 * moving a lot of data here for what is probably a single
733 * instruction, but the alternative is to pre-decode the FP
734 * register operands before invoking the emulator, which seems
735 * a bit extreme for what should be an infrequent event.
737 /* Ensure 'resume' not overwrite saved fp context again. */
740 /* Run the emulator */
741 sig
= fpu_emulator_cop1Handler(regs
, ¤t
->thread
.fpu
, 1,
745 * We can't allow the emulated instruction to leave any of
746 * the cause bit set in $fcr31.
748 current
->thread
.fpu
.fcr31
&= ~FPU_CSR_ALL_X
;
750 /* Restore the hardware register state */
751 own_fpu(1); /* Using the FPU again. */
753 /* If something went wrong, signal */
754 process_fpemu_return(sig
, fault_addr
);
757 } else if (fcr31
& FPU_CSR_INV_X
)
758 info
.si_code
= FPE_FLTINV
;
759 else if (fcr31
& FPU_CSR_DIV_X
)
760 info
.si_code
= FPE_FLTDIV
;
761 else if (fcr31
& FPU_CSR_OVF_X
)
762 info
.si_code
= FPE_FLTOVF
;
763 else if (fcr31
& FPU_CSR_UDF_X
)
764 info
.si_code
= FPE_FLTUND
;
765 else if (fcr31
& FPU_CSR_INE_X
)
766 info
.si_code
= FPE_FLTRES
;
768 info
.si_code
= __SI_FAULT
;
769 info
.si_signo
= SIGFPE
;
771 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
772 force_sig_info(SIGFPE
, &info
, current
);
775 static void do_trap_or_bp(struct pt_regs
*regs
, unsigned int code
,
781 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
782 if (kgdb_ll_trap(DIE_TRAP
, str
, regs
, code
, regs_to_trapnr(regs
), SIGTRAP
) == NOTIFY_STOP
)
784 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
786 if (notify_die(DIE_TRAP
, str
, regs
, code
, regs_to_trapnr(regs
), SIGTRAP
) == NOTIFY_STOP
)
790 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
791 * insns, even for trap and break codes that indicate arithmetic
792 * failures. Weird ...
793 * But should we continue the brokenness??? --macro
798 scnprintf(b
, sizeof(b
), "%s instruction in kernel code", str
);
799 die_if_kernel(b
, regs
);
800 if (code
== BRK_DIVZERO
)
801 info
.si_code
= FPE_INTDIV
;
803 info
.si_code
= FPE_INTOVF
;
804 info
.si_signo
= SIGFPE
;
806 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
807 force_sig_info(SIGFPE
, &info
, current
);
810 die_if_kernel("Kernel bug detected", regs
);
811 force_sig(SIGTRAP
, current
);
815 * Address errors may be deliberately induced by the FPU
816 * emulator to retake control of the CPU after executing the
817 * instruction in the delay slot of an emulated branch.
819 * Terminate if exception was recognized as a delay slot return
820 * otherwise handle as normal.
822 if (do_dsemulret(regs
))
825 die_if_kernel("Math emu break/trap", regs
);
826 force_sig(SIGTRAP
, current
);
829 scnprintf(b
, sizeof(b
), "%s instruction in kernel code", str
);
830 die_if_kernel(b
, regs
);
831 force_sig(SIGTRAP
, current
);
835 asmlinkage
void do_bp(struct pt_regs
*regs
)
837 unsigned int opcode
, bcode
;
841 if (get_isa16_mode(regs
->cp0_epc
)) {
843 epc
= exception_epc(regs
);
845 if ((__get_user(instr
[0], (u16 __user
*)msk_isa16_mode(epc
)) ||
846 (__get_user(instr
[1], (u16 __user
*)msk_isa16_mode(epc
+ 2)))))
848 opcode
= (instr
[0] << 16) | instr
[1];
851 if (__get_user(instr
[0], (u16 __user
*)msk_isa16_mode(epc
)))
853 bcode
= (instr
[0] >> 6) & 0x3f;
854 do_trap_or_bp(regs
, bcode
, "Break");
858 if (__get_user(opcode
, (unsigned int __user
*) exception_epc(regs
)))
863 * There is the ancient bug in the MIPS assemblers that the break
864 * code starts left to bit 16 instead to bit 6 in the opcode.
865 * Gas is bug-compatible, but not always, grrr...
866 * We handle both cases with a simple heuristics. --macro
868 bcode
= ((opcode
>> 6) & ((1 << 20) - 1));
869 if (bcode
>= (1 << 10))
873 * notify the kprobe handlers, if instruction is likely to
878 if (notify_die(DIE_BREAK
, "debug", regs
, bcode
, regs_to_trapnr(regs
), SIGTRAP
) == NOTIFY_STOP
)
882 case BRK_KPROBE_SSTEPBP
:
883 if (notify_die(DIE_SSTEPBP
, "single_step", regs
, bcode
, regs_to_trapnr(regs
), SIGTRAP
) == NOTIFY_STOP
)
891 do_trap_or_bp(regs
, bcode
, "Break");
895 force_sig(SIGSEGV
, current
);
898 asmlinkage
void do_tr(struct pt_regs
*regs
)
900 unsigned int opcode
, tcode
= 0;
902 unsigned long epc
= exception_epc(regs
);
904 if ((__get_user(instr
[0], (u16 __user
*)msk_isa16_mode(epc
))) ||
905 (__get_user(instr
[1], (u16 __user
*)msk_isa16_mode(epc
+ 2))))
907 opcode
= (instr
[0] << 16) | instr
[1];
909 /* Immediate versions don't provide a code. */
910 if (!(opcode
& OPCODE
)) {
911 if (get_isa16_mode(regs
->cp0_epc
))
913 tcode
= (opcode
>> 12) & 0x1f;
915 tcode
= ((opcode
>> 6) & ((1 << 10) - 1));
918 do_trap_or_bp(regs
, tcode
, "Trap");
922 force_sig(SIGSEGV
, current
);
925 asmlinkage
void do_ri(struct pt_regs
*regs
)
927 unsigned int __user
*epc
= (unsigned int __user
*)exception_epc(regs
);
928 unsigned long old_epc
= regs
->cp0_epc
;
929 unsigned long old31
= regs
->regs
[31];
930 unsigned int opcode
= 0;
933 if (notify_die(DIE_RI
, "RI Fault", regs
, 0, regs_to_trapnr(regs
), SIGILL
)
937 die_if_kernel("Reserved instruction in kernel code", regs
);
939 if (unlikely(compute_return_epc(regs
) < 0))
942 if (get_isa16_mode(regs
->cp0_epc
)) {
943 unsigned short mmop
[2] = { 0 };
945 if (unlikely(get_user(mmop
[0], epc
) < 0))
947 if (unlikely(get_user(mmop
[1], epc
) < 0))
949 opcode
= (mmop
[0] << 16) | mmop
[1];
952 status
= simulate_rdhwr_mm(regs
, opcode
);
954 if (unlikely(get_user(opcode
, epc
) < 0))
957 if (!cpu_has_llsc
&& status
< 0)
958 status
= simulate_llsc(regs
, opcode
);
961 status
= simulate_rdhwr_normal(regs
, opcode
);
964 status
= simulate_sync(regs
, opcode
);
970 if (unlikely(status
> 0)) {
971 regs
->cp0_epc
= old_epc
; /* Undo skip-over. */
972 regs
->regs
[31] = old31
;
973 force_sig(status
, current
);
978 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
979 * emulated more than some threshold number of instructions, force migration to
980 * a "CPU" that has FP support.
982 static void mt_ase_fp_affinity(void)
984 #ifdef CONFIG_MIPS_MT_FPAFF
985 if (mt_fpemul_threshold
> 0 &&
986 ((current
->thread
.emulated_fp
++ > mt_fpemul_threshold
))) {
988 * If there's no FPU present, or if the application has already
989 * restricted the allowed set to exclude any CPUs with FPUs,
990 * we'll skip the procedure.
992 if (cpus_intersects(current
->cpus_allowed
, mt_fpu_cpumask
)) {
995 current
->thread
.user_cpus_allowed
996 = current
->cpus_allowed
;
997 cpus_and(tmask
, current
->cpus_allowed
,
999 set_cpus_allowed_ptr(current
, &tmask
);
1000 set_thread_flag(TIF_FPUBOUND
);
1003 #endif /* CONFIG_MIPS_MT_FPAFF */
1007 * No lock; only written during early bootup by CPU 0.
1009 static RAW_NOTIFIER_HEAD(cu2_chain
);
1011 int __ref
register_cu2_notifier(struct notifier_block
*nb
)
1013 return raw_notifier_chain_register(&cu2_chain
, nb
);
1016 int cu2_notifier_call_chain(unsigned long val
, void *v
)
1018 return raw_notifier_call_chain(&cu2_chain
, val
, v
);
1021 static int default_cu2_call(struct notifier_block
*nfb
, unsigned long action
,
1024 struct pt_regs
*regs
= data
;
1028 die_if_kernel("Unhandled kernel unaligned access or invalid "
1029 "instruction", regs
);
1033 force_sig(SIGILL
, current
);
1039 asmlinkage
void do_cpu(struct pt_regs
*regs
)
1041 unsigned int __user
*epc
;
1042 unsigned long old_epc
, old31
;
1043 unsigned int opcode
;
1046 unsigned long __maybe_unused flags
;
1048 die_if_kernel("do_cpu invoked from kernel context!", regs
);
1050 cpid
= (regs
->cp0_cause
>> CAUSEB_CE
) & 3;
1054 epc
= (unsigned int __user
*)exception_epc(regs
);
1055 old_epc
= regs
->cp0_epc
;
1056 old31
= regs
->regs
[31];
1060 if (unlikely(compute_return_epc(regs
) < 0))
1063 if (get_isa16_mode(regs
->cp0_epc
)) {
1064 unsigned short mmop
[2] = { 0 };
1066 if (unlikely(get_user(mmop
[0], epc
) < 0))
1068 if (unlikely(get_user(mmop
[1], epc
) < 0))
1070 opcode
= (mmop
[0] << 16) | mmop
[1];
1073 status
= simulate_rdhwr_mm(regs
, opcode
);
1075 if (unlikely(get_user(opcode
, epc
) < 0))
1078 if (!cpu_has_llsc
&& status
< 0)
1079 status
= simulate_llsc(regs
, opcode
);
1082 status
= simulate_rdhwr_normal(regs
, opcode
);
1088 if (unlikely(status
> 0)) {
1089 regs
->cp0_epc
= old_epc
; /* Undo skip-over. */
1090 regs
->regs
[31] = old31
;
1091 force_sig(status
, current
);
1098 * Old (MIPS I and MIPS II) processors will set this code
1099 * for COP1X opcode instructions that replaced the original
1100 * COP3 space. We don't limit COP1 space instructions in
1101 * the emulator according to the CPU ISA, so we want to
1102 * treat COP1X instructions consistently regardless of which
1103 * code the CPU chose. Therefore we redirect this trap to
1104 * the FP emulator too.
1106 * Then some newer FPU-less processors use this code
1107 * erroneously too, so they are covered by this choice
1110 if (raw_cpu_has_fpu
)
1115 if (used_math()) /* Using the FPU again. */
1117 else { /* First time FPU user. */
1122 if (!raw_cpu_has_fpu
) {
1124 void __user
*fault_addr
= NULL
;
1125 sig
= fpu_emulator_cop1Handler(regs
,
1126 ¤t
->thread
.fpu
,
1128 if (!process_fpemu_return(sig
, fault_addr
))
1129 mt_ase_fp_affinity();
1135 raw_notifier_call_chain(&cu2_chain
, CU2_EXCEPTION
, regs
);
1139 force_sig(SIGILL
, current
);
1142 asmlinkage
void do_mdmx(struct pt_regs
*regs
)
1144 force_sig(SIGILL
, current
);
1148 * Called with interrupts disabled.
1150 asmlinkage
void do_watch(struct pt_regs
*regs
)
1155 * Clear WP (bit 22) bit of cause register so we don't loop
1158 cause
= read_c0_cause();
1159 cause
&= ~(1 << 22);
1160 write_c0_cause(cause
);
1163 * If the current thread has the watch registers loaded, save
1164 * their values and send SIGTRAP. Otherwise another thread
1165 * left the registers set, clear them and continue.
1167 if (test_tsk_thread_flag(current
, TIF_LOAD_WATCH
)) {
1168 mips_read_watch_registers();
1170 force_sig(SIGTRAP
, current
);
1172 mips_clear_watch_registers();
1177 asmlinkage
void do_mcheck(struct pt_regs
*regs
)
1179 const int field
= 2 * sizeof(unsigned long);
1180 int multi_match
= regs
->cp0_status
& ST0_TS
;
1185 printk("Index : %0x\n", read_c0_index());
1186 printk("Pagemask: %0x\n", read_c0_pagemask());
1187 printk("EntryHi : %0*lx\n", field
, read_c0_entryhi());
1188 printk("EntryLo0: %0*lx\n", field
, read_c0_entrylo0());
1189 printk("EntryLo1: %0*lx\n", field
, read_c0_entrylo1());
1194 show_code((unsigned int __user
*) regs
->cp0_epc
);
1197 * Some chips may have other causes of machine check (e.g. SB1
1200 panic("Caught Machine Check exception - %scaused by multiple "
1201 "matching entries in the TLB.",
1202 (multi_match
) ? "" : "not ");
1205 asmlinkage
void do_mt(struct pt_regs
*regs
)
1209 subcode
= (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT
)
1210 >> VPECONTROL_EXCPT_SHIFT
;
1213 printk(KERN_DEBUG
"Thread Underflow\n");
1216 printk(KERN_DEBUG
"Thread Overflow\n");
1219 printk(KERN_DEBUG
"Invalid YIELD Qualifier\n");
1222 printk(KERN_DEBUG
"Gating Storage Exception\n");
1225 printk(KERN_DEBUG
"YIELD Scheduler Exception\n");
1228 printk(KERN_DEBUG
"Gating Storage Scheduler Exception\n");
1231 printk(KERN_DEBUG
"*** UNKNOWN THREAD EXCEPTION %d ***\n",
1235 die_if_kernel("MIPS MT Thread exception in kernel", regs
);
1237 force_sig(SIGILL
, current
);
1241 asmlinkage
void do_dsp(struct pt_regs
*regs
)
1244 panic("Unexpected DSP exception");
1246 force_sig(SIGILL
, current
);
1249 asmlinkage
void do_reserved(struct pt_regs
*regs
)
1252 * Game over - no way to handle this if it ever occurs. Most probably
1253 * caused by a new unknown cpu type or after another deadly
1254 * hard/software error.
1257 panic("Caught reserved exception %ld - should not happen.",
1258 (regs
->cp0_cause
& 0x7f) >> 2);
1261 static int __initdata l1parity
= 1;
1262 static int __init
nol1parity(char *s
)
1267 __setup("nol1par", nol1parity
);
1268 static int __initdata l2parity
= 1;
1269 static int __init
nol2parity(char *s
)
1274 __setup("nol2par", nol2parity
);
1277 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1278 * it different ways.
1280 static inline void parity_protection_init(void)
1282 switch (current_cpu_type()) {
1288 #define ERRCTL_PE 0x80000000
1289 #define ERRCTL_L2P 0x00800000
1290 unsigned long errctl
;
1291 unsigned int l1parity_present
, l2parity_present
;
1293 errctl
= read_c0_ecc();
1294 errctl
&= ~(ERRCTL_PE
|ERRCTL_L2P
);
1296 /* probe L1 parity support */
1297 write_c0_ecc(errctl
| ERRCTL_PE
);
1298 back_to_back_c0_hazard();
1299 l1parity_present
= (read_c0_ecc() & ERRCTL_PE
);
1301 /* probe L2 parity support */
1302 write_c0_ecc(errctl
|ERRCTL_L2P
);
1303 back_to_back_c0_hazard();
1304 l2parity_present
= (read_c0_ecc() & ERRCTL_L2P
);
1306 if (l1parity_present
&& l2parity_present
) {
1308 errctl
|= ERRCTL_PE
;
1309 if (l1parity
^ l2parity
)
1310 errctl
|= ERRCTL_L2P
;
1311 } else if (l1parity_present
) {
1313 errctl
|= ERRCTL_PE
;
1314 } else if (l2parity_present
) {
1316 errctl
|= ERRCTL_L2P
;
1318 /* No parity available */
1321 printk(KERN_INFO
"Writing ErrCtl register=%08lx\n", errctl
);
1323 write_c0_ecc(errctl
);
1324 back_to_back_c0_hazard();
1325 errctl
= read_c0_ecc();
1326 printk(KERN_INFO
"Readback ErrCtl register=%08lx\n", errctl
);
1328 if (l1parity_present
)
1329 printk(KERN_INFO
"Cache parity protection %sabled\n",
1330 (errctl
& ERRCTL_PE
) ? "en" : "dis");
1332 if (l2parity_present
) {
1333 if (l1parity_present
&& l1parity
)
1334 errctl
^= ERRCTL_L2P
;
1335 printk(KERN_INFO
"L2 cache parity protection %sabled\n",
1336 (errctl
& ERRCTL_L2P
) ? "en" : "dis");
1344 write_c0_ecc(0x80000000);
1345 back_to_back_c0_hazard();
1346 /* Set the PE bit (bit 31) in the c0_errctl register. */
1347 printk(KERN_INFO
"Cache parity protection %sabled\n",
1348 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1352 /* Clear the DE bit (bit 16) in the c0_status register. */
1353 printk(KERN_INFO
"Enable cache parity protection for "
1354 "MIPS 20KC/25KF CPUs.\n");
1355 clear_c0_status(ST0_DE
);
1362 asmlinkage
void cache_parity_error(void)
1364 const int field
= 2 * sizeof(unsigned long);
1365 unsigned int reg_val
;
1367 /* For the moment, report the problem and hang. */
1368 printk("Cache error exception:\n");
1369 printk("cp0_errorepc == %0*lx\n", field
, read_c0_errorepc());
1370 reg_val
= read_c0_cacheerr();
1371 printk("c0_cacheerr == %08x\n", reg_val
);
1373 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1374 reg_val
& (1<<30) ? "secondary" : "primary",
1375 reg_val
& (1<<31) ? "data" : "insn");
1376 printk("Error bits: %s%s%s%s%s%s%s\n",
1377 reg_val
& (1<<29) ? "ED " : "",
1378 reg_val
& (1<<28) ? "ET " : "",
1379 reg_val
& (1<<26) ? "EE " : "",
1380 reg_val
& (1<<25) ? "EB " : "",
1381 reg_val
& (1<<24) ? "EI " : "",
1382 reg_val
& (1<<23) ? "E1 " : "",
1383 reg_val
& (1<<22) ? "E0 " : "");
1384 printk("IDX: 0x%08x\n", reg_val
& ((1<<22)-1));
1386 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1387 if (reg_val
& (1<<22))
1388 printk("DErrAddr0: 0x%0*lx\n", field
, read_c0_derraddr0());
1390 if (reg_val
& (1<<23))
1391 printk("DErrAddr1: 0x%0*lx\n", field
, read_c0_derraddr1());
1394 panic("Can't handle the cache error!");
1398 * SDBBP EJTAG debug exception handler.
1399 * We skip the instruction and return to the next instruction.
1401 void ejtag_exception_handler(struct pt_regs
*regs
)
1403 const int field
= 2 * sizeof(unsigned long);
1404 unsigned long depc
, old_epc
, old_ra
;
1407 printk(KERN_DEBUG
"SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1408 depc
= read_c0_depc();
1409 debug
= read_c0_debug();
1410 printk(KERN_DEBUG
"c0_depc = %0*lx, DEBUG = %08x\n", field
, depc
, debug
);
1411 if (debug
& 0x80000000) {
1413 * In branch delay slot.
1414 * We cheat a little bit here and use EPC to calculate the
1415 * debug return address (DEPC). EPC is restored after the
1418 old_epc
= regs
->cp0_epc
;
1419 old_ra
= regs
->regs
[31];
1420 regs
->cp0_epc
= depc
;
1421 compute_return_epc(regs
);
1422 depc
= regs
->cp0_epc
;
1423 regs
->cp0_epc
= old_epc
;
1424 regs
->regs
[31] = old_ra
;
1427 write_c0_depc(depc
);
1430 printk(KERN_DEBUG
"\n\n----- Enable EJTAG single stepping ----\n\n");
1431 write_c0_debug(debug
| 0x100);
1436 * NMI exception handler.
1437 * No lock; only written during early bootup by CPU 0.
1439 static RAW_NOTIFIER_HEAD(nmi_chain
);
1441 int register_nmi_notifier(struct notifier_block
*nb
)
1443 return raw_notifier_chain_register(&nmi_chain
, nb
);
1446 void __noreturn
nmi_exception_handler(struct pt_regs
*regs
)
1448 raw_notifier_call_chain(&nmi_chain
, 0, regs
);
1450 printk("NMI taken!!!!\n");
1454 #define VECTORSPACING 0x100 /* for EI/VI mode */
1456 unsigned long ebase
;
1457 unsigned long exception_handlers
[32];
1458 unsigned long vi_handlers
[64];
1460 void __init
*set_except_vector(int n
, void *addr
)
1462 unsigned long handler
= (unsigned long) addr
;
1463 unsigned long old_handler
;
1465 #ifdef CONFIG_CPU_MICROMIPS
1467 * Only the TLB handlers are cache aligned with an even
1468 * address. All other handlers are on an odd address and
1469 * require no modification. Otherwise, MIPS32 mode will
1470 * be entered when handling any TLB exceptions. That
1471 * would be bad...since we must stay in microMIPS mode.
1473 if (!(handler
& 0x1))
1476 old_handler
= xchg(&exception_handlers
[n
], handler
);
1478 if (n
== 0 && cpu_has_divec
) {
1479 #ifdef CONFIG_CPU_MICROMIPS
1480 unsigned long jump_mask
= ~((1 << 27) - 1);
1482 unsigned long jump_mask
= ~((1 << 28) - 1);
1484 u32
*buf
= (u32
*)(ebase
+ 0x200);
1485 unsigned int k0
= 26;
1486 if ((handler
& jump_mask
) == ((ebase
+ 0x200) & jump_mask
)) {
1487 uasm_i_j(&buf
, handler
& ~jump_mask
);
1490 UASM_i_LA(&buf
, k0
, handler
);
1491 uasm_i_jr(&buf
, k0
);
1494 local_flush_icache_range(ebase
+ 0x200, (unsigned long)buf
);
1496 return (void *)old_handler
;
1499 static void do_default_vi(void)
1501 show_regs(get_irq_regs());
1502 panic("Caught unexpected vectored interrupt.");
1505 static void *set_vi_srs_handler(int n
, vi_handler_t addr
, int srs
)
1507 unsigned long handler
;
1508 unsigned long old_handler
= vi_handlers
[n
];
1509 int srssets
= current_cpu_data
.srsets
;
1513 BUG_ON(!cpu_has_veic
&& !cpu_has_vint
);
1514 BUG_ON((n
< 0) && (n
> 9));
1517 handler
= (unsigned long) do_default_vi
;
1520 handler
= (unsigned long) addr
;
1521 vi_handlers
[n
] = handler
;
1523 b
= (unsigned char *)(ebase
+ 0x200 + n
*VECTORSPACING
);
1526 panic("Shadow register set %d not supported", srs
);
1529 if (board_bind_eic_interrupt
)
1530 board_bind_eic_interrupt(n
, srs
);
1531 } else if (cpu_has_vint
) {
1532 /* SRSMap is only defined if shadow sets are implemented */
1534 change_c0_srsmap(0xf << n
*4, srs
<< n
*4);
1539 * If no shadow set is selected then use the default handler
1540 * that does normal register saving and standard interrupt exit
1542 extern char except_vec_vi
, except_vec_vi_lui
;
1543 extern char except_vec_vi_ori
, except_vec_vi_end
;
1544 extern char rollback_except_vec_vi
;
1545 char *vec_start
= (cpu_wait
== r4k_wait
) ?
1546 &rollback_except_vec_vi
: &except_vec_vi
;
1547 #ifdef CONFIG_MIPS_MT_SMTC
1549 * We need to provide the SMTC vectored interrupt handler
1550 * not only with the address of the handler, but with the
1551 * Status.IM bit to be masked before going there.
1553 extern char except_vec_vi_mori
;
1554 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1555 const int mori_offset
= &except_vec_vi_mori
- vec_start
+ 2;
1557 const int mori_offset
= &except_vec_vi_mori
- vec_start
;
1559 #endif /* CONFIG_MIPS_MT_SMTC */
1560 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1561 const int lui_offset
= &except_vec_vi_lui
- vec_start
+ 2;
1562 const int ori_offset
= &except_vec_vi_ori
- vec_start
+ 2;
1564 const int lui_offset
= &except_vec_vi_lui
- vec_start
;
1565 const int ori_offset
= &except_vec_vi_ori
- vec_start
;
1567 const int handler_len
= &except_vec_vi_end
- vec_start
;
1569 if (handler_len
> VECTORSPACING
) {
1571 * Sigh... panicing won't help as the console
1572 * is probably not configured :(
1574 panic("VECTORSPACING too small");
1577 set_handler(((unsigned long)b
- ebase
), vec_start
,
1578 #ifdef CONFIG_CPU_MICROMIPS
1583 #ifdef CONFIG_MIPS_MT_SMTC
1584 BUG_ON(n
> 7); /* Vector index %d exceeds SMTC maximum. */
1586 h
= (u16
*)(b
+ mori_offset
);
1588 #endif /* CONFIG_MIPS_MT_SMTC */
1589 h
= (u16
*)(b
+ lui_offset
);
1590 *h
= (handler
>> 16) & 0xffff;
1591 h
= (u16
*)(b
+ ori_offset
);
1592 *h
= (handler
& 0xffff);
1593 local_flush_icache_range((unsigned long)b
,
1594 (unsigned long)(b
+handler_len
));
1598 * In other cases jump directly to the interrupt handler. It
1599 * is the handler's responsibility to save registers if required
1600 * (eg hi/lo) and return from the exception using "eret".
1606 #ifdef CONFIG_CPU_MICROMIPS
1607 insn
= 0xd4000000 | (((u32
)handler
& 0x07ffffff) >> 1);
1609 insn
= 0x08000000 | (((u32
)handler
& 0x0fffffff) >> 2);
1611 h
[0] = (insn
>> 16) & 0xffff;
1612 h
[1] = insn
& 0xffff;
1615 local_flush_icache_range((unsigned long)b
,
1616 (unsigned long)(b
+8));
1619 return (void *)old_handler
;
1622 void *set_vi_handler(int n
, vi_handler_t addr
)
1624 return set_vi_srs_handler(n
, addr
, 0);
1627 extern void tlb_init(void);
1628 extern void flush_tlb_handlers(void);
1633 int cp0_compare_irq
;
1634 EXPORT_SYMBOL_GPL(cp0_compare_irq
);
1635 int cp0_compare_irq_shift
;
1638 * Performance counter IRQ or -1 if shared with timer
1640 int cp0_perfcount_irq
;
1641 EXPORT_SYMBOL_GPL(cp0_perfcount_irq
);
1643 static int __cpuinitdata noulri
;
1645 static int __init
ulri_disable(char *s
)
1647 pr_info("Disabling ulri\n");
1652 __setup("noulri", ulri_disable
);
1654 void __cpuinit
per_cpu_trap_init(bool is_boot_cpu
)
1656 unsigned int cpu
= smp_processor_id();
1657 unsigned int status_set
= ST0_CU0
;
1658 unsigned int hwrena
= cpu_hwrena_impl_bits
;
1659 unsigned long asid
= 0;
1660 #ifdef CONFIG_MIPS_MT_SMTC
1661 int secondaryTC
= 0;
1662 int bootTC
= (cpu
== 0);
1665 * Only do per_cpu_trap_init() for first TC of Each VPE.
1666 * Note that this hack assumes that the SMTC init code
1667 * assigns TCs consecutively and in ascending order.
1670 if (((read_c0_tcbind() & TCBIND_CURTC
) != 0) &&
1671 ((read_c0_tcbind() & TCBIND_CURVPE
) == cpu_data
[cpu
- 1].vpe_id
))
1673 #endif /* CONFIG_MIPS_MT_SMTC */
1676 * Disable coprocessors and select 32-bit or 64-bit addressing
1677 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1678 * flag that some firmware may have left set and the TS bit (for
1679 * IP27). Set XX for ISA IV code to work.
1682 status_set
|= ST0_FR
|ST0_KX
|ST0_SX
|ST0_UX
;
1684 if (current_cpu_data
.isa_level
& MIPS_CPU_ISA_IV
)
1685 status_set
|= ST0_XX
;
1687 status_set
|= ST0_MX
;
1689 change_c0_status(ST0_CU
|ST0_MX
|ST0_RE
|ST0_FR
|ST0_BEV
|ST0_TS
|ST0_KX
|ST0_SX
|ST0_UX
,
1692 if (cpu_has_mips_r2
)
1693 hwrena
|= 0x0000000f;
1695 if (!noulri
&& cpu_has_userlocal
)
1696 hwrena
|= (1 << 29);
1699 write_c0_hwrena(hwrena
);
1701 #ifdef CONFIG_MIPS_MT_SMTC
1703 #endif /* CONFIG_MIPS_MT_SMTC */
1705 if (cpu_has_veic
|| cpu_has_vint
) {
1706 unsigned long sr
= set_c0_status(ST0_BEV
);
1707 write_c0_ebase(ebase
);
1708 write_c0_status(sr
);
1709 /* Setting vector spacing enables EI/VI mode */
1710 change_c0_intctl(0x3e0, VECTORSPACING
);
1712 if (cpu_has_divec
) {
1713 if (cpu_has_mipsmt
) {
1714 unsigned int vpflags
= dvpe();
1715 set_c0_cause(CAUSEF_IV
);
1718 set_c0_cause(CAUSEF_IV
);
1722 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1724 * o read IntCtl.IPTI to determine the timer interrupt
1725 * o read IntCtl.IPPCI to determine the performance counter interrupt
1727 if (cpu_has_mips_r2
) {
1728 cp0_compare_irq_shift
= CAUSEB_TI
- CAUSEB_IP
;
1729 cp0_compare_irq
= (read_c0_intctl() >> INTCTLB_IPTI
) & 7;
1730 cp0_perfcount_irq
= (read_c0_intctl() >> INTCTLB_IPPCI
) & 7;
1731 if (cp0_perfcount_irq
== cp0_compare_irq
)
1732 cp0_perfcount_irq
= -1;
1734 cp0_compare_irq
= CP0_LEGACY_COMPARE_IRQ
;
1735 cp0_compare_irq_shift
= CP0_LEGACY_PERFCNT_IRQ
;
1736 cp0_perfcount_irq
= -1;
1739 #ifdef CONFIG_MIPS_MT_SMTC
1741 #endif /* CONFIG_MIPS_MT_SMTC */
1743 asid
= ASID_FIRST_VERSION
;
1744 cpu_data
[cpu
].asid_cache
= asid
;
1745 TLBMISS_HANDLER_SETUP();
1747 atomic_inc(&init_mm
.mm_count
);
1748 current
->active_mm
= &init_mm
;
1749 BUG_ON(current
->mm
);
1750 enter_lazy_tlb(&init_mm
, current
);
1752 #ifdef CONFIG_MIPS_MT_SMTC
1754 #endif /* CONFIG_MIPS_MT_SMTC */
1755 /* Boot CPU's cache setup in setup_arch(). */
1759 #ifdef CONFIG_MIPS_MT_SMTC
1760 } else if (!secondaryTC
) {
1762 * First TC in non-boot VPE must do subset of tlb_init()
1763 * for MMU countrol registers.
1765 write_c0_pagemask(PM_DEFAULT_MASK
);
1768 #endif /* CONFIG_MIPS_MT_SMTC */
1769 TLBMISS_HANDLER_SETUP();
1772 /* Install CPU exception handler */
1773 void __cpuinit
set_handler(unsigned long offset
, void *addr
, unsigned long size
)
1775 #ifdef CONFIG_CPU_MICROMIPS
1776 memcpy((void *)(ebase
+ offset
), ((unsigned char *)addr
- 1), size
);
1778 memcpy((void *)(ebase
+ offset
), addr
, size
);
1780 local_flush_icache_range(ebase
+ offset
, ebase
+ offset
+ size
);
1783 static char panic_null_cerr
[] __cpuinitdata
=
1784 "Trying to set NULL cache error exception handler";
1787 * Install uncached CPU exception handler.
1788 * This is suitable only for the cache error exception which is the only
1789 * exception handler that is being run uncached.
1791 void __cpuinit
set_uncached_handler(unsigned long offset
, void *addr
,
1794 unsigned long uncached_ebase
= CKSEG1ADDR(ebase
);
1797 panic(panic_null_cerr
);
1799 memcpy((void *)(uncached_ebase
+ offset
), addr
, size
);
1802 static int __initdata rdhwr_noopt
;
1803 static int __init
set_rdhwr_noopt(char *str
)
1809 __setup("rdhwr_noopt", set_rdhwr_noopt
);
1811 void __init
trap_init(void)
1813 extern char except_vec3_generic
;
1814 extern char except_vec4
;
1815 extern char except_vec3_r4000
;
1820 rollback
= (cpu_wait
== r4k_wait
);
1822 #if defined(CONFIG_KGDB)
1823 if (kgdb_early_setup
)
1824 return; /* Already done */
1827 if (cpu_has_veic
|| cpu_has_vint
) {
1828 unsigned long size
= 0x200 + VECTORSPACING
*64;
1829 ebase
= (unsigned long)
1830 __alloc_bootmem(size
, 1 << fls(size
), 0);
1832 #ifdef CONFIG_KVM_GUEST
1833 #define KVM_GUEST_KSEG0 0x40000000
1834 ebase
= KVM_GUEST_KSEG0
;
1838 if (cpu_has_mips_r2
)
1839 ebase
+= (read_c0_ebase() & 0x3ffff000);
1842 if (board_ebase_setup
)
1843 board_ebase_setup();
1844 per_cpu_trap_init(true);
1847 * Copy the generic exception handlers to their final destination.
1848 * This will be overriden later as suitable for a particular
1851 set_handler(0x180, &except_vec3_generic
, 0x80);
1854 * Setup default vectors
1856 for (i
= 0; i
<= 31; i
++)
1857 set_except_vector(i
, handle_reserved
);
1860 * Copy the EJTAG debug exception vector handler code to it's final
1863 if (cpu_has_ejtag
&& board_ejtag_handler_setup
)
1864 board_ejtag_handler_setup();
1867 * Only some CPUs have the watch exceptions.
1870 set_except_vector(23, handle_watch
);
1873 * Initialise interrupt handlers
1875 if (cpu_has_veic
|| cpu_has_vint
) {
1876 int nvec
= cpu_has_veic
? 64 : 8;
1877 for (i
= 0; i
< nvec
; i
++)
1878 set_vi_handler(i
, NULL
);
1880 else if (cpu_has_divec
)
1881 set_handler(0x200, &except_vec4
, 0x8);
1884 * Some CPUs can enable/disable for cache parity detection, but does
1885 * it different ways.
1887 parity_protection_init();
1890 * The Data Bus Errors / Instruction Bus Errors are signaled
1891 * by external hardware. Therefore these two exceptions
1892 * may have board specific handlers.
1897 set_except_vector(0, rollback
? rollback_handle_int
: handle_int
);
1898 set_except_vector(1, handle_tlbm
);
1899 set_except_vector(2, handle_tlbl
);
1900 set_except_vector(3, handle_tlbs
);
1902 set_except_vector(4, handle_adel
);
1903 set_except_vector(5, handle_ades
);
1905 set_except_vector(6, handle_ibe
);
1906 set_except_vector(7, handle_dbe
);
1908 set_except_vector(8, handle_sys
);
1909 set_except_vector(9, handle_bp
);
1910 set_except_vector(10, rdhwr_noopt
? handle_ri
:
1911 (cpu_has_vtag_icache
?
1912 handle_ri_rdhwr_vivt
: handle_ri_rdhwr
));
1913 set_except_vector(11, handle_cpu
);
1914 set_except_vector(12, handle_ov
);
1915 set_except_vector(13, handle_tr
);
1917 if (current_cpu_type() == CPU_R6000
||
1918 current_cpu_type() == CPU_R6000A
) {
1920 * The R6000 is the only R-series CPU that features a machine
1921 * check exception (similar to the R4000 cache error) and
1922 * unaligned ldc1/sdc1 exception. The handlers have not been
1923 * written yet. Well, anyway there is no R6000 machine on the
1924 * current list of targets for Linux/MIPS.
1925 * (Duh, crap, there is someone with a triple R6k machine)
1927 //set_except_vector(14, handle_mc);
1928 //set_except_vector(15, handle_ndc);
1932 if (board_nmi_handler_setup
)
1933 board_nmi_handler_setup();
1935 if (cpu_has_fpu
&& !cpu_has_nofpuex
)
1936 set_except_vector(15, handle_fpe
);
1938 set_except_vector(22, handle_mdmx
);
1941 set_except_vector(24, handle_mcheck
);
1944 set_except_vector(25, handle_mt
);
1946 set_except_vector(26, handle_dsp
);
1948 if (board_cache_error_setup
)
1949 board_cache_error_setup();
1952 /* Special exception: R4[04]00 uses also the divec space. */
1953 set_handler(0x180, &except_vec3_r4000
, 0x100);
1954 else if (cpu_has_4kex
)
1955 set_handler(0x180, &except_vec3_generic
, 0x80);
1957 set_handler(0x080, &except_vec3_generic
, 0x80);
1959 local_flush_icache_range(ebase
, ebase
+ 0x400);
1960 flush_tlb_handlers();
1962 sort_extable(__start___dbe_table
, __stop___dbe_table
);
1964 cu2_notifier(default_cu2_call
, 0x80000000); /* Run last */