arch/arm/mach-mvebu/system-controller.c

   1 /*
   2  * System controller support for Armada 370, 375 and XP platforms.
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2.  This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  *
  14  * The Armada 370, 375 and Armada XP SoCs have a range of
  15  * miscellaneous registers, that do not belong to a particular device,
  16  * but rather provide system-level features. This basic
  17  * system-controller driver provides a device tree binding for those
  18  * registers, and implements utility functions offering various
  19  * features related to those registers.
  20  *
  21  * For now, the feature set is limited to restarting the platform by a
  22  * soft-reset, but it might be extended in the future.
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/of_address.h>
  28 #include <linux/io.h>
  29 #include <linux/reboot.h>
  30 #include "common.h"
  31 #include "mvebu-soc-id.h"
  32 #include "pmsu.h"
  33
  34 #define ARMADA_375_CRYPT0_ENG_TARGET 41
  35 #define ARMADA_375_CRYPT0_ENG_ATTR    1
  36
  37 static void __iomem *system_controller_base;
  38 static phys_addr_t system_controller_phys_base;
  39
  40 struct mvebu_system_controller {
  41         u32 rstoutn_mask_offset;
  42         u32 system_soft_reset_offset;
  43
  44         u32 rstoutn_mask_reset_out_en;
  45         u32 system_soft_reset;
  46
  47         u32 resume_boot_addr;
  48
  49         u32 dev_id;
  50         u32 rev_id;
  51 };
  52 static struct mvebu_system_controller *mvebu_sc;
  53
  54 static const struct mvebu_system_controller armada_370_xp_system_controller = {
  55         .rstoutn_mask_offset = 0x60,
  56         .system_soft_reset_offset = 0x64,
  57         .rstoutn_mask_reset_out_en = 0x1,
  58         .system_soft_reset = 0x1,
  59         .dev_id = 0x38,
  60         .rev_id = 0x3c,
  61 };
  62
  63 static const struct mvebu_system_controller armada_375_system_controller = {
  64         .rstoutn_mask_offset = 0x54,
  65         .system_soft_reset_offset = 0x58,
  66         .rstoutn_mask_reset_out_en = 0x1,
  67         .system_soft_reset = 0x1,
  68         .resume_boot_addr = 0xd4,
  69         .dev_id = 0x38,
  70         .rev_id = 0x3c,
  71 };
  72
  73 static const struct mvebu_system_controller orion_system_controller = {
  74         .rstoutn_mask_offset = 0x108,
  75         .system_soft_reset_offset = 0x10c,
  76         .rstoutn_mask_reset_out_en = 0x4,
  77         .system_soft_reset = 0x1,
  78 };
  79
  80 static const struct of_device_id of_system_controller_table[] = {
  81         {
  82                 .compatible = "marvell,orion-system-controller",
  83                 .data = (void *) &orion_system_controller,
  84         }, {
  85                 .compatible = "marvell,armada-370-xp-system-controller",
  86                 .data = (void *) &armada_370_xp_system_controller,
  87         }, {
  88                 .compatible = "marvell,armada-375-system-controller",
  89                 .data = (void *) &armada_375_system_controller,
  90         },
  91         { /* end of list */ },
  92 };
  93
  94 void mvebu_restart(enum reboot_mode mode, const char *cmd)
  95 {
  96         if (!system_controller_base) {
  97                 pr_err("Cannot restart, system-controller not available: check the device tree\n");
  98         } else {
  99                 /*
 100                  * Enable soft reset to assert RSTOUTn.
 101                  */
 102                 writel(mvebu_sc->rstoutn_mask_reset_out_en,
 103                         system_controller_base +
 104                         mvebu_sc->rstoutn_mask_offset);
 105                 /*
 106                  * Assert soft reset.
 107                  */
 108                 writel(mvebu_sc->system_soft_reset,
 109                         system_controller_base +
 110                         mvebu_sc->system_soft_reset_offset);
 111         }
 112
 113         while (1)
 114                 ;
 115 }
 116
 117 int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev)
 118 {
 119         if (of_machine_is_compatible("marvell,armada380") &&
 120                 system_controller_base) {
 121                 *dev = readl(system_controller_base + mvebu_sc->dev_id) >> 16;
 122                 *rev = (readl(system_controller_base + mvebu_sc->rev_id) >> 8)
 123                         & 0xF;
 124                 return 0;
 125         } else
 126                 return -ENODEV;
 127 }
 128
 129 #if defined(CONFIG_SMP) && defined(CONFIG_MACH_MVEBU_V7)
 130 void mvebu_armada375_smp_wa_init(void)
 131 {
 132         u32 dev, rev;
 133         phys_addr_t resume_addr_reg;
 134
 135         if (mvebu_get_soc_id(&dev, &rev) != 0)
 136                 return;
 137
 138         if (rev != ARMADA_375_Z1_REV)
 139                 return;
 140
 141         resume_addr_reg = system_controller_phys_base +
 142                 mvebu_sc->resume_boot_addr;
 143         mvebu_setup_boot_addr_wa(ARMADA_375_CRYPT0_ENG_TARGET,
 144                                  ARMADA_375_CRYPT0_ENG_ATTR,
 145                                  resume_addr_reg);
 146 }
 147
 148 void mvebu_system_controller_set_cpu_boot_addr(void *boot_addr)
 149 {
 150         BUG_ON(system_controller_base == NULL);
 151         BUG_ON(mvebu_sc->resume_boot_addr == 0);
 152
 153         if (of_machine_is_compatible("marvell,armada375"))
 154                 mvebu_armada375_smp_wa_init();
 155
 156         writel(virt_to_phys(boot_addr), system_controller_base +
 157                mvebu_sc->resume_boot_addr);
 158 }
 159 #endif
 160
 161 static int __init mvebu_system_controller_init(void)
 162 {
 163         const struct of_device_id *match;
 164         struct device_node *np;
 165
 166         np = of_find_matching_node_and_match(NULL, of_system_controller_table,
 167                                              &match);
 168         if (np) {
 169                 struct resource res;
 170                 system_controller_base = of_iomap(np, 0);
 171                 of_address_to_resource(np, 0, &res);
 172                 system_controller_phys_base = res.start;
 173                 mvebu_sc = (struct mvebu_system_controller *)match->data;
 174                 of_node_put(np);
 175         }
 176
 177         return 0;
 178 }
 179
 180 early_initcall(mvebu_system_controller_init);