drivers/clk/rockchip/clk-mmc-phase.c

   1 /*
   2  * Copyright 2014 Google, Inc
   3  * Author: Alexandru M Stan <amstan@chromium.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/slab.h>
  17 #include <linux/clk.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/io.h>
  20 #include <linux/kernel.h>
  21 #include "clk.h"
  22
  23 struct rockchip_mmc_clock {
  24         struct clk_hw   hw;
  25         void __iomem    *reg;
  26         int             id;
  27         int             shift;
  28 };
  29
  30 #define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw)
  31
  32 #define RK3288_MMC_CLKGEN_DIV 2
  33
  34 static unsigned long rockchip_mmc_recalc(struct clk_hw *hw,
  35                                          unsigned long parent_rate)
  36 {
  37         return parent_rate / RK3288_MMC_CLKGEN_DIV;
  38 }
  39
  40 #define ROCKCHIP_MMC_DELAY_SEL BIT(10)
  41 #define ROCKCHIP_MMC_DEGREE_MASK 0x3
  42 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
  43 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
  44
  45 #define PSECS_PER_SEC 1000000000000LL
  46
  47 /*
  48  * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
  49  * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.
  50  */
  51 #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
  52
  53 static int rockchip_mmc_get_phase(struct clk_hw *hw)
  54 {
  55         struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
  56         unsigned long rate = clk_get_rate(hw->clk);
  57         u32 raw_value;
  58         u16 degrees;
  59         u32 delay_num = 0;
  60
  61         /* See the comment for rockchip_mmc_set_phase below */
  62         if (!rate) {
  63                 pr_err("%s: invalid clk rate\n", __func__);
  64                 return -EINVAL;
  65         }
  66
  67         raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
  68
  69         degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
  70
  71         if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
  72                 /* degrees/delaynum * 10000 */
  73                 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
  74                                         36 * (rate / 1000000);
  75
  76                 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
  77                 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
  78                 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000);
  79         }
  80
  81         return degrees % 360;
  82 }
  83
  84 static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)
  85 {
  86         struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
  87         unsigned long rate = clk_get_rate(hw->clk);
  88         u8 nineties, remainder;
  89         u8 delay_num;
  90         u32 raw_value;
  91         u32 delay;
  92
  93         /*
  94          * The below calculation is based on the output clock from
  95          * MMC host to the card, which expects the phase clock inherits
  96          * the clock rate from its parent, namely the output clock
  97          * provider of MMC host. However, things may go wrong if
  98          * (1) It is orphan.
  99          * (2) It is assigned to the wrong parent.
 100          *
 101          * This check help debug the case (1), which seems to be the
 102          * most likely problem we often face and which makes it difficult
 103          * for people to debug unstable mmc tuning results.
 104          */
 105         if (!rate) {
 106                 pr_err("%s: invalid clk rate\n", __func__);
 107                 return -EINVAL;
 108         }
 109
 110         nineties = degrees / 90;
 111         remainder = (degrees % 90);
 112
 113         /*
 114          * Due to the inexact nature of the "fine" delay, we might
 115          * actually go non-monotonic.  We don't go _too_ monotonic
 116          * though, so we should be OK.  Here are options of how we may
 117          * work:
 118          *
 119          * Ideally we end up with:
 120          *   1.0, 2.0, ..., 69.0, 70.0, ...,  89.0, 90.0
 121          *
 122          * On one extreme (if delay is actually 44ps):
 123          *   .73, 1.5, ..., 50.6, 51.3, ...,  65.3, 90.0
 124          * The other (if delay is actually 77ps):
 125          *   1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90
 126          *
 127          * It's possible we might make a delay that is up to 25
 128          * degrees off from what we think we're making.  That's OK
 129          * though because we should be REALLY far from any bad range.
 130          */
 131
 132         /*
 133          * Convert to delay; do a little extra work to make sure we
 134          * don't overflow 32-bit / 64-bit numbers.
 135          */
 136         delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */
 137         delay *= remainder;
 138         delay = DIV_ROUND_CLOSEST(delay,
 139                         (rate / 1000) * 36 *
 140                                 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10));
 141
 142         delay_num = (u8) min_t(u32, delay, 255);
 143
 144         raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
 145         raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
 146         raw_value |= nineties;
 147         writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift),
 148                mmc_clock->reg);
 149
 150         pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",
 151                 clk_hw_get_name(hw), degrees, delay_num,
 152                 mmc_clock->reg, raw_value>>(mmc_clock->shift),
 153                 rockchip_mmc_get_phase(hw)
 154         );
 155
 156         return 0;
 157 }
 158
 159 static const struct clk_ops rockchip_mmc_clk_ops = {
 160         .recalc_rate    = rockchip_mmc_recalc,
 161         .get_phase      = rockchip_mmc_get_phase,
 162         .set_phase      = rockchip_mmc_set_phase,
 163 };
 164
 165 struct clk *rockchip_clk_register_mmc(const char *name,
 166                                 const char *const *parent_names, u8 num_parents,
 167                                 void __iomem *reg, int shift)
 168 {
 169         struct clk_init_data init;
 170         struct rockchip_mmc_clock *mmc_clock;
 171         struct clk *clk;
 172
 173         mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL);
 174         if (!mmc_clock)
 175                 return ERR_PTR(-ENOMEM);
 176
 177         init.name = name;
 178         init.flags = 0;
 179         init.num_parents = num_parents;
 180         init.parent_names = parent_names;
 181         init.ops = &rockchip_mmc_clk_ops;
 182
 183         mmc_clock->hw.init = &init;
 184         mmc_clock->reg = reg;
 185         mmc_clock->shift = shift;
 186
 187         clk = clk_register(NULL, &mmc_clock->hw);
 188         if (IS_ERR(clk))
 189                 kfree(mmc_clock);
 190
 191         return clk;
 192 }