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ASoC: arizona: Correct handling of FLL theta in synchroniser mode
[linux/fpc-iii.git] / drivers / mmc / host / sdhci.c
blobcd65d474afa2bc300064f1214a0e478e90a7366d
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
25
26 #include <linux/leds.h>
27
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/sdio.h>
32 #include <linux/mmc/slot-gpio.h>
33
34 #include "sdhci.h"
35
36 #define DRIVER_NAME "sdhci"
37
38 #define DBG(f, x...) \
39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
40
41 #define MAX_TUNING_LOOP 40
42
43 static unsigned int debug_quirks = 0;
44 static unsigned int debug_quirks2;
45
46 static void sdhci_finish_data(struct sdhci_host *);
47
48 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
49
50 static void sdhci_dumpregs(struct sdhci_host *host)
51 {
52 pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
53 mmc_hostname(host->mmc));
54
55 pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
56 sdhci_readl(host, SDHCI_DMA_ADDRESS),
57 sdhci_readw(host, SDHCI_HOST_VERSION));
58 pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
59 sdhci_readw(host, SDHCI_BLOCK_SIZE),
60 sdhci_readw(host, SDHCI_BLOCK_COUNT));
61 pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
62 sdhci_readl(host, SDHCI_ARGUMENT),
63 sdhci_readw(host, SDHCI_TRANSFER_MODE));
64 pr_err(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
65 sdhci_readl(host, SDHCI_PRESENT_STATE),
66 sdhci_readb(host, SDHCI_HOST_CONTROL));
67 pr_err(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
68 sdhci_readb(host, SDHCI_POWER_CONTROL),
69 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
70 pr_err(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
71 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
72 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
73 pr_err(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
74 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
75 sdhci_readl(host, SDHCI_INT_STATUS));
76 pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
77 sdhci_readl(host, SDHCI_INT_ENABLE),
78 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
79 pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
80 sdhci_readw(host, SDHCI_ACMD12_ERR),
81 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
82 pr_err(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
83 sdhci_readl(host, SDHCI_CAPABILITIES),
84 sdhci_readl(host, SDHCI_CAPABILITIES_1));
85 pr_err(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
86 sdhci_readw(host, SDHCI_COMMAND),
87 sdhci_readl(host, SDHCI_MAX_CURRENT));
88 pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n",
89 sdhci_readw(host, SDHCI_HOST_CONTROL2));
90
91 if (host->flags & SDHCI_USE_ADMA) {
92 if (host->flags & SDHCI_USE_64_BIT_DMA)
93 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
94 readl(host->ioaddr + SDHCI_ADMA_ERROR),
95 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
97 else
98 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
99 readl(host->ioaddr + SDHCI_ADMA_ERROR),
100 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
101 }
102
103 pr_err(DRIVER_NAME ": ===========================================\n");
104 }
105
106 /*****************************************************************************\
107 * *
108 * Low level functions *
109 * *
110 \*****************************************************************************/
111
112 static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
113 {
114 return cmd->data || cmd->flags & MMC_RSP_BUSY;
115 }
116
117 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
118 {
119 u32 present;
120
121 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
122 !mmc_card_is_removable(host->mmc))
123 return;
124
125 if (enable) {
126 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
127 SDHCI_CARD_PRESENT;
128
129 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
130 SDHCI_INT_CARD_INSERT;
131 } else {
132 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
133 }
134
135 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
136 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
137 }
138
139 static void sdhci_enable_card_detection(struct sdhci_host *host)
140 {
141 sdhci_set_card_detection(host, true);
142 }
143
144 static void sdhci_disable_card_detection(struct sdhci_host *host)
145 {
146 sdhci_set_card_detection(host, false);
147 }
148
149 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
150 {
151 if (host->bus_on)
152 return;
153 host->bus_on = true;
154 pm_runtime_get_noresume(host->mmc->parent);
155 }
156
157 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
158 {
159 if (!host->bus_on)
160 return;
161 host->bus_on = false;
162 pm_runtime_put_noidle(host->mmc->parent);
163 }
164
165 void sdhci_reset(struct sdhci_host *host, u8 mask)
166 {
167 unsigned long timeout;
168
169 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
170
171 if (mask & SDHCI_RESET_ALL) {
172 host->clock = 0;
173 /* Reset-all turns off SD Bus Power */
174 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
175 sdhci_runtime_pm_bus_off(host);
176 }
177
178 /* Wait max 100 ms */
179 timeout = 100;
180
181 /* hw clears the bit when it's done */
182 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
183 if (timeout == 0) {
184 pr_err("%s: Reset 0x%x never completed.\n",
185 mmc_hostname(host->mmc), (int)mask);
186 sdhci_dumpregs(host);
187 return;
188 }
189 timeout--;
190 mdelay(1);
191 }
192 }
193 EXPORT_SYMBOL_GPL(sdhci_reset);
194
195 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
196 {
197 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
198 struct mmc_host *mmc = host->mmc;
199
200 if (!mmc->ops->get_cd(mmc))
201 return;
202 }
203
204 host->ops->reset(host, mask);
205
206 if (mask & SDHCI_RESET_ALL) {
207 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
208 if (host->ops->enable_dma)
209 host->ops->enable_dma(host);
210 }
211
212 /* Resetting the controller clears many */
213 host->preset_enabled = false;
214 }
215 }
216
217 static void sdhci_init(struct sdhci_host *host, int soft)
218 {
219 struct mmc_host *mmc = host->mmc;
220
221 if (soft)
222 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
223 else
224 sdhci_do_reset(host, SDHCI_RESET_ALL);
225
226 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
227 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
228 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
229 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
230 SDHCI_INT_RESPONSE;
231
232 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
233 host->tuning_mode == SDHCI_TUNING_MODE_3)
234 host->ier |= SDHCI_INT_RETUNE;
235
236 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
237 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
238
239 if (soft) {
240 /* force clock reconfiguration */
241 host->clock = 0;
242 mmc->ops->set_ios(mmc, &mmc->ios);
243 }
244 }
245
246 static void sdhci_reinit(struct sdhci_host *host)
247 {
248 sdhci_init(host, 0);
249 sdhci_enable_card_detection(host);
250 }
251
252 static void __sdhci_led_activate(struct sdhci_host *host)
253 {
254 u8 ctrl;
255
256 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
257 ctrl |= SDHCI_CTRL_LED;
258 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
259 }
260
261 static void __sdhci_led_deactivate(struct sdhci_host *host)
262 {
263 u8 ctrl;
264
265 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
266 ctrl &= ~SDHCI_CTRL_LED;
267 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
268 }
269
270 #if IS_REACHABLE(CONFIG_LEDS_CLASS)
271 static void sdhci_led_control(struct led_classdev *led,
272 enum led_brightness brightness)
273 {
274 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
275 unsigned long flags;
276
277 spin_lock_irqsave(&host->lock, flags);
278
279 if (host->runtime_suspended)
280 goto out;
281
282 if (brightness == LED_OFF)
283 __sdhci_led_deactivate(host);
284 else
285 __sdhci_led_activate(host);
286 out:
287 spin_unlock_irqrestore(&host->lock, flags);
288 }
289
290 static int sdhci_led_register(struct sdhci_host *host)
291 {
292 struct mmc_host *mmc = host->mmc;
293
294 snprintf(host->led_name, sizeof(host->led_name),
295 "%s::", mmc_hostname(mmc));
296
297 host->led.name = host->led_name;
298 host->led.brightness = LED_OFF;
299 host->led.default_trigger = mmc_hostname(mmc);
300 host->led.brightness_set = sdhci_led_control;
301
302 return led_classdev_register(mmc_dev(mmc), &host->led);
303 }
304
305 static void sdhci_led_unregister(struct sdhci_host *host)
306 {
307 led_classdev_unregister(&host->led);
308 }
309
310 static inline void sdhci_led_activate(struct sdhci_host *host)
311 {
312 }
313
314 static inline void sdhci_led_deactivate(struct sdhci_host *host)
315 {
316 }
317
318 #else
319
320 static inline int sdhci_led_register(struct sdhci_host *host)
321 {
322 return 0;
323 }
324
325 static inline void sdhci_led_unregister(struct sdhci_host *host)
326 {
327 }
328
329 static inline void sdhci_led_activate(struct sdhci_host *host)
330 {
331 __sdhci_led_activate(host);
332 }
333
334 static inline void sdhci_led_deactivate(struct sdhci_host *host)
335 {
336 __sdhci_led_deactivate(host);
337 }
338
339 #endif
340
341 /*****************************************************************************\
342 * *
343 * Core functions *
344 * *
345 \*****************************************************************************/
346
347 static void sdhci_read_block_pio(struct sdhci_host *host)
348 {
349 unsigned long flags;
350 size_t blksize, len, chunk;
351 u32 uninitialized_var(scratch);
352 u8 *buf;
353
354 DBG("PIO reading\n");
355
356 blksize = host->data->blksz;
357 chunk = 0;
358
359 local_irq_save(flags);
360
361 while (blksize) {
362 BUG_ON(!sg_miter_next(&host->sg_miter));
363
364 len = min(host->sg_miter.length, blksize);
365
366 blksize -= len;
367 host->sg_miter.consumed = len;
368
369 buf = host->sg_miter.addr;
370
371 while (len) {
372 if (chunk == 0) {
373 scratch = sdhci_readl(host, SDHCI_BUFFER);
374 chunk = 4;
375 }
376
377 *buf = scratch & 0xFF;
378
379 buf++;
380 scratch >>= 8;
381 chunk--;
382 len--;
383 }
384 }
385
386 sg_miter_stop(&host->sg_miter);
387
388 local_irq_restore(flags);
389 }
390
391 static void sdhci_write_block_pio(struct sdhci_host *host)
392 {
393 unsigned long flags;
394 size_t blksize, len, chunk;
395 u32 scratch;
396 u8 *buf;
397
398 DBG("PIO writing\n");
399
400 blksize = host->data->blksz;
401 chunk = 0;
402 scratch = 0;
403
404 local_irq_save(flags);
405
406 while (blksize) {
407 BUG_ON(!sg_miter_next(&host->sg_miter));
408
409 len = min(host->sg_miter.length, blksize);
410
411 blksize -= len;
412 host->sg_miter.consumed = len;
413
414 buf = host->sg_miter.addr;
415
416 while (len) {
417 scratch |= (u32)*buf << (chunk * 8);
418
419 buf++;
420 chunk++;
421 len--;
422
423 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
424 sdhci_writel(host, scratch, SDHCI_BUFFER);
425 chunk = 0;
426 scratch = 0;
427 }
428 }
429 }
430
431 sg_miter_stop(&host->sg_miter);
432
433 local_irq_restore(flags);
434 }
435
436 static void sdhci_transfer_pio(struct sdhci_host *host)
437 {
438 u32 mask;
439
440 if (host->blocks == 0)
441 return;
442
443 if (host->data->flags & MMC_DATA_READ)
444 mask = SDHCI_DATA_AVAILABLE;
445 else
446 mask = SDHCI_SPACE_AVAILABLE;
447
448 /*
449 * Some controllers (JMicron JMB38x) mess up the buffer bits
450 * for transfers < 4 bytes. As long as it is just one block,
451 * we can ignore the bits.
452 */
453 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
454 (host->data->blocks == 1))
455 mask = ~0;
456
457 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
458 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
459 udelay(100);
460
461 if (host->data->flags & MMC_DATA_READ)
462 sdhci_read_block_pio(host);
463 else
464 sdhci_write_block_pio(host);
465
466 host->blocks--;
467 if (host->blocks == 0)
468 break;
469 }
470
471 DBG("PIO transfer complete.\n");
472 }
473
474 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
475 struct mmc_data *data, int cookie)
476 {
477 int sg_count;
478
479 /*
480 * If the data buffers are already mapped, return the previous
481 * dma_map_sg() result.
482 */
483 if (data->host_cookie == COOKIE_PRE_MAPPED)
484 return data->sg_count;
485
486 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
487 data->flags & MMC_DATA_WRITE ?
488 DMA_TO_DEVICE : DMA_FROM_DEVICE);
489
490 if (sg_count == 0)
491 return -ENOSPC;
492
493 data->sg_count = sg_count;
494 data->host_cookie = cookie;
495
496 return sg_count;
497 }
498
499 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
500 {
501 local_irq_save(*flags);
502 return kmap_atomic(sg_page(sg)) + sg->offset;
503 }
504
505 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
506 {
507 kunmap_atomic(buffer);
508 local_irq_restore(*flags);
509 }
510
511 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
512 dma_addr_t addr, int len, unsigned cmd)
513 {
514 struct sdhci_adma2_64_desc *dma_desc = desc;
515
516 /* 32-bit and 64-bit descriptors have these members in same position */
517 dma_desc->cmd = cpu_to_le16(cmd);
518 dma_desc->len = cpu_to_le16(len);
519 dma_desc->addr_lo = cpu_to_le32((u32)addr);
520
521 if (host->flags & SDHCI_USE_64_BIT_DMA)
522 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
523 }
524
525 static void sdhci_adma_mark_end(void *desc)
526 {
527 struct sdhci_adma2_64_desc *dma_desc = desc;
528
529 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
530 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
531 }
532
533 static void sdhci_adma_table_pre(struct sdhci_host *host,
534 struct mmc_data *data, int sg_count)
535 {
536 struct scatterlist *sg;
537 unsigned long flags;
538 dma_addr_t addr, align_addr;
539 void *desc, *align;
540 char *buffer;
541 int len, offset, i;
542
543 /*
544 * The spec does not specify endianness of descriptor table.
545 * We currently guess that it is LE.
546 */
547
548 host->sg_count = sg_count;
549
550 desc = host->adma_table;
551 align = host->align_buffer;
552
553 align_addr = host->align_addr;
554
555 for_each_sg(data->sg, sg, host->sg_count, i) {
556 addr = sg_dma_address(sg);
557 len = sg_dma_len(sg);
558
559 /*
560 * The SDHCI specification states that ADMA addresses must
561 * be 32-bit aligned. If they aren't, then we use a bounce
562 * buffer for the (up to three) bytes that screw up the
563 * alignment.
564 */
565 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
566 SDHCI_ADMA2_MASK;
567 if (offset) {
568 if (data->flags & MMC_DATA_WRITE) {
569 buffer = sdhci_kmap_atomic(sg, &flags);
570 memcpy(align, buffer, offset);
571 sdhci_kunmap_atomic(buffer, &flags);
572 }
573
574 /* tran, valid */
575 sdhci_adma_write_desc(host, desc, align_addr, offset,
576 ADMA2_TRAN_VALID);
577
578 BUG_ON(offset > 65536);
579
580 align += SDHCI_ADMA2_ALIGN;
581 align_addr += SDHCI_ADMA2_ALIGN;
582
583 desc += host->desc_sz;
584
585 addr += offset;
586 len -= offset;
587 }
588
589 BUG_ON(len > 65536);
590
591 if (len) {
592 /* tran, valid */
593 sdhci_adma_write_desc(host, desc, addr, len,
594 ADMA2_TRAN_VALID);
595 desc += host->desc_sz;
596 }
597
598 /*
599 * If this triggers then we have a calculation bug
600 * somewhere. :/
601 */
602 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
603 }
604
605 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
606 /* Mark the last descriptor as the terminating descriptor */
607 if (desc != host->adma_table) {
608 desc -= host->desc_sz;
609 sdhci_adma_mark_end(desc);
610 }
611 } else {
612 /* Add a terminating entry - nop, end, valid */
613 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
614 }
615 }
616
617 static void sdhci_adma_table_post(struct sdhci_host *host,
618 struct mmc_data *data)
619 {
620 struct scatterlist *sg;
621 int i, size;
622 void *align;
623 char *buffer;
624 unsigned long flags;
625
626 if (data->flags & MMC_DATA_READ) {
627 bool has_unaligned = false;
628
629 /* Do a quick scan of the SG list for any unaligned mappings */
630 for_each_sg(data->sg, sg, host->sg_count, i)
631 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
632 has_unaligned = true;
633 break;
634 }
635
636 if (has_unaligned) {
637 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
638 data->sg_len, DMA_FROM_DEVICE);
639
640 align = host->align_buffer;
641
642 for_each_sg(data->sg, sg, host->sg_count, i) {
643 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
644 size = SDHCI_ADMA2_ALIGN -
645 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
646
647 buffer = sdhci_kmap_atomic(sg, &flags);
648 memcpy(buffer, align, size);
649 sdhci_kunmap_atomic(buffer, &flags);
650
651 align += SDHCI_ADMA2_ALIGN;
652 }
653 }
654 }
655 }
656 }
657
658 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
659 {
660 u8 count;
661 struct mmc_data *data = cmd->data;
662 unsigned target_timeout, current_timeout;
663
664 /*
665 * If the host controller provides us with an incorrect timeout
666 * value, just skip the check and use 0xE. The hardware may take
667 * longer to time out, but that's much better than having a too-short
668 * timeout value.
669 */
670 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
671 return 0xE;
672
673 /* Unspecified timeout, assume max */
674 if (!data && !cmd->busy_timeout)
675 return 0xE;
676
677 /* timeout in us */
678 if (!data)
679 target_timeout = cmd->busy_timeout * 1000;
680 else {
681 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
682 if (host->clock && data->timeout_clks) {
683 unsigned long long val;
684
685 /*
686 * data->timeout_clks is in units of clock cycles.
687 * host->clock is in Hz. target_timeout is in us.
688 * Hence, us = 1000000 * cycles / Hz. Round up.
689 */
690 val = 1000000 * data->timeout_clks;
691 if (do_div(val, host->clock))
692 target_timeout++;
693 target_timeout += val;
694 }
695 }
696
697 /*
698 * Figure out needed cycles.
699 * We do this in steps in order to fit inside a 32 bit int.
700 * The first step is the minimum timeout, which will have a
701 * minimum resolution of 6 bits:
702 * (1) 2^13*1000 > 2^22,
703 * (2) host->timeout_clk < 2^16
704 * =>
705 * (1) / (2) > 2^6
706 */
707 count = 0;
708 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
709 while (current_timeout < target_timeout) {
710 count++;
711 current_timeout <<= 1;
712 if (count >= 0xF)
713 break;
714 }
715
716 if (count >= 0xF) {
717 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
718 mmc_hostname(host->mmc), count, cmd->opcode);
719 count = 0xE;
720 }
721
722 return count;
723 }
724
725 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
726 {
727 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
728 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
729
730 if (host->flags & SDHCI_REQ_USE_DMA)
731 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
732 else
733 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
734
735 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
736 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
737 }
738
739 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
740 {
741 u8 count;
742
743 if (host->ops->set_timeout) {
744 host->ops->set_timeout(host, cmd);
745 } else {
746 count = sdhci_calc_timeout(host, cmd);
747 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
748 }
749 }
750
751 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
752 {
753 u8 ctrl;
754 struct mmc_data *data = cmd->data;
755
756 if (sdhci_data_line_cmd(cmd))
757 sdhci_set_timeout(host, cmd);
758
759 if (!data)
760 return;
761
762 WARN_ON(host->data);
763
764 /* Sanity checks */
765 BUG_ON(data->blksz * data->blocks > 524288);
766 BUG_ON(data->blksz > host->mmc->max_blk_size);
767 BUG_ON(data->blocks > 65535);
768
769 host->data = data;
770 host->data_early = 0;
771 host->data->bytes_xfered = 0;
772
773 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
774 struct scatterlist *sg;
775 unsigned int length_mask, offset_mask;
776 int i;
777
778 host->flags |= SDHCI_REQ_USE_DMA;
779
780 /*
781 * FIXME: This doesn't account for merging when mapping the
782 * scatterlist.
783 *
784 * The assumption here being that alignment and lengths are
785 * the same after DMA mapping to device address space.
786 */
787 length_mask = 0;
788 offset_mask = 0;
789 if (host->flags & SDHCI_USE_ADMA) {
790 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
791 length_mask = 3;
792 /*
793 * As we use up to 3 byte chunks to work
794 * around alignment problems, we need to
795 * check the offset as well.
796 */
797 offset_mask = 3;
798 }
799 } else {
800 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
801 length_mask = 3;
802 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
803 offset_mask = 3;
804 }
805
806 if (unlikely(length_mask | offset_mask)) {
807 for_each_sg(data->sg, sg, data->sg_len, i) {
808 if (sg->length & length_mask) {
809 DBG("Reverting to PIO because of transfer size (%d)\n",
810 sg->length);
811 host->flags &= ~SDHCI_REQ_USE_DMA;
812 break;
813 }
814 if (sg->offset & offset_mask) {
815 DBG("Reverting to PIO because of bad alignment\n");
816 host->flags &= ~SDHCI_REQ_USE_DMA;
817 break;
818 }
819 }
820 }
821 }
822
823 if (host->flags & SDHCI_REQ_USE_DMA) {
824 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
825
826 if (sg_cnt <= 0) {
827 /*
828 * This only happens when someone fed
829 * us an invalid request.
830 */
831 WARN_ON(1);
832 host->flags &= ~SDHCI_REQ_USE_DMA;
833 } else if (host->flags & SDHCI_USE_ADMA) {
834 sdhci_adma_table_pre(host, data, sg_cnt);
835
836 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
837 if (host->flags & SDHCI_USE_64_BIT_DMA)
838 sdhci_writel(host,
839 (u64)host->adma_addr >> 32,
840 SDHCI_ADMA_ADDRESS_HI);
841 } else {
842 WARN_ON(sg_cnt != 1);
843 sdhci_writel(host, sg_dma_address(data->sg),
844 SDHCI_DMA_ADDRESS);
845 }
846 }
847
848 /*
849 * Always adjust the DMA selection as some controllers
850 * (e.g. JMicron) can't do PIO properly when the selection
851 * is ADMA.
852 */
853 if (host->version >= SDHCI_SPEC_200) {
854 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
855 ctrl &= ~SDHCI_CTRL_DMA_MASK;
856 if ((host->flags & SDHCI_REQ_USE_DMA) &&
857 (host->flags & SDHCI_USE_ADMA)) {
858 if (host->flags & SDHCI_USE_64_BIT_DMA)
859 ctrl |= SDHCI_CTRL_ADMA64;
860 else
861 ctrl |= SDHCI_CTRL_ADMA32;
862 } else {
863 ctrl |= SDHCI_CTRL_SDMA;
864 }
865 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
866 }
867
868 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
869 int flags;
870
871 flags = SG_MITER_ATOMIC;
872 if (host->data->flags & MMC_DATA_READ)
873 flags |= SG_MITER_TO_SG;
874 else
875 flags |= SG_MITER_FROM_SG;
876 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
877 host->blocks = data->blocks;
878 }
879
880 sdhci_set_transfer_irqs(host);
881
882 /* Set the DMA boundary value and block size */
883 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
884 data->blksz), SDHCI_BLOCK_SIZE);
885 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
886 }
887
888 static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
889 struct mmc_request *mrq)
890 {
891 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12);
892 }
893
894 static void sdhci_set_transfer_mode(struct sdhci_host *host,
895 struct mmc_command *cmd)
896 {
897 u16 mode = 0;
898 struct mmc_data *data = cmd->data;
899
900 if (data == NULL) {
901 if (host->quirks2 &
902 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
903 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
904 } else {
905 /* clear Auto CMD settings for no data CMDs */
906 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
907 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
908 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
909 }
910 return;
911 }
912
913 WARN_ON(!host->data);
914
915 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
916 mode = SDHCI_TRNS_BLK_CNT_EN;
917
918 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
919 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
920 /*
921 * If we are sending CMD23, CMD12 never gets sent
922 * on successful completion (so no Auto-CMD12).
923 */
924 if (sdhci_auto_cmd12(host, cmd->mrq) &&
925 (cmd->opcode != SD_IO_RW_EXTENDED))
926 mode |= SDHCI_TRNS_AUTO_CMD12;
927 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
928 mode |= SDHCI_TRNS_AUTO_CMD23;
929 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
930 }
931 }
932
933 if (data->flags & MMC_DATA_READ)
934 mode |= SDHCI_TRNS_READ;
935 if (host->flags & SDHCI_REQ_USE_DMA)
936 mode |= SDHCI_TRNS_DMA;
937
938 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
939 }
940
941 static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
942 {
943 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
944 ((mrq->cmd && mrq->cmd->error) ||
945 (mrq->sbc && mrq->sbc->error) ||
946 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
947 (mrq->data->stop && mrq->data->stop->error))) ||
948 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
949 }
950
951 static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
952 {
953 int i;
954
955 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
956 if (host->mrqs_done[i] == mrq) {
957 WARN_ON(1);
958 return;
959 }
960 }
961
962 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
963 if (!host->mrqs_done[i]) {
964 host->mrqs_done[i] = mrq;
965 break;
966 }
967 }
968
969 WARN_ON(i >= SDHCI_MAX_MRQS);
970
971 tasklet_schedule(&host->finish_tasklet);
972 }
973
974 static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
975 {
976 if (host->cmd && host->cmd->mrq == mrq)
977 host->cmd = NULL;
978
979 if (host->data_cmd && host->data_cmd->mrq == mrq)
980 host->data_cmd = NULL;
981
982 if (host->data && host->data->mrq == mrq)
983 host->data = NULL;
984
985 if (sdhci_needs_reset(host, mrq))
986 host->pending_reset = true;
987
988 __sdhci_finish_mrq(host, mrq);
989 }
990
991 static void sdhci_finish_data(struct sdhci_host *host)
992 {
993 struct mmc_command *data_cmd = host->data_cmd;
994 struct mmc_data *data = host->data;
995
996 host->data = NULL;
997 host->data_cmd = NULL;
998
999 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1000 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1001 sdhci_adma_table_post(host, data);
1002
1003 /*
1004 * The specification states that the block count register must
1005 * be updated, but it does not specify at what point in the
1006 * data flow. That makes the register entirely useless to read
1007 * back so we have to assume that nothing made it to the card
1008 * in the event of an error.
1009 */
1010 if (data->error)
1011 data->bytes_xfered = 0;
1012 else
1013 data->bytes_xfered = data->blksz * data->blocks;
1014
1015 /*
1016 * Need to send CMD12 if -
1017 * a) open-ended multiblock transfer (no CMD23)
1018 * b) error in multiblock transfer
1019 */
1020 if (data->stop &&
1021 (data->error ||
1022 !data->mrq->sbc)) {
1023
1024 /*
1025 * The controller needs a reset of internal state machines
1026 * upon error conditions.
1027 */
1028 if (data->error) {
1029 if (!host->cmd || host->cmd == data_cmd)
1030 sdhci_do_reset(host, SDHCI_RESET_CMD);
1031 sdhci_do_reset(host, SDHCI_RESET_DATA);
1032 }
1033
1034 /* Avoid triggering warning in sdhci_send_command() */
1035 host->cmd = NULL;
1036 sdhci_send_command(host, data->stop);
1037 } else {
1038 sdhci_finish_mrq(host, data->mrq);
1039 }
1040 }
1041
1042 static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
1043 unsigned long timeout)
1044 {
1045 if (sdhci_data_line_cmd(mrq->cmd))
1046 mod_timer(&host->data_timer, timeout);
1047 else
1048 mod_timer(&host->timer, timeout);
1049 }
1050
1051 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
1052 {
1053 if (sdhci_data_line_cmd(mrq->cmd))
1054 del_timer(&host->data_timer);
1055 else
1056 del_timer(&host->timer);
1057 }
1058
1059 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1060 {
1061 int flags;
1062 u32 mask;
1063 unsigned long timeout;
1064
1065 WARN_ON(host->cmd);
1066
1067 /* Initially, a command has no error */
1068 cmd->error = 0;
1069
1070 /* Wait max 10 ms */
1071 timeout = 10;
1072
1073 mask = SDHCI_CMD_INHIBIT;
1074 if (sdhci_data_line_cmd(cmd))
1075 mask |= SDHCI_DATA_INHIBIT;
1076
1077 /* We shouldn't wait for data inihibit for stop commands, even
1078 though they might use busy signaling */
1079 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1080 mask &= ~SDHCI_DATA_INHIBIT;
1081
1082 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1083 if (timeout == 0) {
1084 pr_err("%s: Controller never released inhibit bit(s).\n",
1085 mmc_hostname(host->mmc));
1086 sdhci_dumpregs(host);
1087 cmd->error = -EIO;
1088 sdhci_finish_mrq(host, cmd->mrq);
1089 return;
1090 }
1091 timeout--;
1092 mdelay(1);
1093 }
1094
1095 timeout = jiffies;
1096 if (!cmd->data && cmd->busy_timeout > 9000)
1097 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1098 else
1099 timeout += 10 * HZ;
1100 sdhci_mod_timer(host, cmd->mrq, timeout);
1101
1102 host->cmd = cmd;
1103 if (sdhci_data_line_cmd(cmd)) {
1104 WARN_ON(host->data_cmd);
1105 host->data_cmd = cmd;
1106 }
1107
1108 sdhci_prepare_data(host, cmd);
1109
1110 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1111
1112 sdhci_set_transfer_mode(host, cmd);
1113
1114 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1115 pr_err("%s: Unsupported response type!\n",
1116 mmc_hostname(host->mmc));
1117 cmd->error = -EINVAL;
1118 sdhci_finish_mrq(host, cmd->mrq);
1119 return;
1120 }
1121
1122 if (!(cmd->flags & MMC_RSP_PRESENT))
1123 flags = SDHCI_CMD_RESP_NONE;
1124 else if (cmd->flags & MMC_RSP_136)
1125 flags = SDHCI_CMD_RESP_LONG;
1126 else if (cmd->flags & MMC_RSP_BUSY)
1127 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1128 else
1129 flags = SDHCI_CMD_RESP_SHORT;
1130
1131 if (cmd->flags & MMC_RSP_CRC)
1132 flags |= SDHCI_CMD_CRC;
1133 if (cmd->flags & MMC_RSP_OPCODE)
1134 flags |= SDHCI_CMD_INDEX;
1135
1136 /* CMD19 is special in that the Data Present Select should be set */
1137 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1138 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1139 flags |= SDHCI_CMD_DATA;
1140
1141 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1142 }
1143 EXPORT_SYMBOL_GPL(sdhci_send_command);
1144
1145 static void sdhci_finish_command(struct sdhci_host *host)
1146 {
1147 struct mmc_command *cmd = host->cmd;
1148 int i;
1149
1150 host->cmd = NULL;
1151
1152 if (cmd->flags & MMC_RSP_PRESENT) {
1153 if (cmd->flags & MMC_RSP_136) {
1154 /* CRC is stripped so we need to do some shifting. */
1155 for (i = 0;i < 4;i++) {
1156 cmd->resp[i] = sdhci_readl(host,
1157 SDHCI_RESPONSE + (3-i)*4) << 8;
1158 if (i != 3)
1159 cmd->resp[i] |=
1160 sdhci_readb(host,
1161 SDHCI_RESPONSE + (3-i)*4-1);
1162 }
1163 } else {
1164 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1165 }
1166 }
1167
1168 /*
1169 * The host can send and interrupt when the busy state has
1170 * ended, allowing us to wait without wasting CPU cycles.
1171 * The busy signal uses DAT0 so this is similar to waiting
1172 * for data to complete.
1173 *
1174 * Note: The 1.0 specification is a bit ambiguous about this
1175 * feature so there might be some problems with older
1176 * controllers.
1177 */
1178 if (cmd->flags & MMC_RSP_BUSY) {
1179 if (cmd->data) {
1180 DBG("Cannot wait for busy signal when also doing a data transfer");
1181 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1182 cmd == host->data_cmd) {
1183 /* Command complete before busy is ended */
1184 return;
1185 }
1186 }
1187
1188 /* Finished CMD23, now send actual command. */
1189 if (cmd == cmd->mrq->sbc) {
1190 sdhci_send_command(host, cmd->mrq->cmd);
1191 } else {
1192
1193 /* Processed actual command. */
1194 if (host->data && host->data_early)
1195 sdhci_finish_data(host);
1196
1197 if (!cmd->data)
1198 sdhci_finish_mrq(host, cmd->mrq);
1199 }
1200 }
1201
1202 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1203 {
1204 u16 preset = 0;
1205
1206 switch (host->timing) {
1207 case MMC_TIMING_UHS_SDR12:
1208 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1209 break;
1210 case MMC_TIMING_UHS_SDR25:
1211 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1212 break;
1213 case MMC_TIMING_UHS_SDR50:
1214 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1215 break;
1216 case MMC_TIMING_UHS_SDR104:
1217 case MMC_TIMING_MMC_HS200:
1218 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1219 break;
1220 case MMC_TIMING_UHS_DDR50:
1221 case MMC_TIMING_MMC_DDR52:
1222 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1223 break;
1224 case MMC_TIMING_MMC_HS400:
1225 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1226 break;
1227 default:
1228 pr_warn("%s: Invalid UHS-I mode selected\n",
1229 mmc_hostname(host->mmc));
1230 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1231 break;
1232 }
1233 return preset;
1234 }
1235
1236 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1237 unsigned int *actual_clock)
1238 {
1239 int div = 0; /* Initialized for compiler warning */
1240 int real_div = div, clk_mul = 1;
1241 u16 clk = 0;
1242 bool switch_base_clk = false;
1243
1244 if (host->version >= SDHCI_SPEC_300) {
1245 if (host->preset_enabled) {
1246 u16 pre_val;
1247
1248 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1249 pre_val = sdhci_get_preset_value(host);
1250 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1251 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1252 if (host->clk_mul &&
1253 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1254 clk = SDHCI_PROG_CLOCK_MODE;
1255 real_div = div + 1;
1256 clk_mul = host->clk_mul;
1257 } else {
1258 real_div = max_t(int, 1, div << 1);
1259 }
1260 goto clock_set;
1261 }
1262
1263 /*
1264 * Check if the Host Controller supports Programmable Clock
1265 * Mode.
1266 */
1267 if (host->clk_mul) {
1268 for (div = 1; div <= 1024; div++) {
1269 if ((host->max_clk * host->clk_mul / div)
1270 <= clock)
1271 break;
1272 }
1273 if ((host->max_clk * host->clk_mul / div) <= clock) {
1274 /*
1275 * Set Programmable Clock Mode in the Clock
1276 * Control register.
1277 */
1278 clk = SDHCI_PROG_CLOCK_MODE;
1279 real_div = div;
1280 clk_mul = host->clk_mul;
1281 div--;
1282 } else {
1283 /*
1284 * Divisor can be too small to reach clock
1285 * speed requirement. Then use the base clock.
1286 */
1287 switch_base_clk = true;
1288 }
1289 }
1290
1291 if (!host->clk_mul || switch_base_clk) {
1292 /* Version 3.00 divisors must be a multiple of 2. */
1293 if (host->max_clk <= clock)
1294 div = 1;
1295 else {
1296 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1297 div += 2) {
1298 if ((host->max_clk / div) <= clock)
1299 break;
1300 }
1301 }
1302 real_div = div;
1303 div >>= 1;
1304 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1305 && !div && host->max_clk <= 25000000)
1306 div = 1;
1307 }
1308 } else {
1309 /* Version 2.00 divisors must be a power of 2. */
1310 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1311 if ((host->max_clk / div) <= clock)
1312 break;
1313 }
1314 real_div = div;
1315 div >>= 1;
1316 }
1317
1318 clock_set:
1319 if (real_div)
1320 *actual_clock = (host->max_clk * clk_mul) / real_div;
1321 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1322 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1323 << SDHCI_DIVIDER_HI_SHIFT;
1324
1325 return clk;
1326 }
1327 EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1328
1329 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1330 {
1331 u16 clk;
1332 unsigned long timeout;
1333
1334 host->mmc->actual_clock = 0;
1335
1336 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1337
1338 if (clock == 0)
1339 return;
1340
1341 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1342
1343 clk |= SDHCI_CLOCK_INT_EN;
1344 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1345
1346 /* Wait max 20 ms */
1347 timeout = 20;
1348 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1349 & SDHCI_CLOCK_INT_STABLE)) {
1350 if (timeout == 0) {
1351 pr_err("%s: Internal clock never stabilised.\n",
1352 mmc_hostname(host->mmc));
1353 sdhci_dumpregs(host);
1354 return;
1355 }
1356 timeout--;
1357 mdelay(1);
1358 }
1359
1360 clk |= SDHCI_CLOCK_CARD_EN;
1361 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1362 }
1363 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1364
1365 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1366 unsigned short vdd)
1367 {
1368 struct mmc_host *mmc = host->mmc;
1369
1370 spin_unlock_irq(&host->lock);
1371 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1372 spin_lock_irq(&host->lock);
1373
1374 if (mode != MMC_POWER_OFF)
1375 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1376 else
1377 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1378 }
1379
1380 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1381 unsigned short vdd)
1382 {
1383 u8 pwr = 0;
1384
1385 if (mode != MMC_POWER_OFF) {
1386 switch (1 << vdd) {
1387 case MMC_VDD_165_195:
1388 pwr = SDHCI_POWER_180;
1389 break;
1390 case MMC_VDD_29_30:
1391 case MMC_VDD_30_31:
1392 pwr = SDHCI_POWER_300;
1393 break;
1394 case MMC_VDD_32_33:
1395 case MMC_VDD_33_34:
1396 pwr = SDHCI_POWER_330;
1397 break;
1398 default:
1399 WARN(1, "%s: Invalid vdd %#x\n",
1400 mmc_hostname(host->mmc), vdd);
1401 break;
1402 }
1403 }
1404
1405 if (host->pwr == pwr)
1406 return;
1407
1408 host->pwr = pwr;
1409
1410 if (pwr == 0) {
1411 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1412 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1413 sdhci_runtime_pm_bus_off(host);
1414 } else {
1415 /*
1416 * Spec says that we should clear the power reg before setting
1417 * a new value. Some controllers don't seem to like this though.
1418 */
1419 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1420 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1421
1422 /*
1423 * At least the Marvell CaFe chip gets confused if we set the
1424 * voltage and set turn on power at the same time, so set the
1425 * voltage first.
1426 */
1427 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1428 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1429
1430 pwr |= SDHCI_POWER_ON;
1431
1432 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1433
1434 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1435 sdhci_runtime_pm_bus_on(host);
1436
1437 /*
1438 * Some controllers need an extra 10ms delay of 10ms before
1439 * they can apply clock after applying power
1440 */
1441 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1442 mdelay(10);
1443 }
1444 }
1445 EXPORT_SYMBOL_GPL(sdhci_set_power);
1446
1447 static void __sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1448 unsigned short vdd)
1449 {
1450 struct mmc_host *mmc = host->mmc;
1451
1452 if (host->ops->set_power)
1453 host->ops->set_power(host, mode, vdd);
1454 else if (!IS_ERR(mmc->supply.vmmc))
1455 sdhci_set_power_reg(host, mode, vdd);
1456 else
1457 sdhci_set_power(host, mode, vdd);
1458 }
1459
1460 /*****************************************************************************\
1461 * *
1462 * MMC callbacks *
1463 * *
1464 \*****************************************************************************/
1465
1466 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1467 {
1468 struct sdhci_host *host;
1469 int present;
1470 unsigned long flags;
1471
1472 host = mmc_priv(mmc);
1473
1474 /* Firstly check card presence */
1475 present = mmc->ops->get_cd(mmc);
1476
1477 spin_lock_irqsave(&host->lock, flags);
1478
1479 sdhci_led_activate(host);
1480
1481 /*
1482 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1483 * requests if Auto-CMD12 is enabled.
1484 */
1485 if (sdhci_auto_cmd12(host, mrq)) {
1486 if (mrq->stop) {
1487 mrq->data->stop = NULL;
1488 mrq->stop = NULL;
1489 }
1490 }
1491
1492 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1493 mrq->cmd->error = -ENOMEDIUM;
1494 sdhci_finish_mrq(host, mrq);
1495 } else {
1496 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1497 sdhci_send_command(host, mrq->sbc);
1498 else
1499 sdhci_send_command(host, mrq->cmd);
1500 }
1501
1502 mmiowb();
1503 spin_unlock_irqrestore(&host->lock, flags);
1504 }
1505
1506 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1507 {
1508 u8 ctrl;
1509
1510 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1511 if (width == MMC_BUS_WIDTH_8) {
1512 ctrl &= ~SDHCI_CTRL_4BITBUS;
1513 if (host->version >= SDHCI_SPEC_300)
1514 ctrl |= SDHCI_CTRL_8BITBUS;
1515 } else {
1516 if (host->version >= SDHCI_SPEC_300)
1517 ctrl &= ~SDHCI_CTRL_8BITBUS;
1518 if (width == MMC_BUS_WIDTH_4)
1519 ctrl |= SDHCI_CTRL_4BITBUS;
1520 else
1521 ctrl &= ~SDHCI_CTRL_4BITBUS;
1522 }
1523 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1524 }
1525 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1526
1527 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1528 {
1529 u16 ctrl_2;
1530
1531 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1532 /* Select Bus Speed Mode for host */
1533 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1534 if ((timing == MMC_TIMING_MMC_HS200) ||
1535 (timing == MMC_TIMING_UHS_SDR104))
1536 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1537 else if (timing == MMC_TIMING_UHS_SDR12)
1538 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1539 else if (timing == MMC_TIMING_UHS_SDR25)
1540 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1541 else if (timing == MMC_TIMING_UHS_SDR50)
1542 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1543 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1544 (timing == MMC_TIMING_MMC_DDR52))
1545 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1546 else if (timing == MMC_TIMING_MMC_HS400)
1547 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1548 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1549 }
1550 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1551
1552 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1553 {
1554 struct sdhci_host *host = mmc_priv(mmc);
1555 unsigned long flags;
1556 u8 ctrl;
1557
1558 spin_lock_irqsave(&host->lock, flags);
1559
1560 if (host->flags & SDHCI_DEVICE_DEAD) {
1561 spin_unlock_irqrestore(&host->lock, flags);
1562 if (!IS_ERR(mmc->supply.vmmc) &&
1563 ios->power_mode == MMC_POWER_OFF)
1564 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1565 return;
1566 }
1567
1568 /*
1569 * Reset the chip on each power off.
1570 * Should clear out any weird states.
1571 */
1572 if (ios->power_mode == MMC_POWER_OFF) {
1573 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1574 sdhci_reinit(host);
1575 }
1576
1577 if (host->version >= SDHCI_SPEC_300 &&
1578 (ios->power_mode == MMC_POWER_UP) &&
1579 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1580 sdhci_enable_preset_value(host, false);
1581
1582 if (!ios->clock || ios->clock != host->clock) {
1583 host->ops->set_clock(host, ios->clock);
1584 host->clock = ios->clock;
1585
1586 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1587 host->clock) {
1588 host->timeout_clk = host->mmc->actual_clock ?
1589 host->mmc->actual_clock / 1000 :
1590 host->clock / 1000;
1591 host->mmc->max_busy_timeout =
1592 host->ops->get_max_timeout_count ?
1593 host->ops->get_max_timeout_count(host) :
1594 1 << 27;
1595 host->mmc->max_busy_timeout /= host->timeout_clk;
1596 }
1597 }
1598
1599 __sdhci_set_power(host, ios->power_mode, ios->vdd);
1600
1601 if (host->ops->platform_send_init_74_clocks)
1602 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1603
1604 host->ops->set_bus_width(host, ios->bus_width);
1605
1606 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1607
1608 if ((ios->timing == MMC_TIMING_SD_HS ||
1609 ios->timing == MMC_TIMING_MMC_HS)
1610 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1611 ctrl |= SDHCI_CTRL_HISPD;
1612 else
1613 ctrl &= ~SDHCI_CTRL_HISPD;
1614
1615 if (host->version >= SDHCI_SPEC_300) {
1616 u16 clk, ctrl_2;
1617
1618 /* In case of UHS-I modes, set High Speed Enable */
1619 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1620 (ios->timing == MMC_TIMING_MMC_HS200) ||
1621 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1622 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1623 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1624 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1625 (ios->timing == MMC_TIMING_UHS_SDR25))
1626 ctrl |= SDHCI_CTRL_HISPD;
1627
1628 if (!host->preset_enabled) {
1629 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1630 /*
1631 * We only need to set Driver Strength if the
1632 * preset value enable is not set.
1633 */
1634 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1635 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1636 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1637 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1638 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1639 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1640 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1641 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1642 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1643 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1644 else {
1645 pr_warn("%s: invalid driver type, default to driver type B\n",
1646 mmc_hostname(mmc));
1647 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1648 }
1649
1650 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1651 } else {
1652 /*
1653 * According to SDHC Spec v3.00, if the Preset Value
1654 * Enable in the Host Control 2 register is set, we
1655 * need to reset SD Clock Enable before changing High
1656 * Speed Enable to avoid generating clock gliches.
1657 */
1658
1659 /* Reset SD Clock Enable */
1660 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1661 clk &= ~SDHCI_CLOCK_CARD_EN;
1662 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1663
1664 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1665
1666 /* Re-enable SD Clock */
1667 host->ops->set_clock(host, host->clock);
1668 }
1669
1670 /* Reset SD Clock Enable */
1671 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1672 clk &= ~SDHCI_CLOCK_CARD_EN;
1673 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1674
1675 host->ops->set_uhs_signaling(host, ios->timing);
1676 host->timing = ios->timing;
1677
1678 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1679 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1680 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1681 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1682 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1683 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1684 (ios->timing == MMC_TIMING_MMC_DDR52))) {
1685 u16 preset;
1686
1687 sdhci_enable_preset_value(host, true);
1688 preset = sdhci_get_preset_value(host);
1689 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1690 >> SDHCI_PRESET_DRV_SHIFT;
1691 }
1692
1693 /* Re-enable SD Clock */
1694 host->ops->set_clock(host, host->clock);
1695 } else
1696 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1697
1698 /*
1699 * Some (ENE) controllers go apeshit on some ios operation,
1700 * signalling timeout and CRC errors even on CMD0. Resetting
1701 * it on each ios seems to solve the problem.
1702 */
1703 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1704 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1705
1706 mmiowb();
1707 spin_unlock_irqrestore(&host->lock, flags);
1708 }
1709
1710 static int sdhci_get_cd(struct mmc_host *mmc)
1711 {
1712 struct sdhci_host *host = mmc_priv(mmc);
1713 int gpio_cd = mmc_gpio_get_cd(mmc);
1714
1715 if (host->flags & SDHCI_DEVICE_DEAD)
1716 return 0;
1717
1718 /* If nonremovable, assume that the card is always present. */
1719 if (!mmc_card_is_removable(host->mmc))
1720 return 1;
1721
1722 /*
1723 * Try slot gpio detect, if defined it take precedence
1724 * over build in controller functionality
1725 */
1726 if (gpio_cd >= 0)
1727 return !!gpio_cd;
1728
1729 /* If polling, assume that the card is always present. */
1730 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1731 return 1;
1732
1733 /* Host native card detect */
1734 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1735 }
1736
1737 static int sdhci_check_ro(struct sdhci_host *host)
1738 {
1739 unsigned long flags;
1740 int is_readonly;
1741
1742 spin_lock_irqsave(&host->lock, flags);
1743
1744 if (host->flags & SDHCI_DEVICE_DEAD)
1745 is_readonly = 0;
1746 else if (host->ops->get_ro)
1747 is_readonly = host->ops->get_ro(host);
1748 else
1749 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1750 & SDHCI_WRITE_PROTECT);
1751
1752 spin_unlock_irqrestore(&host->lock, flags);
1753
1754 /* This quirk needs to be replaced by a callback-function later */
1755 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1756 !is_readonly : is_readonly;
1757 }
1758
1759 #define SAMPLE_COUNT 5
1760
1761 static int sdhci_get_ro(struct mmc_host *mmc)
1762 {
1763 struct sdhci_host *host = mmc_priv(mmc);
1764 int i, ro_count;
1765
1766 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1767 return sdhci_check_ro(host);
1768
1769 ro_count = 0;
1770 for (i = 0; i < SAMPLE_COUNT; i++) {
1771 if (sdhci_check_ro(host)) {
1772 if (++ro_count > SAMPLE_COUNT / 2)
1773 return 1;
1774 }
1775 msleep(30);
1776 }
1777 return 0;
1778 }
1779
1780 static void sdhci_hw_reset(struct mmc_host *mmc)
1781 {
1782 struct sdhci_host *host = mmc_priv(mmc);
1783
1784 if (host->ops && host->ops->hw_reset)
1785 host->ops->hw_reset(host);
1786 }
1787
1788 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1789 {
1790 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1791 if (enable)
1792 host->ier |= SDHCI_INT_CARD_INT;
1793 else
1794 host->ier &= ~SDHCI_INT_CARD_INT;
1795
1796 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1797 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1798 mmiowb();
1799 }
1800 }
1801
1802 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1803 {
1804 struct sdhci_host *host = mmc_priv(mmc);
1805 unsigned long flags;
1806
1807 spin_lock_irqsave(&host->lock, flags);
1808 if (enable)
1809 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1810 else
1811 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1812
1813 sdhci_enable_sdio_irq_nolock(host, enable);
1814 spin_unlock_irqrestore(&host->lock, flags);
1815 }
1816
1817 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1818 struct mmc_ios *ios)
1819 {
1820 struct sdhci_host *host = mmc_priv(mmc);
1821 u16 ctrl;
1822 int ret;
1823
1824 /*
1825 * Signal Voltage Switching is only applicable for Host Controllers
1826 * v3.00 and above.
1827 */
1828 if (host->version < SDHCI_SPEC_300)
1829 return 0;
1830
1831 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1832
1833 switch (ios->signal_voltage) {
1834 case MMC_SIGNAL_VOLTAGE_330:
1835 if (!(host->flags & SDHCI_SIGNALING_330))
1836 return -EINVAL;
1837 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1838 ctrl &= ~SDHCI_CTRL_VDD_180;
1839 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1840
1841 if (!IS_ERR(mmc->supply.vqmmc)) {
1842 ret = mmc_regulator_set_vqmmc(mmc, ios);
1843 if (ret) {
1844 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1845 mmc_hostname(mmc));
1846 return -EIO;
1847 }
1848 }
1849 /* Wait for 5ms */
1850 usleep_range(5000, 5500);
1851
1852 /* 3.3V regulator output should be stable within 5 ms */
1853 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1854 if (!(ctrl & SDHCI_CTRL_VDD_180))
1855 return 0;
1856
1857 pr_warn("%s: 3.3V regulator output did not became stable\n",
1858 mmc_hostname(mmc));
1859
1860 return -EAGAIN;
1861 case MMC_SIGNAL_VOLTAGE_180:
1862 if (!(host->flags & SDHCI_SIGNALING_180))
1863 return -EINVAL;
1864 if (!IS_ERR(mmc->supply.vqmmc)) {
1865 ret = mmc_regulator_set_vqmmc(mmc, ios);
1866 if (ret) {
1867 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1868 mmc_hostname(mmc));
1869 return -EIO;
1870 }
1871 }
1872
1873 /*
1874 * Enable 1.8V Signal Enable in the Host Control2
1875 * register
1876 */
1877 ctrl |= SDHCI_CTRL_VDD_180;
1878 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1879
1880 /* Some controller need to do more when switching */
1881 if (host->ops->voltage_switch)
1882 host->ops->voltage_switch(host);
1883
1884 /* 1.8V regulator output should be stable within 5 ms */
1885 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1886 if (ctrl & SDHCI_CTRL_VDD_180)
1887 return 0;
1888
1889 pr_warn("%s: 1.8V regulator output did not became stable\n",
1890 mmc_hostname(mmc));
1891
1892 return -EAGAIN;
1893 case MMC_SIGNAL_VOLTAGE_120:
1894 if (!(host->flags & SDHCI_SIGNALING_120))
1895 return -EINVAL;
1896 if (!IS_ERR(mmc->supply.vqmmc)) {
1897 ret = mmc_regulator_set_vqmmc(mmc, ios);
1898 if (ret) {
1899 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1900 mmc_hostname(mmc));
1901 return -EIO;
1902 }
1903 }
1904 return 0;
1905 default:
1906 /* No signal voltage switch required */
1907 return 0;
1908 }
1909 }
1910
1911 static int sdhci_card_busy(struct mmc_host *mmc)
1912 {
1913 struct sdhci_host *host = mmc_priv(mmc);
1914 u32 present_state;
1915
1916 /* Check whether DAT[0] is 0 */
1917 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1918
1919 return !(present_state & SDHCI_DATA_0_LVL_MASK);
1920 }
1921
1922 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1923 {
1924 struct sdhci_host *host = mmc_priv(mmc);
1925 unsigned long flags;
1926
1927 spin_lock_irqsave(&host->lock, flags);
1928 host->flags |= SDHCI_HS400_TUNING;
1929 spin_unlock_irqrestore(&host->lock, flags);
1930
1931 return 0;
1932 }
1933
1934 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1935 {
1936 struct sdhci_host *host = mmc_priv(mmc);
1937 u16 ctrl;
1938 int tuning_loop_counter = MAX_TUNING_LOOP;
1939 int err = 0;
1940 unsigned long flags;
1941 unsigned int tuning_count = 0;
1942 bool hs400_tuning;
1943
1944 spin_lock_irqsave(&host->lock, flags);
1945
1946 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1947 host->flags &= ~SDHCI_HS400_TUNING;
1948
1949 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1950 tuning_count = host->tuning_count;
1951
1952 /*
1953 * The Host Controller needs tuning in case of SDR104 and DDR50
1954 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1955 * the Capabilities register.
1956 * If the Host Controller supports the HS200 mode then the
1957 * tuning function has to be executed.
1958 */
1959 switch (host->timing) {
1960 /* HS400 tuning is done in HS200 mode */
1961 case MMC_TIMING_MMC_HS400:
1962 err = -EINVAL;
1963 goto out_unlock;
1964
1965 case MMC_TIMING_MMC_HS200:
1966 /*
1967 * Periodic re-tuning for HS400 is not expected to be needed, so
1968 * disable it here.
1969 */
1970 if (hs400_tuning)
1971 tuning_count = 0;
1972 break;
1973
1974 case MMC_TIMING_UHS_SDR104:
1975 case MMC_TIMING_UHS_DDR50:
1976 break;
1977
1978 case MMC_TIMING_UHS_SDR50:
1979 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
1980 break;
1981 /* FALLTHROUGH */
1982
1983 default:
1984 goto out_unlock;
1985 }
1986
1987 if (host->ops->platform_execute_tuning) {
1988 spin_unlock_irqrestore(&host->lock, flags);
1989 err = host->ops->platform_execute_tuning(host, opcode);
1990 return err;
1991 }
1992
1993 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1994 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1995 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1996 ctrl |= SDHCI_CTRL_TUNED_CLK;
1997 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1998
1999 /*
2000 * As per the Host Controller spec v3.00, tuning command
2001 * generates Buffer Read Ready interrupt, so enable that.
2002 *
2003 * Note: The spec clearly says that when tuning sequence
2004 * is being performed, the controller does not generate
2005 * interrupts other than Buffer Read Ready interrupt. But
2006 * to make sure we don't hit a controller bug, we _only_
2007 * enable Buffer Read Ready interrupt here.
2008 */
2009 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2010 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2011
2012 /*
2013 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
2014 * of loops reaches 40 times.
2015 */
2016 do {
2017 struct mmc_command cmd = {0};
2018 struct mmc_request mrq = {NULL};
2019
2020 cmd.opcode = opcode;
2021 cmd.arg = 0;
2022 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2023 cmd.retries = 0;
2024 cmd.data = NULL;
2025 cmd.mrq = &mrq;
2026 cmd.error = 0;
2027
2028 if (tuning_loop_counter-- == 0)
2029 break;
2030
2031 mrq.cmd = &cmd;
2032
2033 /*
2034 * In response to CMD19, the card sends 64 bytes of tuning
2035 * block to the Host Controller. So we set the block size
2036 * to 64 here.
2037 */
2038 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
2039 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2040 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
2041 SDHCI_BLOCK_SIZE);
2042 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
2043 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2044 SDHCI_BLOCK_SIZE);
2045 } else {
2046 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2047 SDHCI_BLOCK_SIZE);
2048 }
2049
2050 /*
2051 * The tuning block is sent by the card to the host controller.
2052 * So we set the TRNS_READ bit in the Transfer Mode register.
2053 * This also takes care of setting DMA Enable and Multi Block
2054 * Select in the same register to 0.
2055 */
2056 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2057
2058 sdhci_send_command(host, &cmd);
2059
2060 host->cmd = NULL;
2061 sdhci_del_timer(host, &mrq);
2062
2063 spin_unlock_irqrestore(&host->lock, flags);
2064 /* Wait for Buffer Read Ready interrupt */
2065 wait_event_interruptible_timeout(host->buf_ready_int,
2066 (host->tuning_done == 1),
2067 msecs_to_jiffies(50));
2068 spin_lock_irqsave(&host->lock, flags);
2069
2070 if (!host->tuning_done) {
2071 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
2072 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2073 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2074 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2075 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2076
2077 err = -EIO;
2078 goto out;
2079 }
2080
2081 host->tuning_done = 0;
2082
2083 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2084
2085 /* eMMC spec does not require a delay between tuning cycles */
2086 if (opcode == MMC_SEND_TUNING_BLOCK)
2087 mdelay(1);
2088 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2089
2090 /*
2091 * The Host Driver has exhausted the maximum number of loops allowed,
2092 * so use fixed sampling frequency.
2093 */
2094 if (tuning_loop_counter < 0) {
2095 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2096 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2097 }
2098 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2099 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
2100 err = -EIO;
2101 }
2102
2103 out:
2104 if (tuning_count) {
2105 /*
2106 * In case tuning fails, host controllers which support
2107 * re-tuning can try tuning again at a later time, when the
2108 * re-tuning timer expires. So for these controllers, we
2109 * return 0. Since there might be other controllers who do not
2110 * have this capability, we return error for them.
2111 */
2112 err = 0;
2113 }
2114
2115 host->mmc->retune_period = err ? 0 : tuning_count;
2116
2117 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2118 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2119 out_unlock:
2120 spin_unlock_irqrestore(&host->lock, flags);
2121 return err;
2122 }
2123
2124 static int sdhci_select_drive_strength(struct mmc_card *card,
2125 unsigned int max_dtr, int host_drv,
2126 int card_drv, int *drv_type)
2127 {
2128 struct sdhci_host *host = mmc_priv(card->host);
2129
2130 if (!host->ops->select_drive_strength)
2131 return 0;
2132
2133 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2134 card_drv, drv_type);
2135 }
2136
2137 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2138 {
2139 /* Host Controller v3.00 defines preset value registers */
2140 if (host->version < SDHCI_SPEC_300)
2141 return;
2142
2143 /*
2144 * We only enable or disable Preset Value if they are not already
2145 * enabled or disabled respectively. Otherwise, we bail out.
2146 */
2147 if (host->preset_enabled != enable) {
2148 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2149
2150 if (enable)
2151 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2152 else
2153 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2154
2155 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2156
2157 if (enable)
2158 host->flags |= SDHCI_PV_ENABLED;
2159 else
2160 host->flags &= ~SDHCI_PV_ENABLED;
2161
2162 host->preset_enabled = enable;
2163 }
2164 }
2165
2166 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2167 int err)
2168 {
2169 struct sdhci_host *host = mmc_priv(mmc);
2170 struct mmc_data *data = mrq->data;
2171
2172 if (data->host_cookie != COOKIE_UNMAPPED)
2173 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2174 data->flags & MMC_DATA_WRITE ?
2175 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2176
2177 data->host_cookie = COOKIE_UNMAPPED;
2178 }
2179
2180 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2181 bool is_first_req)
2182 {
2183 struct sdhci_host *host = mmc_priv(mmc);
2184
2185 mrq->data->host_cookie = COOKIE_UNMAPPED;
2186
2187 if (host->flags & SDHCI_REQ_USE_DMA)
2188 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2189 }
2190
2191 static inline bool sdhci_has_requests(struct sdhci_host *host)
2192 {
2193 return host->cmd || host->data_cmd;
2194 }
2195
2196 static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2197 {
2198 if (host->data_cmd) {
2199 host->data_cmd->error = err;
2200 sdhci_finish_mrq(host, host->data_cmd->mrq);
2201 }
2202
2203 if (host->cmd) {
2204 host->cmd->error = err;
2205 sdhci_finish_mrq(host, host->cmd->mrq);
2206 }
2207 }
2208
2209 static void sdhci_card_event(struct mmc_host *mmc)
2210 {
2211 struct sdhci_host *host = mmc_priv(mmc);
2212 unsigned long flags;
2213 int present;
2214
2215 /* First check if client has provided their own card event */
2216 if (host->ops->card_event)
2217 host->ops->card_event(host);
2218
2219 present = mmc->ops->get_cd(mmc);
2220
2221 spin_lock_irqsave(&host->lock, flags);
2222
2223 /* Check sdhci_has_requests() first in case we are runtime suspended */
2224 if (sdhci_has_requests(host) && !present) {
2225 pr_err("%s: Card removed during transfer!\n",
2226 mmc_hostname(host->mmc));
2227 pr_err("%s: Resetting controller.\n",
2228 mmc_hostname(host->mmc));
2229
2230 sdhci_do_reset(host, SDHCI_RESET_CMD);
2231 sdhci_do_reset(host, SDHCI_RESET_DATA);
2232
2233 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2234 }
2235
2236 spin_unlock_irqrestore(&host->lock, flags);
2237 }
2238
2239 static const struct mmc_host_ops sdhci_ops = {
2240 .request = sdhci_request,
2241 .post_req = sdhci_post_req,
2242 .pre_req = sdhci_pre_req,
2243 .set_ios = sdhci_set_ios,
2244 .get_cd = sdhci_get_cd,
2245 .get_ro = sdhci_get_ro,
2246 .hw_reset = sdhci_hw_reset,
2247 .enable_sdio_irq = sdhci_enable_sdio_irq,
2248 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2249 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2250 .execute_tuning = sdhci_execute_tuning,
2251 .select_drive_strength = sdhci_select_drive_strength,
2252 .card_event = sdhci_card_event,
2253 .card_busy = sdhci_card_busy,
2254 };
2255
2256 /*****************************************************************************\
2257 * *
2258 * Tasklets *
2259 * *
2260 \*****************************************************************************/
2261
2262 static bool sdhci_request_done(struct sdhci_host *host)
2263 {
2264 unsigned long flags;
2265 struct mmc_request *mrq;
2266 int i;
2267
2268 spin_lock_irqsave(&host->lock, flags);
2269
2270 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2271 mrq = host->mrqs_done[i];
2272 if (mrq) {
2273 host->mrqs_done[i] = NULL;
2274 break;
2275 }
2276 }
2277
2278 if (!mrq) {
2279 spin_unlock_irqrestore(&host->lock, flags);
2280 return true;
2281 }
2282
2283 sdhci_del_timer(host, mrq);
2284
2285 /*
2286 * Always unmap the data buffers if they were mapped by
2287 * sdhci_prepare_data() whenever we finish with a request.
2288 * This avoids leaking DMA mappings on error.
2289 */
2290 if (host->flags & SDHCI_REQ_USE_DMA) {
2291 struct mmc_data *data = mrq->data;
2292
2293 if (data && data->host_cookie == COOKIE_MAPPED) {
2294 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2295 (data->flags & MMC_DATA_READ) ?
2296 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2297 data->host_cookie = COOKIE_UNMAPPED;
2298 }
2299 }
2300
2301 /*
2302 * The controller needs a reset of internal state machines
2303 * upon error conditions.
2304 */
2305 if (sdhci_needs_reset(host, mrq)) {
2306 /* Some controllers need this kick or reset won't work here */
2307 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2308 /* This is to force an update */
2309 host->ops->set_clock(host, host->clock);
2310
2311 /* Spec says we should do both at the same time, but Ricoh
2312 controllers do not like that. */
2313 if (!host->cmd)
2314 sdhci_do_reset(host, SDHCI_RESET_CMD);
2315 if (!host->data_cmd)
2316 sdhci_do_reset(host, SDHCI_RESET_DATA);
2317
2318 host->pending_reset = false;
2319 }
2320
2321 if (!sdhci_has_requests(host))
2322 sdhci_led_deactivate(host);
2323
2324 mmiowb();
2325 spin_unlock_irqrestore(&host->lock, flags);
2326
2327 mmc_request_done(host->mmc, mrq);
2328
2329 return false;
2330 }
2331
2332 static void sdhci_tasklet_finish(unsigned long param)
2333 {
2334 struct sdhci_host *host = (struct sdhci_host *)param;
2335
2336 while (!sdhci_request_done(host))
2337 ;
2338 }
2339
2340 static void sdhci_timeout_timer(unsigned long data)
2341 {
2342 struct sdhci_host *host;
2343 unsigned long flags;
2344
2345 host = (struct sdhci_host*)data;
2346
2347 spin_lock_irqsave(&host->lock, flags);
2348
2349 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2350 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2351 mmc_hostname(host->mmc));
2352 sdhci_dumpregs(host);
2353
2354 host->cmd->error = -ETIMEDOUT;
2355 sdhci_finish_mrq(host, host->cmd->mrq);
2356 }
2357
2358 mmiowb();
2359 spin_unlock_irqrestore(&host->lock, flags);
2360 }
2361
2362 static void sdhci_timeout_data_timer(unsigned long data)
2363 {
2364 struct sdhci_host *host;
2365 unsigned long flags;
2366
2367 host = (struct sdhci_host *)data;
2368
2369 spin_lock_irqsave(&host->lock, flags);
2370
2371 if (host->data || host->data_cmd ||
2372 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2373 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2374 mmc_hostname(host->mmc));
2375 sdhci_dumpregs(host);
2376
2377 if (host->data) {
2378 host->data->error = -ETIMEDOUT;
2379 sdhci_finish_data(host);
2380 } else if (host->data_cmd) {
2381 host->data_cmd->error = -ETIMEDOUT;
2382 sdhci_finish_mrq(host, host->data_cmd->mrq);
2383 } else {
2384 host->cmd->error = -ETIMEDOUT;
2385 sdhci_finish_mrq(host, host->cmd->mrq);
2386 }
2387 }
2388
2389 mmiowb();
2390 spin_unlock_irqrestore(&host->lock, flags);
2391 }
2392
2393 /*****************************************************************************\
2394 * *
2395 * Interrupt handling *
2396 * *
2397 \*****************************************************************************/
2398
2399 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2400 {
2401 if (!host->cmd) {
2402 /*
2403 * SDHCI recovers from errors by resetting the cmd and data
2404 * circuits. Until that is done, there very well might be more
2405 * interrupts, so ignore them in that case.
2406 */
2407 if (host->pending_reset)
2408 return;
2409 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2410 mmc_hostname(host->mmc), (unsigned)intmask);
2411 sdhci_dumpregs(host);
2412 return;
2413 }
2414
2415 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2416 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2417 if (intmask & SDHCI_INT_TIMEOUT)
2418 host->cmd->error = -ETIMEDOUT;
2419 else
2420 host->cmd->error = -EILSEQ;
2421
2422 /*
2423 * If this command initiates a data phase and a response
2424 * CRC error is signalled, the card can start transferring
2425 * data - the card may have received the command without
2426 * error. We must not terminate the mmc_request early.
2427 *
2428 * If the card did not receive the command or returned an
2429 * error which prevented it sending data, the data phase
2430 * will time out.
2431 */
2432 if (host->cmd->data &&
2433 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2434 SDHCI_INT_CRC) {
2435 host->cmd = NULL;
2436 return;
2437 }
2438
2439 sdhci_finish_mrq(host, host->cmd->mrq);
2440 return;
2441 }
2442
2443 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2444 !(host->cmd->flags & MMC_RSP_BUSY) && !host->data &&
2445 host->cmd->opcode == MMC_STOP_TRANSMISSION)
2446 *mask &= ~SDHCI_INT_DATA_END;
2447
2448 if (intmask & SDHCI_INT_RESPONSE)
2449 sdhci_finish_command(host);
2450 }
2451
2452 #ifdef CONFIG_MMC_DEBUG
2453 static void sdhci_adma_show_error(struct sdhci_host *host)
2454 {
2455 const char *name = mmc_hostname(host->mmc);
2456 void *desc = host->adma_table;
2457
2458 sdhci_dumpregs(host);
2459
2460 while (true) {
2461 struct sdhci_adma2_64_desc *dma_desc = desc;
2462
2463 if (host->flags & SDHCI_USE_64_BIT_DMA)
2464 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2465 name, desc, le32_to_cpu(dma_desc->addr_hi),
2466 le32_to_cpu(dma_desc->addr_lo),
2467 le16_to_cpu(dma_desc->len),
2468 le16_to_cpu(dma_desc->cmd));
2469 else
2470 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2471 name, desc, le32_to_cpu(dma_desc->addr_lo),
2472 le16_to_cpu(dma_desc->len),
2473 le16_to_cpu(dma_desc->cmd));
2474
2475 desc += host->desc_sz;
2476
2477 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2478 break;
2479 }
2480 }
2481 #else
2482 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2483 #endif
2484
2485 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2486 {
2487 u32 command;
2488
2489 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2490 if (intmask & SDHCI_INT_DATA_AVAIL) {
2491 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2492 if (command == MMC_SEND_TUNING_BLOCK ||
2493 command == MMC_SEND_TUNING_BLOCK_HS200) {
2494 host->tuning_done = 1;
2495 wake_up(&host->buf_ready_int);
2496 return;
2497 }
2498 }
2499
2500 if (!host->data) {
2501 struct mmc_command *data_cmd = host->data_cmd;
2502
2503 if (data_cmd)
2504 host->data_cmd = NULL;
2505
2506 /*
2507 * The "data complete" interrupt is also used to
2508 * indicate that a busy state has ended. See comment
2509 * above in sdhci_cmd_irq().
2510 */
2511 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
2512 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2513 data_cmd->error = -ETIMEDOUT;
2514 sdhci_finish_mrq(host, data_cmd->mrq);
2515 return;
2516 }
2517 if (intmask & SDHCI_INT_DATA_END) {
2518 /*
2519 * Some cards handle busy-end interrupt
2520 * before the command completed, so make
2521 * sure we do things in the proper order.
2522 */
2523 if (host->cmd == data_cmd)
2524 return;
2525
2526 sdhci_finish_mrq(host, data_cmd->mrq);
2527 return;
2528 }
2529 }
2530
2531 /*
2532 * SDHCI recovers from errors by resetting the cmd and data
2533 * circuits. Until that is done, there very well might be more
2534 * interrupts, so ignore them in that case.
2535 */
2536 if (host->pending_reset)
2537 return;
2538
2539 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2540 mmc_hostname(host->mmc), (unsigned)intmask);
2541 sdhci_dumpregs(host);
2542
2543 return;
2544 }
2545
2546 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2547 host->data->error = -ETIMEDOUT;
2548 else if (intmask & SDHCI_INT_DATA_END_BIT)
2549 host->data->error = -EILSEQ;
2550 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2551 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2552 != MMC_BUS_TEST_R)
2553 host->data->error = -EILSEQ;
2554 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2555 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2556 sdhci_adma_show_error(host);
2557 host->data->error = -EIO;
2558 if (host->ops->adma_workaround)
2559 host->ops->adma_workaround(host, intmask);
2560 }
2561
2562 if (host->data->error)
2563 sdhci_finish_data(host);
2564 else {
2565 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2566 sdhci_transfer_pio(host);
2567
2568 /*
2569 * We currently don't do anything fancy with DMA
2570 * boundaries, but as we can't disable the feature
2571 * we need to at least restart the transfer.
2572 *
2573 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2574 * should return a valid address to continue from, but as
2575 * some controllers are faulty, don't trust them.
2576 */
2577 if (intmask & SDHCI_INT_DMA_END) {
2578 u32 dmastart, dmanow;
2579 dmastart = sg_dma_address(host->data->sg);
2580 dmanow = dmastart + host->data->bytes_xfered;
2581 /*
2582 * Force update to the next DMA block boundary.
2583 */
2584 dmanow = (dmanow &
2585 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2586 SDHCI_DEFAULT_BOUNDARY_SIZE;
2587 host->data->bytes_xfered = dmanow - dmastart;
2588 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2589 " next 0x%08x\n",
2590 mmc_hostname(host->mmc), dmastart,
2591 host->data->bytes_xfered, dmanow);
2592 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2593 }
2594
2595 if (intmask & SDHCI_INT_DATA_END) {
2596 if (host->cmd == host->data_cmd) {
2597 /*
2598 * Data managed to finish before the
2599 * command completed. Make sure we do
2600 * things in the proper order.
2601 */
2602 host->data_early = 1;
2603 } else {
2604 sdhci_finish_data(host);
2605 }
2606 }
2607 }
2608 }
2609
2610 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2611 {
2612 irqreturn_t result = IRQ_NONE;
2613 struct sdhci_host *host = dev_id;
2614 u32 intmask, mask, unexpected = 0;
2615 int max_loops = 16;
2616
2617 spin_lock(&host->lock);
2618
2619 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2620 spin_unlock(&host->lock);
2621 return IRQ_NONE;
2622 }
2623
2624 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2625 if (!intmask || intmask == 0xffffffff) {
2626 result = IRQ_NONE;
2627 goto out;
2628 }
2629
2630 do {
2631 /* Clear selected interrupts. */
2632 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2633 SDHCI_INT_BUS_POWER);
2634 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2635
2636 DBG("*** %s got interrupt: 0x%08x\n",
2637 mmc_hostname(host->mmc), intmask);
2638
2639 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2640 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2641 SDHCI_CARD_PRESENT;
2642
2643 /*
2644 * There is a observation on i.mx esdhc. INSERT
2645 * bit will be immediately set again when it gets
2646 * cleared, if a card is inserted. We have to mask
2647 * the irq to prevent interrupt storm which will
2648 * freeze the system. And the REMOVE gets the
2649 * same situation.
2650 *
2651 * More testing are needed here to ensure it works
2652 * for other platforms though.
2653 */
2654 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2655 SDHCI_INT_CARD_REMOVE);
2656 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2657 SDHCI_INT_CARD_INSERT;
2658 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2659 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2660
2661 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2662 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2663
2664 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2665 SDHCI_INT_CARD_REMOVE);
2666 result = IRQ_WAKE_THREAD;
2667 }
2668
2669 if (intmask & SDHCI_INT_CMD_MASK)
2670 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2671 &intmask);
2672
2673 if (intmask & SDHCI_INT_DATA_MASK)
2674 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2675
2676 if (intmask & SDHCI_INT_BUS_POWER)
2677 pr_err("%s: Card is consuming too much power!\n",
2678 mmc_hostname(host->mmc));
2679
2680 if (intmask & SDHCI_INT_RETUNE)
2681 mmc_retune_needed(host->mmc);
2682
2683 if (intmask & SDHCI_INT_CARD_INT) {
2684 sdhci_enable_sdio_irq_nolock(host, false);
2685 host->thread_isr |= SDHCI_INT_CARD_INT;
2686 result = IRQ_WAKE_THREAD;
2687 }
2688
2689 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2690 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2691 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2692 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
2693
2694 if (intmask) {
2695 unexpected |= intmask;
2696 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2697 }
2698
2699 if (result == IRQ_NONE)
2700 result = IRQ_HANDLED;
2701
2702 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2703 } while (intmask && --max_loops);
2704 out:
2705 spin_unlock(&host->lock);
2706
2707 if (unexpected) {
2708 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2709 mmc_hostname(host->mmc), unexpected);
2710 sdhci_dumpregs(host);
2711 }
2712
2713 return result;
2714 }
2715
2716 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2717 {
2718 struct sdhci_host *host = dev_id;
2719 unsigned long flags;
2720 u32 isr;
2721
2722 spin_lock_irqsave(&host->lock, flags);
2723 isr = host->thread_isr;
2724 host->thread_isr = 0;
2725 spin_unlock_irqrestore(&host->lock, flags);
2726
2727 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2728 struct mmc_host *mmc = host->mmc;
2729
2730 mmc->ops->card_event(mmc);
2731 mmc_detect_change(mmc, msecs_to_jiffies(200));
2732 }
2733
2734 if (isr & SDHCI_INT_CARD_INT) {
2735 sdio_run_irqs(host->mmc);
2736
2737 spin_lock_irqsave(&host->lock, flags);
2738 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2739 sdhci_enable_sdio_irq_nolock(host, true);
2740 spin_unlock_irqrestore(&host->lock, flags);
2741 }
2742
2743 return isr ? IRQ_HANDLED : IRQ_NONE;
2744 }
2745
2746 /*****************************************************************************\
2747 * *
2748 * Suspend/resume *
2749 * *
2750 \*****************************************************************************/
2751
2752 #ifdef CONFIG_PM
2753 /*
2754 * To enable wakeup events, the corresponding events have to be enabled in
2755 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2756 * Table' in the SD Host Controller Standard Specification.
2757 * It is useless to restore SDHCI_INT_ENABLE state in
2758 * sdhci_disable_irq_wakeups() since it will be set by
2759 * sdhci_enable_card_detection() or sdhci_init().
2760 */
2761 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2762 {
2763 u8 val;
2764 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2765 | SDHCI_WAKE_ON_INT;
2766 u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2767 SDHCI_INT_CARD_INT;
2768
2769 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2770 val |= mask ;
2771 /* Avoid fake wake up */
2772 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) {
2773 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2774 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2775 }
2776 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2777 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
2778 }
2779 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2780
2781 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2782 {
2783 u8 val;
2784 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2785 | SDHCI_WAKE_ON_INT;
2786
2787 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2788 val &= ~mask;
2789 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2790 }
2791
2792 int sdhci_suspend_host(struct sdhci_host *host)
2793 {
2794 sdhci_disable_card_detection(host);
2795
2796 mmc_retune_timer_stop(host->mmc);
2797 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
2798 mmc_retune_needed(host->mmc);
2799
2800 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2801 host->ier = 0;
2802 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2803 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2804 free_irq(host->irq, host);
2805 } else {
2806 sdhci_enable_irq_wakeups(host);
2807 enable_irq_wake(host->irq);
2808 }
2809 return 0;
2810 }
2811
2812 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2813
2814 int sdhci_resume_host(struct sdhci_host *host)
2815 {
2816 struct mmc_host *mmc = host->mmc;
2817 int ret = 0;
2818
2819 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2820 if (host->ops->enable_dma)
2821 host->ops->enable_dma(host);
2822 }
2823
2824 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2825 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2826 /* Card keeps power but host controller does not */
2827 sdhci_init(host, 0);
2828 host->pwr = 0;
2829 host->clock = 0;
2830 mmc->ops->set_ios(mmc, &mmc->ios);
2831 } else {
2832 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2833 mmiowb();
2834 }
2835
2836 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2837 ret = request_threaded_irq(host->irq, sdhci_irq,
2838 sdhci_thread_irq, IRQF_SHARED,
2839 mmc_hostname(host->mmc), host);
2840 if (ret)
2841 return ret;
2842 } else {
2843 sdhci_disable_irq_wakeups(host);
2844 disable_irq_wake(host->irq);
2845 }
2846
2847 sdhci_enable_card_detection(host);
2848
2849 return ret;
2850 }
2851
2852 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2853
2854 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2855 {
2856 unsigned long flags;
2857
2858 mmc_retune_timer_stop(host->mmc);
2859 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
2860 mmc_retune_needed(host->mmc);
2861
2862 spin_lock_irqsave(&host->lock, flags);
2863 host->ier &= SDHCI_INT_CARD_INT;
2864 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2865 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2866 spin_unlock_irqrestore(&host->lock, flags);
2867
2868 synchronize_hardirq(host->irq);
2869
2870 spin_lock_irqsave(&host->lock, flags);
2871 host->runtime_suspended = true;
2872 spin_unlock_irqrestore(&host->lock, flags);
2873
2874 return 0;
2875 }
2876 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2877
2878 int sdhci_runtime_resume_host(struct sdhci_host *host)
2879 {
2880 struct mmc_host *mmc = host->mmc;
2881 unsigned long flags;
2882 int host_flags = host->flags;
2883
2884 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2885 if (host->ops->enable_dma)
2886 host->ops->enable_dma(host);
2887 }
2888
2889 sdhci_init(host, 0);
2890
2891 /* Force clock and power re-program */
2892 host->pwr = 0;
2893 host->clock = 0;
2894 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
2895 mmc->ops->set_ios(mmc, &mmc->ios);
2896
2897 if ((host_flags & SDHCI_PV_ENABLED) &&
2898 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2899 spin_lock_irqsave(&host->lock, flags);
2900 sdhci_enable_preset_value(host, true);
2901 spin_unlock_irqrestore(&host->lock, flags);
2902 }
2903
2904 spin_lock_irqsave(&host->lock, flags);
2905
2906 host->runtime_suspended = false;
2907
2908 /* Enable SDIO IRQ */
2909 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2910 sdhci_enable_sdio_irq_nolock(host, true);
2911
2912 /* Enable Card Detection */
2913 sdhci_enable_card_detection(host);
2914
2915 spin_unlock_irqrestore(&host->lock, flags);
2916
2917 return 0;
2918 }
2919 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2920
2921 #endif /* CONFIG_PM */
2922
2923 /*****************************************************************************\
2924 * *
2925 * Device allocation/registration *
2926 * *
2927 \*****************************************************************************/
2928
2929 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2930 size_t priv_size)
2931 {
2932 struct mmc_host *mmc;
2933 struct sdhci_host *host;
2934
2935 WARN_ON(dev == NULL);
2936
2937 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2938 if (!mmc)
2939 return ERR_PTR(-ENOMEM);
2940
2941 host = mmc_priv(mmc);
2942 host->mmc = mmc;
2943 host->mmc_host_ops = sdhci_ops;
2944 mmc->ops = &host->mmc_host_ops;
2945
2946 host->flags = SDHCI_SIGNALING_330;
2947
2948 return host;
2949 }
2950
2951 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2952
2953 static int sdhci_set_dma_mask(struct sdhci_host *host)
2954 {
2955 struct mmc_host *mmc = host->mmc;
2956 struct device *dev = mmc_dev(mmc);
2957 int ret = -EINVAL;
2958
2959 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
2960 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2961
2962 /* Try 64-bit mask if hardware is capable of it */
2963 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2964 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
2965 if (ret) {
2966 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
2967 mmc_hostname(mmc));
2968 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2969 }
2970 }
2971
2972 /* 32-bit mask as default & fallback */
2973 if (ret) {
2974 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
2975 if (ret)
2976 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
2977 mmc_hostname(mmc));
2978 }
2979
2980 return ret;
2981 }
2982
2983 void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
2984 {
2985 u16 v;
2986
2987 if (host->read_caps)
2988 return;
2989
2990 host->read_caps = true;
2991
2992 if (debug_quirks)
2993 host->quirks = debug_quirks;
2994
2995 if (debug_quirks2)
2996 host->quirks2 = debug_quirks2;
2997
2998 sdhci_do_reset(host, SDHCI_RESET_ALL);
2999
3000 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3001 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3002
3003 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3004 return;
3005
3006 host->caps = caps ? *caps : sdhci_readl(host, SDHCI_CAPABILITIES);
3007
3008 if (host->version < SDHCI_SPEC_300)
3009 return;
3010
3011 host->caps1 = caps1 ? *caps1 : sdhci_readl(host, SDHCI_CAPABILITIES_1);
3012 }
3013 EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3014
3015 int sdhci_setup_host(struct sdhci_host *host)
3016 {
3017 struct mmc_host *mmc;
3018 u32 max_current_caps;
3019 unsigned int ocr_avail;
3020 unsigned int override_timeout_clk;
3021 u32 max_clk;
3022 int ret;
3023
3024 WARN_ON(host == NULL);
3025 if (host == NULL)
3026 return -EINVAL;
3027
3028 mmc = host->mmc;
3029
3030 /*
3031 * If there are external regulators, get them. Note this must be done
3032 * early before resetting the host and reading the capabilities so that
3033 * the host can take the appropriate action if regulators are not
3034 * available.
3035 */
3036 ret = mmc_regulator_get_supply(mmc);
3037 if (ret == -EPROBE_DEFER)
3038 return ret;
3039
3040 sdhci_read_caps(host);
3041
3042 override_timeout_clk = host->timeout_clk;
3043
3044 if (host->version > SDHCI_SPEC_300) {
3045 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3046 mmc_hostname(mmc), host->version);
3047 }
3048
3049 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3050 host->flags |= SDHCI_USE_SDMA;
3051 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
3052 DBG("Controller doesn't have SDMA capability\n");
3053 else
3054 host->flags |= SDHCI_USE_SDMA;
3055
3056 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
3057 (host->flags & SDHCI_USE_SDMA)) {
3058 DBG("Disabling DMA as it is marked broken\n");
3059 host->flags &= ~SDHCI_USE_SDMA;
3060 }
3061
3062 if ((host->version >= SDHCI_SPEC_200) &&
3063 (host->caps & SDHCI_CAN_DO_ADMA2))
3064 host->flags |= SDHCI_USE_ADMA;
3065
3066 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3067 (host->flags & SDHCI_USE_ADMA)) {
3068 DBG("Disabling ADMA as it is marked broken\n");
3069 host->flags &= ~SDHCI_USE_ADMA;
3070 }
3071
3072 /*
3073 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3074 * and *must* do 64-bit DMA. A driver has the opportunity to change
3075 * that during the first call to ->enable_dma(). Similarly
3076 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3077 * implement.
3078 */
3079 if (host->caps & SDHCI_CAN_64BIT)
3080 host->flags |= SDHCI_USE_64_BIT_DMA;
3081
3082 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3083 ret = sdhci_set_dma_mask(host);
3084
3085 if (!ret && host->ops->enable_dma)
3086 ret = host->ops->enable_dma(host);
3087
3088 if (ret) {
3089 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3090 mmc_hostname(mmc));
3091 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3092
3093 ret = 0;
3094 }
3095 }
3096
3097 /* SDMA does not support 64-bit DMA */
3098 if (host->flags & SDHCI_USE_64_BIT_DMA)
3099 host->flags &= ~SDHCI_USE_SDMA;
3100
3101 if (host->flags & SDHCI_USE_ADMA) {
3102 dma_addr_t dma;
3103 void *buf;
3104
3105 /*
3106 * The DMA descriptor table size is calculated as the maximum
3107 * number of segments times 2, to allow for an alignment
3108 * descriptor for each segment, plus 1 for a nop end descriptor,
3109 * all multipled by the descriptor size.
3110 */
3111 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3112 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3113 SDHCI_ADMA2_64_DESC_SZ;
3114 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3115 } else {
3116 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3117 SDHCI_ADMA2_32_DESC_SZ;
3118 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3119 }
3120
3121 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
3122 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
3123 host->adma_table_sz, &dma, GFP_KERNEL);
3124 if (!buf) {
3125 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3126 mmc_hostname(mmc));
3127 host->flags &= ~SDHCI_USE_ADMA;
3128 } else if ((dma + host->align_buffer_sz) &
3129 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
3130 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3131 mmc_hostname(mmc));
3132 host->flags &= ~SDHCI_USE_ADMA;
3133 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3134 host->adma_table_sz, buf, dma);
3135 } else {
3136 host->align_buffer = buf;
3137 host->align_addr = dma;
3138
3139 host->adma_table = buf + host->align_buffer_sz;
3140 host->adma_addr = dma + host->align_buffer_sz;
3141 }
3142 }
3143
3144 /*
3145 * If we use DMA, then it's up to the caller to set the DMA
3146 * mask, but PIO does not need the hw shim so we set a new
3147 * mask here in that case.
3148 */
3149 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3150 host->dma_mask = DMA_BIT_MASK(64);
3151 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3152 }
3153
3154 if (host->version >= SDHCI_SPEC_300)
3155 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
3156 >> SDHCI_CLOCK_BASE_SHIFT;
3157 else
3158 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
3159 >> SDHCI_CLOCK_BASE_SHIFT;
3160
3161 host->max_clk *= 1000000;
3162 if (host->max_clk == 0 || host->quirks &
3163 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3164 if (!host->ops->get_max_clock) {
3165 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3166 mmc_hostname(mmc));
3167 ret = -ENODEV;
3168 goto undma;
3169 }
3170 host->max_clk = host->ops->get_max_clock(host);
3171 }
3172
3173 /*
3174 * In case of Host Controller v3.00, find out whether clock
3175 * multiplier is supported.
3176 */
3177 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
3178 SDHCI_CLOCK_MUL_SHIFT;
3179
3180 /*
3181 * In case the value in Clock Multiplier is 0, then programmable
3182 * clock mode is not supported, otherwise the actual clock
3183 * multiplier is one more than the value of Clock Multiplier
3184 * in the Capabilities Register.
3185 */
3186 if (host->clk_mul)
3187 host->clk_mul += 1;
3188
3189 /*
3190 * Set host parameters.
3191 */
3192 max_clk = host->max_clk;
3193
3194 if (host->ops->get_min_clock)
3195 mmc->f_min = host->ops->get_min_clock(host);
3196 else if (host->version >= SDHCI_SPEC_300) {
3197 if (host->clk_mul) {
3198 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3199 max_clk = host->max_clk * host->clk_mul;
3200 } else
3201 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3202 } else
3203 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3204
3205 if (!mmc->f_max || mmc->f_max > max_clk)
3206 mmc->f_max = max_clk;
3207
3208 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3209 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
3210 SDHCI_TIMEOUT_CLK_SHIFT;
3211 if (host->timeout_clk == 0) {
3212 if (host->ops->get_timeout_clock) {
3213 host->timeout_clk =
3214 host->ops->get_timeout_clock(host);
3215 } else {
3216 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3217 mmc_hostname(mmc));
3218 ret = -ENODEV;
3219 goto undma;
3220 }
3221 }
3222
3223 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
3224 host->timeout_clk *= 1000;
3225
3226 if (override_timeout_clk)
3227 host->timeout_clk = override_timeout_clk;
3228
3229 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3230 host->ops->get_max_timeout_count(host) : 1 << 27;
3231 mmc->max_busy_timeout /= host->timeout_clk;
3232 }
3233
3234 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3235 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3236
3237 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3238 host->flags |= SDHCI_AUTO_CMD12;
3239
3240 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3241 if ((host->version >= SDHCI_SPEC_300) &&
3242 ((host->flags & SDHCI_USE_ADMA) ||
3243 !(host->flags & SDHCI_USE_SDMA)) &&
3244 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3245 host->flags |= SDHCI_AUTO_CMD23;
3246 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3247 } else {
3248 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3249 }
3250
3251 /*
3252 * A controller may support 8-bit width, but the board itself
3253 * might not have the pins brought out. Boards that support
3254 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3255 * their platform code before calling sdhci_add_host(), and we
3256 * won't assume 8-bit width for hosts without that CAP.
3257 */
3258 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3259 mmc->caps |= MMC_CAP_4_BIT_DATA;
3260
3261 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3262 mmc->caps &= ~MMC_CAP_CMD23;
3263
3264 if (host->caps & SDHCI_CAN_DO_HISPD)
3265 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3266
3267 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3268 mmc_card_is_removable(mmc) &&
3269 mmc_gpio_get_cd(host->mmc) < 0)
3270 mmc->caps |= MMC_CAP_NEEDS_POLL;
3271
3272 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3273 if (!IS_ERR(mmc->supply.vqmmc)) {
3274 ret = regulator_enable(mmc->supply.vqmmc);
3275 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3276 1950000))
3277 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3278 SDHCI_SUPPORT_SDR50 |
3279 SDHCI_SUPPORT_DDR50);
3280 if (ret) {
3281 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3282 mmc_hostname(mmc), ret);
3283 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3284 }
3285 }
3286
3287 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3288 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3289 SDHCI_SUPPORT_DDR50);
3290 }
3291
3292 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3293 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3294 SDHCI_SUPPORT_DDR50))
3295 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3296
3297 /* SDR104 supports also implies SDR50 support */
3298 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
3299 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3300 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3301 * field can be promoted to support HS200.
3302 */
3303 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3304 mmc->caps2 |= MMC_CAP2_HS200;
3305 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
3306 mmc->caps |= MMC_CAP_UHS_SDR50;
3307 }
3308
3309 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3310 (host->caps1 & SDHCI_SUPPORT_HS400))
3311 mmc->caps2 |= MMC_CAP2_HS400;
3312
3313 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3314 (IS_ERR(mmc->supply.vqmmc) ||
3315 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3316 1300000)))
3317 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3318
3319 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3320 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3321 mmc->caps |= MMC_CAP_UHS_DDR50;
3322
3323 /* Does the host need tuning for SDR50? */
3324 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
3325 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3326
3327 /* Driver Type(s) (A, C, D) supported by the host */
3328 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
3329 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3330 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
3331 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3332 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
3333 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3334
3335 /* Initial value for re-tuning timer count */
3336 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3337 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3338
3339 /*
3340 * In case Re-tuning Timer is not disabled, the actual value of
3341 * re-tuning timer will be 2 ^ (n - 1).
3342 */
3343 if (host->tuning_count)
3344 host->tuning_count = 1 << (host->tuning_count - 1);
3345
3346 /* Re-tuning mode supported by the Host Controller */
3347 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
3348 SDHCI_RETUNING_MODE_SHIFT;
3349
3350 ocr_avail = 0;
3351
3352 /*
3353 * According to SD Host Controller spec v3.00, if the Host System
3354 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3355 * the value is meaningful only if Voltage Support in the Capabilities
3356 * register is set. The actual current value is 4 times the register
3357 * value.
3358 */
3359 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3360 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3361 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3362 if (curr > 0) {
3363
3364 /* convert to SDHCI_MAX_CURRENT format */
3365 curr = curr/1000; /* convert to mA */
3366 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3367
3368 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3369 max_current_caps =
3370 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3371 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3372 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3373 }
3374 }
3375
3376 if (host->caps & SDHCI_CAN_VDD_330) {
3377 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3378
3379 mmc->max_current_330 = ((max_current_caps &
3380 SDHCI_MAX_CURRENT_330_MASK) >>
3381 SDHCI_MAX_CURRENT_330_SHIFT) *
3382 SDHCI_MAX_CURRENT_MULTIPLIER;
3383 }
3384 if (host->caps & SDHCI_CAN_VDD_300) {
3385 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3386
3387 mmc->max_current_300 = ((max_current_caps &
3388 SDHCI_MAX_CURRENT_300_MASK) >>
3389 SDHCI_MAX_CURRENT_300_SHIFT) *
3390 SDHCI_MAX_CURRENT_MULTIPLIER;
3391 }
3392 if (host->caps & SDHCI_CAN_VDD_180) {
3393 ocr_avail |= MMC_VDD_165_195;
3394
3395 mmc->max_current_180 = ((max_current_caps &
3396 SDHCI_MAX_CURRENT_180_MASK) >>
3397 SDHCI_MAX_CURRENT_180_SHIFT) *
3398 SDHCI_MAX_CURRENT_MULTIPLIER;
3399 }
3400
3401 /* If OCR set by host, use it instead. */
3402 if (host->ocr_mask)
3403 ocr_avail = host->ocr_mask;
3404
3405 /* If OCR set by external regulators, give it highest prio. */
3406 if (mmc->ocr_avail)
3407 ocr_avail = mmc->ocr_avail;
3408
3409 mmc->ocr_avail = ocr_avail;
3410 mmc->ocr_avail_sdio = ocr_avail;
3411 if (host->ocr_avail_sdio)
3412 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3413 mmc->ocr_avail_sd = ocr_avail;
3414 if (host->ocr_avail_sd)
3415 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3416 else /* normal SD controllers don't support 1.8V */
3417 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3418 mmc->ocr_avail_mmc = ocr_avail;
3419 if (host->ocr_avail_mmc)
3420 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3421
3422 if (mmc->ocr_avail == 0) {
3423 pr_err("%s: Hardware doesn't report any support voltages.\n",
3424 mmc_hostname(mmc));
3425 ret = -ENODEV;
3426 goto unreg;
3427 }
3428
3429 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3430 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3431 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3432 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3433 host->flags |= SDHCI_SIGNALING_180;
3434
3435 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3436 host->flags |= SDHCI_SIGNALING_120;
3437
3438 spin_lock_init(&host->lock);
3439
3440 /*
3441 * Maximum number of segments. Depends on if the hardware
3442 * can do scatter/gather or not.
3443 */
3444 if (host->flags & SDHCI_USE_ADMA)
3445 mmc->max_segs = SDHCI_MAX_SEGS;
3446 else if (host->flags & SDHCI_USE_SDMA)
3447 mmc->max_segs = 1;
3448 else /* PIO */
3449 mmc->max_segs = SDHCI_MAX_SEGS;
3450
3451 /*
3452 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3453 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3454 * is less anyway.
3455 */
3456 mmc->max_req_size = 524288;
3457
3458 /*
3459 * Maximum segment size. Could be one segment with the maximum number
3460 * of bytes. When doing hardware scatter/gather, each entry cannot
3461 * be larger than 64 KiB though.
3462 */
3463 if (host->flags & SDHCI_USE_ADMA) {
3464 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3465 mmc->max_seg_size = 65535;
3466 else
3467 mmc->max_seg_size = 65536;
3468 } else {
3469 mmc->max_seg_size = mmc->max_req_size;
3470 }
3471
3472 /*
3473 * Maximum block size. This varies from controller to controller and
3474 * is specified in the capabilities register.
3475 */
3476 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3477 mmc->max_blk_size = 2;
3478 } else {
3479 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
3480 SDHCI_MAX_BLOCK_SHIFT;
3481 if (mmc->max_blk_size >= 3) {
3482 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3483 mmc_hostname(mmc));
3484 mmc->max_blk_size = 0;
3485 }
3486 }
3487
3488 mmc->max_blk_size = 512 << mmc->max_blk_size;
3489
3490 /*
3491 * Maximum block count.
3492 */
3493 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3494
3495 return 0;
3496
3497 unreg:
3498 if (!IS_ERR(mmc->supply.vqmmc))
3499 regulator_disable(mmc->supply.vqmmc);
3500 undma:
3501 if (host->align_buffer)
3502 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3503 host->adma_table_sz, host->align_buffer,
3504 host->align_addr);
3505 host->adma_table = NULL;
3506 host->align_buffer = NULL;
3507
3508 return ret;
3509 }
3510 EXPORT_SYMBOL_GPL(sdhci_setup_host);
3511
3512 int __sdhci_add_host(struct sdhci_host *host)
3513 {
3514 struct mmc_host *mmc = host->mmc;
3515 int ret;
3516
3517 /*
3518 * Init tasklets.
3519 */
3520 tasklet_init(&host->finish_tasklet,
3521 sdhci_tasklet_finish, (unsigned long)host);
3522
3523 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3524 setup_timer(&host->data_timer, sdhci_timeout_data_timer,
3525 (unsigned long)host);
3526
3527 init_waitqueue_head(&host->buf_ready_int);
3528
3529 sdhci_init(host, 0);
3530
3531 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3532 IRQF_SHARED, mmc_hostname(mmc), host);
3533 if (ret) {
3534 pr_err("%s: Failed to request IRQ %d: %d\n",
3535 mmc_hostname(mmc), host->irq, ret);
3536 goto untasklet;
3537 }
3538
3539 #ifdef CONFIG_MMC_DEBUG
3540 sdhci_dumpregs(host);
3541 #endif
3542
3543 ret = sdhci_led_register(host);
3544 if (ret) {
3545 pr_err("%s: Failed to register LED device: %d\n",
3546 mmc_hostname(mmc), ret);
3547 goto unirq;
3548 }
3549
3550 mmiowb();
3551
3552 ret = mmc_add_host(mmc);
3553 if (ret)
3554 goto unled;
3555
3556 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3557 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3558 (host->flags & SDHCI_USE_ADMA) ?
3559 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3560 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3561
3562 sdhci_enable_card_detection(host);
3563
3564 return 0;
3565
3566 unled:
3567 sdhci_led_unregister(host);
3568 unirq:
3569 sdhci_do_reset(host, SDHCI_RESET_ALL);
3570 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3571 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3572 free_irq(host->irq, host);
3573 untasklet:
3574 tasklet_kill(&host->finish_tasklet);
3575
3576 if (!IS_ERR(mmc->supply.vqmmc))
3577 regulator_disable(mmc->supply.vqmmc);
3578
3579 if (host->align_buffer)
3580 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3581 host->adma_table_sz, host->align_buffer,
3582 host->align_addr);
3583 host->adma_table = NULL;
3584 host->align_buffer = NULL;
3585
3586 return ret;
3587 }
3588 EXPORT_SYMBOL_GPL(__sdhci_add_host);
3589
3590 int sdhci_add_host(struct sdhci_host *host)
3591 {
3592 int ret;
3593
3594 ret = sdhci_setup_host(host);
3595 if (ret)
3596 return ret;
3597
3598 return __sdhci_add_host(host);
3599 }
3600 EXPORT_SYMBOL_GPL(sdhci_add_host);
3601
3602 void sdhci_remove_host(struct sdhci_host *host, int dead)
3603 {
3604 struct mmc_host *mmc = host->mmc;
3605 unsigned long flags;
3606
3607 if (dead) {
3608 spin_lock_irqsave(&host->lock, flags);
3609
3610 host->flags |= SDHCI_DEVICE_DEAD;
3611
3612 if (sdhci_has_requests(host)) {
3613 pr_err("%s: Controller removed during "
3614 " transfer!\n", mmc_hostname(mmc));
3615 sdhci_error_out_mrqs(host, -ENOMEDIUM);
3616 }
3617
3618 spin_unlock_irqrestore(&host->lock, flags);
3619 }
3620
3621 sdhci_disable_card_detection(host);
3622
3623 mmc_remove_host(mmc);
3624
3625 sdhci_led_unregister(host);
3626
3627 if (!dead)
3628 sdhci_do_reset(host, SDHCI_RESET_ALL);
3629
3630 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3631 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3632 free_irq(host->irq, host);
3633
3634 del_timer_sync(&host->timer);
3635 del_timer_sync(&host->data_timer);
3636
3637 tasklet_kill(&host->finish_tasklet);
3638
3639 if (!IS_ERR(mmc->supply.vqmmc))
3640 regulator_disable(mmc->supply.vqmmc);
3641
3642 if (host->align_buffer)
3643 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3644 host->adma_table_sz, host->align_buffer,
3645 host->align_addr);
3646
3647 host->adma_table = NULL;
3648 host->align_buffer = NULL;
3649 }
3650
3651 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3652
3653 void sdhci_free_host(struct sdhci_host *host)
3654 {
3655 mmc_free_host(host->mmc);
3656 }
3657
3658 EXPORT_SYMBOL_GPL(sdhci_free_host);
3659
3660 /*****************************************************************************\
3661 * *
3662 * Driver init/exit *
3663 * *
3664 \*****************************************************************************/
3665
3666 static int __init sdhci_drv_init(void)
3667 {
3668 pr_info(DRIVER_NAME
3669 ": Secure Digital Host Controller Interface driver\n");
3670 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3671
3672 return 0;
3673 }
3674
3675 static void __exit sdhci_drv_exit(void)
3676 {
3677 }
3678
3679 module_init(sdhci_drv_init);
3680 module_exit(sdhci_drv_exit);
3681
3682 module_param(debug_quirks, uint, 0444);
3683 module_param(debug_quirks2, uint, 0444);
3684
3685 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3686 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3687 MODULE_LICENSE("GPL");
3688
3689 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3690 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux with added FPC-III support