drivers/mmc/host/sdhci.h

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
   3  *
   4  * Header file for Host Controller registers and I/O accessors.
   5  *
   6  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or (at
  11  * your option) any later version.
  12  */
  13 #ifndef __SDHCI_HW_H
  14 #define __SDHCI_HW_H
  15
  16 #include <linux/scatterlist.h>
  17 #include <linux/compiler.h>
  18 #include <linux/types.h>
  19 #include <linux/io.h>
  20
  21 #include <linux/mmc/host.h>
  22
  23 /*
  24  * Controller registers
  25  */
  26
  27 #define SDHCI_DMA_ADDRESS       0x00
  28 #define SDHCI_ARGUMENT2         SDHCI_DMA_ADDRESS
  29
  30 #define SDHCI_BLOCK_SIZE        0x04
  31 #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
  32
  33 #define SDHCI_BLOCK_COUNT       0x06
  34
  35 #define SDHCI_ARGUMENT          0x08
  36
  37 #define SDHCI_TRANSFER_MODE     0x0C
  38 #define  SDHCI_TRNS_DMA         0x01
  39 #define  SDHCI_TRNS_BLK_CNT_EN  0x02
  40 #define  SDHCI_TRNS_AUTO_CMD12  0x04
  41 #define  SDHCI_TRNS_AUTO_CMD23  0x08
  42 #define  SDHCI_TRNS_READ        0x10
  43 #define  SDHCI_TRNS_MULTI       0x20
  44
  45 #define SDHCI_COMMAND           0x0E
  46 #define  SDHCI_CMD_RESP_MASK    0x03
  47 #define  SDHCI_CMD_CRC          0x08
  48 #define  SDHCI_CMD_INDEX        0x10
  49 #define  SDHCI_CMD_DATA         0x20
  50 #define  SDHCI_CMD_ABORTCMD     0xC0
  51
  52 #define  SDHCI_CMD_RESP_NONE    0x00
  53 #define  SDHCI_CMD_RESP_LONG    0x01
  54 #define  SDHCI_CMD_RESP_SHORT   0x02
  55 #define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
  56
  57 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
  58 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
  59
  60 #define SDHCI_RESPONSE          0x10
  61
  62 #define SDHCI_BUFFER            0x20
  63
  64 #define SDHCI_PRESENT_STATE     0x24
  65 #define  SDHCI_CMD_INHIBIT      0x00000001
  66 #define  SDHCI_DATA_INHIBIT     0x00000002
  67 #define  SDHCI_DOING_WRITE      0x00000100
  68 #define  SDHCI_DOING_READ       0x00000200
  69 #define  SDHCI_SPACE_AVAILABLE  0x00000400
  70 #define  SDHCI_DATA_AVAILABLE   0x00000800
  71 #define  SDHCI_CARD_PRESENT     0x00010000
  72 #define  SDHCI_WRITE_PROTECT    0x00080000
  73 #define  SDHCI_DATA_LVL_MASK    0x00F00000
  74 #define   SDHCI_DATA_LVL_SHIFT  20
  75 #define   SDHCI_DATA_0_LVL_MASK 0x00100000
  76
  77 #define SDHCI_HOST_CONTROL      0x28
  78 #define  SDHCI_CTRL_LED         0x01
  79 #define  SDHCI_CTRL_4BITBUS     0x02
  80 #define  SDHCI_CTRL_HISPD       0x04
  81 #define  SDHCI_CTRL_DMA_MASK    0x18
  82 #define   SDHCI_CTRL_SDMA       0x00
  83 #define   SDHCI_CTRL_ADMA1      0x08
  84 #define   SDHCI_CTRL_ADMA32     0x10
  85 #define   SDHCI_CTRL_ADMA64     0x18
  86 #define   SDHCI_CTRL_8BITBUS    0x20
  87
  88 #define SDHCI_POWER_CONTROL     0x29
  89 #define  SDHCI_POWER_ON         0x01
  90 #define  SDHCI_POWER_180        0x0A
  91 #define  SDHCI_POWER_300        0x0C
  92 #define  SDHCI_POWER_330        0x0E
  93
  94 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
  95
  96 #define SDHCI_WAKE_UP_CONTROL   0x2B
  97 #define  SDHCI_WAKE_ON_INT      0x01
  98 #define  SDHCI_WAKE_ON_INSERT   0x02
  99 #define  SDHCI_WAKE_ON_REMOVE   0x04
 100
 101 #define SDHCI_CLOCK_CONTROL     0x2C
 102 #define  SDHCI_DIVIDER_SHIFT    8
 103 #define  SDHCI_DIVIDER_HI_SHIFT 6
 104 #define  SDHCI_DIV_MASK 0xFF
 105 #define  SDHCI_DIV_MASK_LEN     8
 106 #define  SDHCI_DIV_HI_MASK      0x300
 107 #define  SDHCI_PROG_CLOCK_MODE  0x0020
 108 #define  SDHCI_CLOCK_CARD_EN    0x0004
 109 #define  SDHCI_CLOCK_INT_STABLE 0x0002
 110 #define  SDHCI_CLOCK_INT_EN     0x0001
 111
 112 #define SDHCI_TIMEOUT_CONTROL   0x2E
 113
 114 #define SDHCI_SOFTWARE_RESET    0x2F
 115 #define  SDHCI_RESET_ALL        0x01
 116 #define  SDHCI_RESET_CMD        0x02
 117 #define  SDHCI_RESET_DATA       0x04
 118
 119 #define SDHCI_INT_STATUS        0x30
 120 #define SDHCI_INT_ENABLE        0x34
 121 #define SDHCI_SIGNAL_ENABLE     0x38
 122 #define  SDHCI_INT_RESPONSE     0x00000001
 123 #define  SDHCI_INT_DATA_END     0x00000002
 124 #define  SDHCI_INT_BLK_GAP      0x00000004
 125 #define  SDHCI_INT_DMA_END      0x00000008
 126 #define  SDHCI_INT_SPACE_AVAIL  0x00000010
 127 #define  SDHCI_INT_DATA_AVAIL   0x00000020
 128 #define  SDHCI_INT_CARD_INSERT  0x00000040
 129 #define  SDHCI_INT_CARD_REMOVE  0x00000080
 130 #define  SDHCI_INT_CARD_INT     0x00000100
 131 #define  SDHCI_INT_RETUNE       0x00001000
 132 #define  SDHCI_INT_ERROR        0x00008000
 133 #define  SDHCI_INT_TIMEOUT      0x00010000
 134 #define  SDHCI_INT_CRC          0x00020000
 135 #define  SDHCI_INT_END_BIT      0x00040000
 136 #define  SDHCI_INT_INDEX        0x00080000
 137 #define  SDHCI_INT_DATA_TIMEOUT 0x00100000
 138 #define  SDHCI_INT_DATA_CRC     0x00200000
 139 #define  SDHCI_INT_DATA_END_BIT 0x00400000
 140 #define  SDHCI_INT_BUS_POWER    0x00800000
 141 #define  SDHCI_INT_ACMD12ERR    0x01000000
 142 #define  SDHCI_INT_ADMA_ERROR   0x02000000
 143
 144 #define  SDHCI_INT_NORMAL_MASK  0x00007FFF
 145 #define  SDHCI_INT_ERROR_MASK   0xFFFF8000
 146
 147 #define  SDHCI_INT_CMD_MASK     (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
 148                 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
 149 #define  SDHCI_INT_DATA_MASK    (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
 150                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
 151                 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
 152                 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \
 153                 SDHCI_INT_BLK_GAP)
 154 #define SDHCI_INT_ALL_MASK      ((unsigned int)-1)
 155
 156 #define SDHCI_ACMD12_ERR        0x3C
 157
 158 #define SDHCI_HOST_CONTROL2             0x3E
 159 #define  SDHCI_CTRL_UHS_MASK            0x0007
 160 #define   SDHCI_CTRL_UHS_SDR12          0x0000
 161 #define   SDHCI_CTRL_UHS_SDR25          0x0001
 162 #define   SDHCI_CTRL_UHS_SDR50          0x0002
 163 #define   SDHCI_CTRL_UHS_SDR104         0x0003
 164 #define   SDHCI_CTRL_UHS_DDR50          0x0004
 165 #define   SDHCI_CTRL_HS400              0x0005 /* Non-standard */
 166 #define  SDHCI_CTRL_VDD_180             0x0008
 167 #define  SDHCI_CTRL_DRV_TYPE_MASK       0x0030
 168 #define   SDHCI_CTRL_DRV_TYPE_B         0x0000
 169 #define   SDHCI_CTRL_DRV_TYPE_A         0x0010
 170 #define   SDHCI_CTRL_DRV_TYPE_C         0x0020
 171 #define   SDHCI_CTRL_DRV_TYPE_D         0x0030
 172 #define  SDHCI_CTRL_EXEC_TUNING         0x0040
 173 #define  SDHCI_CTRL_TUNED_CLK           0x0080
 174 #define  SDHCI_CTRL_PRESET_VAL_ENABLE   0x8000
 175
 176 #define SDHCI_CAPABILITIES      0x40
 177 #define  SDHCI_TIMEOUT_CLK_MASK 0x0000003F
 178 #define  SDHCI_TIMEOUT_CLK_SHIFT 0
 179 #define  SDHCI_TIMEOUT_CLK_UNIT 0x00000080
 180 #define  SDHCI_CLOCK_BASE_MASK  0x00003F00
 181 #define  SDHCI_CLOCK_V3_BASE_MASK       0x0000FF00
 182 #define  SDHCI_CLOCK_BASE_SHIFT 8
 183 #define  SDHCI_MAX_BLOCK_MASK   0x00030000
 184 #define  SDHCI_MAX_BLOCK_SHIFT  16
 185 #define  SDHCI_CAN_DO_8BIT      0x00040000
 186 #define  SDHCI_CAN_DO_ADMA2     0x00080000
 187 #define  SDHCI_CAN_DO_ADMA1     0x00100000
 188 #define  SDHCI_CAN_DO_HISPD     0x00200000
 189 #define  SDHCI_CAN_DO_SDMA      0x00400000
 190 #define  SDHCI_CAN_DO_SUSPEND   0x00800000
 191 #define  SDHCI_CAN_VDD_330      0x01000000
 192 #define  SDHCI_CAN_VDD_300      0x02000000
 193 #define  SDHCI_CAN_VDD_180      0x04000000
 194 #define  SDHCI_CAN_64BIT        0x10000000
 195
 196 #define  SDHCI_SUPPORT_SDR50    0x00000001
 197 #define  SDHCI_SUPPORT_SDR104   0x00000002
 198 #define  SDHCI_SUPPORT_DDR50    0x00000004
 199 #define  SDHCI_DRIVER_TYPE_A    0x00000010
 200 #define  SDHCI_DRIVER_TYPE_C    0x00000020
 201 #define  SDHCI_DRIVER_TYPE_D    0x00000040
 202 #define  SDHCI_RETUNING_TIMER_COUNT_MASK        0x00000F00
 203 #define  SDHCI_RETUNING_TIMER_COUNT_SHIFT       8
 204 #define  SDHCI_USE_SDR50_TUNING                 0x00002000
 205 #define  SDHCI_RETUNING_MODE_MASK               0x0000C000
 206 #define  SDHCI_RETUNING_MODE_SHIFT              14
 207 #define  SDHCI_CLOCK_MUL_MASK   0x00FF0000
 208 #define  SDHCI_CLOCK_MUL_SHIFT  16
 209 #define  SDHCI_SUPPORT_HS400    0x80000000 /* Non-standard */
 210
 211 #define SDHCI_CAPABILITIES_1    0x44
 212
 213 #define SDHCI_MAX_CURRENT               0x48
 214 #define  SDHCI_MAX_CURRENT_LIMIT        0xFF
 215 #define  SDHCI_MAX_CURRENT_330_MASK     0x0000FF
 216 #define  SDHCI_MAX_CURRENT_330_SHIFT    0
 217 #define  SDHCI_MAX_CURRENT_300_MASK     0x00FF00
 218 #define  SDHCI_MAX_CURRENT_300_SHIFT    8
 219 #define  SDHCI_MAX_CURRENT_180_MASK     0xFF0000
 220 #define  SDHCI_MAX_CURRENT_180_SHIFT    16
 221 #define   SDHCI_MAX_CURRENT_MULTIPLIER  4
 222
 223 /* 4C-4F reserved for more max current */
 224
 225 #define SDHCI_SET_ACMD12_ERROR  0x50
 226 #define SDHCI_SET_INT_ERROR     0x52
 227
 228 #define SDHCI_ADMA_ERROR        0x54
 229
 230 /* 55-57 reserved */
 231
 232 #define SDHCI_ADMA_ADDRESS      0x58
 233 #define SDHCI_ADMA_ADDRESS_HI   0x5C
 234
 235 /* 60-FB reserved */
 236
 237 #define SDHCI_PRESET_FOR_SDR12 0x66
 238 #define SDHCI_PRESET_FOR_SDR25 0x68
 239 #define SDHCI_PRESET_FOR_SDR50 0x6A
 240 #define SDHCI_PRESET_FOR_SDR104        0x6C
 241 #define SDHCI_PRESET_FOR_DDR50 0x6E
 242 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
 243 #define SDHCI_PRESET_DRV_MASK  0xC000
 244 #define SDHCI_PRESET_DRV_SHIFT  14
 245 #define SDHCI_PRESET_CLKGEN_SEL_MASK   0x400
 246 #define SDHCI_PRESET_CLKGEN_SEL_SHIFT   10
 247 #define SDHCI_PRESET_SDCLK_FREQ_MASK   0x3FF
 248 #define SDHCI_PRESET_SDCLK_FREQ_SHIFT   0
 249
 250 #define SDHCI_SLOT_INT_STATUS   0xFC
 251
 252 #define SDHCI_HOST_VERSION      0xFE
 253 #define  SDHCI_VENDOR_VER_MASK  0xFF00
 254 #define  SDHCI_VENDOR_VER_SHIFT 8
 255 #define  SDHCI_SPEC_VER_MASK    0x00FF
 256 #define  SDHCI_SPEC_VER_SHIFT   0
 257 #define   SDHCI_SPEC_100        0
 258 #define   SDHCI_SPEC_200        1
 259 #define   SDHCI_SPEC_300        2
 260
 261 /*
 262  * End of controller registers.
 263  */
 264
 265 #define SDHCI_MAX_DIV_SPEC_200  256
 266 #define SDHCI_MAX_DIV_SPEC_300  2046
 267
 268 /*
 269  * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
 270  */
 271 #define SDHCI_DEFAULT_BOUNDARY_SIZE  (512 * 1024)
 272 #define SDHCI_DEFAULT_BOUNDARY_ARG   (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
 273
 274 /* ADMA2 32-bit DMA descriptor size */
 275 #define SDHCI_ADMA2_32_DESC_SZ  8
 276
 277 /* ADMA2 32-bit descriptor */
 278 struct sdhci_adma2_32_desc {
 279         __le16  cmd;
 280         __le16  len;
 281         __le32  addr;
 282 }  __packed __aligned(4);
 283
 284 /* ADMA2 data alignment */
 285 #define SDHCI_ADMA2_ALIGN       4
 286 #define SDHCI_ADMA2_MASK        (SDHCI_ADMA2_ALIGN - 1)
 287
 288 /*
 289  * ADMA2 descriptor alignment.  Some controllers (e.g. Intel) require 8 byte
 290  * alignment for the descriptor table even in 32-bit DMA mode.  Memory
 291  * allocation is at least 8 byte aligned anyway, so just stipulate 8 always.
 292  */
 293 #define SDHCI_ADMA2_DESC_ALIGN  8
 294
 295 /* ADMA2 64-bit DMA descriptor size */
 296 #define SDHCI_ADMA2_64_DESC_SZ  12
 297
 298 /*
 299  * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
 300  * aligned.
 301  */
 302 struct sdhci_adma2_64_desc {
 303         __le16  cmd;
 304         __le16  len;
 305         __le32  addr_lo;
 306         __le32  addr_hi;
 307 }  __packed __aligned(4);
 308
 309 #define ADMA2_TRAN_VALID        0x21
 310 #define ADMA2_NOP_END_VALID     0x3
 311 #define ADMA2_END               0x2
 312
 313 /*
 314  * Maximum segments assuming a 512KiB maximum requisition size and a minimum
 315  * 4KiB page size.
 316  */
 317 #define SDHCI_MAX_SEGS          128
 318
 319 /* Allow for a a command request and a data request at the same time */
 320 #define SDHCI_MAX_MRQS          2
 321
 322 enum sdhci_cookie {
 323         COOKIE_UNMAPPED,
 324         COOKIE_PRE_MAPPED,      /* mapped by sdhci_pre_req() */
 325         COOKIE_MAPPED,          /* mapped by sdhci_prepare_data() */
 326 };
 327
 328 struct sdhci_host {
 329         /* Data set by hardware interface driver */
 330         const char *hw_name;    /* Hardware bus name */
 331
 332         unsigned int quirks;    /* Deviations from spec. */
 333
 334 /* Controller doesn't honor resets unless we touch the clock register */
 335 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET                  (1<<0)
 336 /* Controller has bad caps bits, but really supports DMA */
 337 #define SDHCI_QUIRK_FORCE_DMA                           (1<<1)
 338 /* Controller doesn't like to be reset when there is no card inserted. */
 339 #define SDHCI_QUIRK_NO_CARD_NO_RESET                    (1<<2)
 340 /* Controller doesn't like clearing the power reg before a change */
 341 #define SDHCI_QUIRK_SINGLE_POWER_WRITE                  (1<<3)
 342 /* Controller has flaky internal state so reset it on each ios change */
 343 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS               (1<<4)
 344 /* Controller has an unusable DMA engine */
 345 #define SDHCI_QUIRK_BROKEN_DMA                          (1<<5)
 346 /* Controller has an unusable ADMA engine */
 347 #define SDHCI_QUIRK_BROKEN_ADMA                         (1<<6)
 348 /* Controller can only DMA from 32-bit aligned addresses */
 349 #define SDHCI_QUIRK_32BIT_DMA_ADDR                      (1<<7)
 350 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
 351 #define SDHCI_QUIRK_32BIT_DMA_SIZE                      (1<<8)
 352 /* Controller can only ADMA chunks that are a multiple of 32 bits */
 353 #define SDHCI_QUIRK_32BIT_ADMA_SIZE                     (1<<9)
 354 /* Controller needs to be reset after each request to stay stable */
 355 #define SDHCI_QUIRK_RESET_AFTER_REQUEST                 (1<<10)
 356 /* Controller needs voltage and power writes to happen separately */
 357 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER             (1<<11)
 358 /* Controller provides an incorrect timeout value for transfers */
 359 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL                  (1<<12)
 360 /* Controller has an issue with buffer bits for small transfers */
 361 #define SDHCI_QUIRK_BROKEN_SMALL_PIO                    (1<<13)
 362 /* Controller does not provide transfer-complete interrupt when not busy */
 363 #define SDHCI_QUIRK_NO_BUSY_IRQ                         (1<<14)
 364 /* Controller has unreliable card detection */
 365 #define SDHCI_QUIRK_BROKEN_CARD_DETECTION               (1<<15)
 366 /* Controller reports inverted write-protect state */
 367 #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT              (1<<16)
 368 /* Controller does not like fast PIO transfers */
 369 #define SDHCI_QUIRK_PIO_NEEDS_DELAY                     (1<<18)
 370 /* Controller has to be forced to use block size of 2048 bytes */
 371 #define SDHCI_QUIRK_FORCE_BLK_SZ_2048                   (1<<20)
 372 /* Controller cannot do multi-block transfers */
 373 #define SDHCI_QUIRK_NO_MULTIBLOCK                       (1<<21)
 374 /* Controller can only handle 1-bit data transfers */
 375 #define SDHCI_QUIRK_FORCE_1_BIT_DATA                    (1<<22)
 376 /* Controller needs 10ms delay between applying power and clock */
 377 #define SDHCI_QUIRK_DELAY_AFTER_POWER                   (1<<23)
 378 /* Controller uses SDCLK instead of TMCLK for data timeouts */
 379 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK             (1<<24)
 380 /* Controller reports wrong base clock capability */
 381 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN               (1<<25)
 382 /* Controller cannot support End Attribute in NOP ADMA descriptor */
 383 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC               (1<<26)
 384 /* Controller is missing device caps. Use caps provided by host */
 385 #define SDHCI_QUIRK_MISSING_CAPS                        (1<<27)
 386 /* Controller uses Auto CMD12 command to stop the transfer */
 387 #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12              (1<<28)
 388 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
 389 #define SDHCI_QUIRK_NO_HISPD_BIT                        (1<<29)
 390 /* Controller treats ADMA descriptors with length 0000h incorrectly */
 391 #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC            (1<<30)
 392 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
 393 #define SDHCI_QUIRK_UNSTABLE_RO_DETECT                  (1<<31)
 394
 395         unsigned int quirks2;   /* More deviations from spec. */
 396
 397 #define SDHCI_QUIRK2_HOST_OFF_CARD_ON                   (1<<0)
 398 #define SDHCI_QUIRK2_HOST_NO_CMD23                      (1<<1)
 399 /* The system physically doesn't support 1.8v, even if the host does */
 400 #define SDHCI_QUIRK2_NO_1_8_V                           (1<<2)
 401 #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN                (1<<3)
 402 #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON               (1<<4)
 403 /* Controller has a non-standard host control register */
 404 #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL                (1<<5)
 405 /* Controller does not support HS200 */
 406 #define SDHCI_QUIRK2_BROKEN_HS200                       (1<<6)
 407 /* Controller does not support DDR50 */
 408 #define SDHCI_QUIRK2_BROKEN_DDR50                       (1<<7)
 409 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
 410 #define SDHCI_QUIRK2_STOP_WITH_TC                       (1<<8)
 411 /* Controller does not support 64-bit DMA */
 412 #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA                  (1<<9)
 413 /* need clear transfer mode register before send cmd */
 414 #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD  (1<<10)
 415 /* Capability register bit-63 indicates HS400 support */
 416 #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400               (1<<11)
 417 /* forced tuned clock */
 418 #define SDHCI_QUIRK2_TUNING_WORK_AROUND                 (1<<12)
 419 /* disable the block count for single block transactions */
 420 #define SDHCI_QUIRK2_SUPPORT_SINGLE                     (1<<13)
 421 /* Controller broken with using ACMD23 */
 422 #define SDHCI_QUIRK2_ACMD23_BROKEN                      (1<<14)
 423 /* Broken Clock divider zero in controller */
 424 #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN              (1<<15)
 425
 426         int irq;                /* Device IRQ */
 427         void __iomem *ioaddr;   /* Mapped address */
 428
 429         const struct sdhci_ops *ops;    /* Low level hw interface */
 430
 431         /* Internal data */
 432         struct mmc_host *mmc;   /* MMC structure */
 433         struct mmc_host_ops mmc_host_ops;       /* MMC host ops */
 434         u64 dma_mask;           /* custom DMA mask */
 435
 436 #if IS_ENABLED(CONFIG_LEDS_CLASS)
 437         struct led_classdev led;        /* LED control */
 438         char led_name[32];
 439 #endif
 440
 441         spinlock_t lock;        /* Mutex */
 442
 443         int flags;              /* Host attributes */
 444 #define SDHCI_USE_SDMA          (1<<0)  /* Host is SDMA capable */
 445 #define SDHCI_USE_ADMA          (1<<1)  /* Host is ADMA capable */
 446 #define SDHCI_REQ_USE_DMA       (1<<2)  /* Use DMA for this req. */
 447 #define SDHCI_DEVICE_DEAD       (1<<3)  /* Device unresponsive */
 448 #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */
 449 #define SDHCI_AUTO_CMD12        (1<<6)  /* Auto CMD12 support */
 450 #define SDHCI_AUTO_CMD23        (1<<7)  /* Auto CMD23 support */
 451 #define SDHCI_PV_ENABLED        (1<<8)  /* Preset value enabled */
 452 #define SDHCI_SDIO_IRQ_ENABLED  (1<<9)  /* SDIO irq enabled */
 453 #define SDHCI_USE_64_BIT_DMA    (1<<12) /* Use 64-bit DMA */
 454 #define SDHCI_HS400_TUNING      (1<<13) /* Tuning for HS400 */
 455 #define SDHCI_SIGNALING_330     (1<<14) /* Host is capable of 3.3V signaling */
 456 #define SDHCI_SIGNALING_180     (1<<15) /* Host is capable of 1.8V signaling */
 457 #define SDHCI_SIGNALING_120     (1<<16) /* Host is capable of 1.2V signaling */
 458
 459         unsigned int version;   /* SDHCI spec. version */
 460
 461         unsigned int max_clk;   /* Max possible freq (MHz) */
 462         unsigned int timeout_clk;       /* Timeout freq (KHz) */
 463         unsigned int clk_mul;   /* Clock Muliplier value */
 464
 465         unsigned int clock;     /* Current clock (MHz) */
 466         u8 pwr;                 /* Current voltage */
 467
 468         bool runtime_suspended; /* Host is runtime suspended */
 469         bool bus_on;            /* Bus power prevents runtime suspend */
 470         bool preset_enabled;    /* Preset is enabled */
 471         bool pending_reset;     /* Cmd/data reset is pending */
 472
 473         struct mmc_request *mrqs_done[SDHCI_MAX_MRQS];  /* Requests done */
 474         struct mmc_command *cmd;        /* Current command */
 475         struct mmc_command *data_cmd;   /* Current data command */
 476         struct mmc_data *data;  /* Current data request */
 477         unsigned int data_early:1;      /* Data finished before cmd */
 478
 479         struct sg_mapping_iter sg_miter;        /* SG state for PIO */
 480         unsigned int blocks;    /* remaining PIO blocks */
 481
 482         int sg_count;           /* Mapped sg entries */
 483
 484         void *adma_table;       /* ADMA descriptor table */
 485         void *align_buffer;     /* Bounce buffer */
 486
 487         size_t adma_table_sz;   /* ADMA descriptor table size */
 488         size_t align_buffer_sz; /* Bounce buffer size */
 489
 490         dma_addr_t adma_addr;   /* Mapped ADMA descr. table */
 491         dma_addr_t align_addr;  /* Mapped bounce buffer */
 492
 493         unsigned int desc_sz;   /* ADMA descriptor size */
 494
 495         struct tasklet_struct finish_tasklet;   /* Tasklet structures */
 496
 497         struct timer_list timer;        /* Timer for timeouts */
 498         struct timer_list data_timer;   /* Timer for data timeouts */
 499
 500         u32 caps;               /* CAPABILITY_0 */
 501         u32 caps1;              /* CAPABILITY_1 */
 502         bool read_caps;         /* Capability flags have been read */
 503
 504         unsigned int            ocr_avail_sdio; /* OCR bit masks */
 505         unsigned int            ocr_avail_sd;
 506         unsigned int            ocr_avail_mmc;
 507         u32 ocr_mask;           /* available voltages */
 508
 509         unsigned                timing;         /* Current timing */
 510
 511         u32                     thread_isr;
 512
 513         /* cached registers */
 514         u32                     ier;
 515
 516         wait_queue_head_t       buf_ready_int;  /* Waitqueue for Buffer Read Ready interrupt */
 517         unsigned int            tuning_done;    /* Condition flag set when CMD19 succeeds */
 518
 519         unsigned int            tuning_count;   /* Timer count for re-tuning */
 520         unsigned int            tuning_mode;    /* Re-tuning mode supported by host */
 521 #define SDHCI_TUNING_MODE_1     0
 522 #define SDHCI_TUNING_MODE_2     1
 523 #define SDHCI_TUNING_MODE_3     2
 524
 525         unsigned long private[0] ____cacheline_aligned;
 526 };
 527
 528 struct sdhci_ops {
 529 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 530         u32             (*read_l)(struct sdhci_host *host, int reg);
 531         u16             (*read_w)(struct sdhci_host *host, int reg);
 532         u8              (*read_b)(struct sdhci_host *host, int reg);
 533         void            (*write_l)(struct sdhci_host *host, u32 val, int reg);
 534         void            (*write_w)(struct sdhci_host *host, u16 val, int reg);
 535         void            (*write_b)(struct sdhci_host *host, u8 val, int reg);
 536 #endif
 537
 538         void    (*set_clock)(struct sdhci_host *host, unsigned int clock);
 539         void    (*set_power)(struct sdhci_host *host, unsigned char mode,
 540                              unsigned short vdd);
 541
 542         int             (*enable_dma)(struct sdhci_host *host);
 543         unsigned int    (*get_max_clock)(struct sdhci_host *host);
 544         unsigned int    (*get_min_clock)(struct sdhci_host *host);
 545         unsigned int    (*get_timeout_clock)(struct sdhci_host *host);
 546         unsigned int    (*get_max_timeout_count)(struct sdhci_host *host);
 547         void            (*set_timeout)(struct sdhci_host *host,
 548                                        struct mmc_command *cmd);
 549         void            (*set_bus_width)(struct sdhci_host *host, int width);
 550         void (*platform_send_init_74_clocks)(struct sdhci_host *host,
 551                                              u8 power_mode);
 552         unsigned int    (*get_ro)(struct sdhci_host *host);
 553         void            (*reset)(struct sdhci_host *host, u8 mask);
 554         int     (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
 555         void    (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
 556         void    (*hw_reset)(struct sdhci_host *host);
 557         void    (*adma_workaround)(struct sdhci_host *host, u32 intmask);
 558         void    (*platform_init)(struct sdhci_host *host);
 559         void    (*card_event)(struct sdhci_host *host);
 560         void    (*voltage_switch)(struct sdhci_host *host);
 561         int     (*select_drive_strength)(struct sdhci_host *host,
 562                                          struct mmc_card *card,
 563                                          unsigned int max_dtr, int host_drv,
 564                                          int card_drv, int *drv_type);
 565 };
 566
 567 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 568
 569 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 570 {
 571         if (unlikely(host->ops->write_l))
 572                 host->ops->write_l(host, val, reg);
 573         else
 574                 writel(val, host->ioaddr + reg);
 575 }
 576
 577 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 578 {
 579         if (unlikely(host->ops->write_w))
 580                 host->ops->write_w(host, val, reg);
 581         else
 582                 writew(val, host->ioaddr + reg);
 583 }
 584
 585 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 586 {
 587         if (unlikely(host->ops->write_b))
 588                 host->ops->write_b(host, val, reg);
 589         else
 590                 writeb(val, host->ioaddr + reg);
 591 }
 592
 593 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
 594 {
 595         if (unlikely(host->ops->read_l))
 596                 return host->ops->read_l(host, reg);
 597         else
 598                 return readl(host->ioaddr + reg);
 599 }
 600
 601 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
 602 {
 603         if (unlikely(host->ops->read_w))
 604                 return host->ops->read_w(host, reg);
 605         else
 606                 return readw(host->ioaddr + reg);
 607 }
 608
 609 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
 610 {
 611         if (unlikely(host->ops->read_b))
 612                 return host->ops->read_b(host, reg);
 613         else
 614                 return readb(host->ioaddr + reg);
 615 }
 616
 617 #else
 618
 619 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 620 {
 621         writel(val, host->ioaddr + reg);
 622 }
 623
 624 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 625 {
 626         writew(val, host->ioaddr + reg);
 627 }
 628
 629 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 630 {
 631         writeb(val, host->ioaddr + reg);
 632 }
 633
 634 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
 635 {
 636         return readl(host->ioaddr + reg);
 637 }
 638
 639 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
 640 {
 641         return readw(host->ioaddr + reg);
 642 }
 643
 644 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
 645 {
 646         return readb(host->ioaddr + reg);
 647 }
 648
 649 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
 650
 651 extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
 652         size_t priv_size);
 653 extern void sdhci_free_host(struct sdhci_host *host);
 654
 655 static inline void *sdhci_priv(struct sdhci_host *host)
 656 {
 657         return (void *)host->private;
 658 }
 659
 660 extern void sdhci_card_detect(struct sdhci_host *host);
 661 extern void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps,
 662                               u32 *caps1);
 663 extern int sdhci_setup_host(struct sdhci_host *host);
 664 extern int __sdhci_add_host(struct sdhci_host *host);
 665 extern int sdhci_add_host(struct sdhci_host *host);
 666 extern void sdhci_remove_host(struct sdhci_host *host, int dead);
 667 extern void sdhci_send_command(struct sdhci_host *host,
 668                                 struct mmc_command *cmd);
 669
 670 static inline void sdhci_read_caps(struct sdhci_host *host)
 671 {
 672         __sdhci_read_caps(host, NULL, NULL, NULL);
 673 }
 674
 675 static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host)
 676 {
 677         return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED);
 678 }
 679
 680 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
 681                    unsigned int *actual_clock);
 682 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
 683 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
 684                      unsigned short vdd);
 685 void sdhci_set_bus_width(struct sdhci_host *host, int width);
 686 void sdhci_reset(struct sdhci_host *host, u8 mask);
 687 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
 688
 689 #ifdef CONFIG_PM
 690 extern int sdhci_suspend_host(struct sdhci_host *host);
 691 extern int sdhci_resume_host(struct sdhci_host *host);
 692 extern void sdhci_enable_irq_wakeups(struct sdhci_host *host);
 693 extern int sdhci_runtime_suspend_host(struct sdhci_host *host);
 694 extern int sdhci_runtime_resume_host(struct sdhci_host *host);
 695 #endif
 696
 697 #endif /* __SDHCI_HW_H */