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ASoC: arizona: Correct handling of FLL theta in synchroniser mode
[linux/fpc-iii.git] / drivers / mmc / host / sunxi-mmc.c
blob2ee4c21ec55eec871c13aadaaad5bb5f9903a581
1 /*
2 * Driver for sunxi SD/MMC host controllers
3 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
4 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
5 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
6 * (C) Copyright 2013-2014 David Lanzend�rfer <david.lanzendoerfer@o2s.ch>
7 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/io.h>
18 #include <linux/device.h>
19 #include <linux/interrupt.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22
23 #include <linux/clk.h>
24 #include <linux/gpio.h>
25 #include <linux/platform_device.h>
26 #include <linux/spinlock.h>
27 #include <linux/scatterlist.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/slab.h>
30 #include <linux/reset.h>
31 #include <linux/regulator/consumer.h>
32
33 #include <linux/of_address.h>
34 #include <linux/of_gpio.h>
35 #include <linux/of_platform.h>
36
37 #include <linux/mmc/host.h>
38 #include <linux/mmc/sd.h>
39 #include <linux/mmc/sdio.h>
40 #include <linux/mmc/mmc.h>
41 #include <linux/mmc/core.h>
42 #include <linux/mmc/card.h>
43 #include <linux/mmc/slot-gpio.h>
44
45 /* register offset definitions */
46 #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
47 #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
48 #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
49 #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
50 #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
51 #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
52 #define SDXC_REG_CMDR (0x18) /* SMC Command Register */
53 #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
54 #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
55 #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
56 #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
57 #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
58 #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
59 #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
60 #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
61 #define SDXC_REG_STAS (0x3C) /* SMC Status Register */
62 #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
63 #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
64 #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
65 #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
66 #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
67 #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
68 #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
69 #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
70 #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
71 #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
72 #define SDXC_REG_CHDA (0x90)
73 #define SDXC_REG_CBDA (0x94)
74
75 #define mmc_readl(host, reg) \
76 readl((host)->reg_base + SDXC_##reg)
77 #define mmc_writel(host, reg, value) \
78 writel((value), (host)->reg_base + SDXC_##reg)
79
80 /* global control register bits */
81 #define SDXC_SOFT_RESET BIT(0)
82 #define SDXC_FIFO_RESET BIT(1)
83 #define SDXC_DMA_RESET BIT(2)
84 #define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
85 #define SDXC_DMA_ENABLE_BIT BIT(5)
86 #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
87 #define SDXC_POSEDGE_LATCH_DATA BIT(9)
88 #define SDXC_DDR_MODE BIT(10)
89 #define SDXC_MEMORY_ACCESS_DONE BIT(29)
90 #define SDXC_ACCESS_DONE_DIRECT BIT(30)
91 #define SDXC_ACCESS_BY_AHB BIT(31)
92 #define SDXC_ACCESS_BY_DMA (0 << 31)
93 #define SDXC_HARDWARE_RESET \
94 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
95
96 /* clock control bits */
97 #define SDXC_CARD_CLOCK_ON BIT(16)
98 #define SDXC_LOW_POWER_ON BIT(17)
99
100 /* bus width */
101 #define SDXC_WIDTH1 0
102 #define SDXC_WIDTH4 1
103 #define SDXC_WIDTH8 2
104
105 /* smc command bits */
106 #define SDXC_RESP_EXPIRE BIT(6)
107 #define SDXC_LONG_RESPONSE BIT(7)
108 #define SDXC_CHECK_RESPONSE_CRC BIT(8)
109 #define SDXC_DATA_EXPIRE BIT(9)
110 #define SDXC_WRITE BIT(10)
111 #define SDXC_SEQUENCE_MODE BIT(11)
112 #define SDXC_SEND_AUTO_STOP BIT(12)
113 #define SDXC_WAIT_PRE_OVER BIT(13)
114 #define SDXC_STOP_ABORT_CMD BIT(14)
115 #define SDXC_SEND_INIT_SEQUENCE BIT(15)
116 #define SDXC_UPCLK_ONLY BIT(21)
117 #define SDXC_READ_CEATA_DEV BIT(22)
118 #define SDXC_CCS_EXPIRE BIT(23)
119 #define SDXC_ENABLE_BIT_BOOT BIT(24)
120 #define SDXC_ALT_BOOT_OPTIONS BIT(25)
121 #define SDXC_BOOT_ACK_EXPIRE BIT(26)
122 #define SDXC_BOOT_ABORT BIT(27)
123 #define SDXC_VOLTAGE_SWITCH BIT(28)
124 #define SDXC_USE_HOLD_REGISTER BIT(29)
125 #define SDXC_START BIT(31)
126
127 /* interrupt bits */
128 #define SDXC_RESP_ERROR BIT(1)
129 #define SDXC_COMMAND_DONE BIT(2)
130 #define SDXC_DATA_OVER BIT(3)
131 #define SDXC_TX_DATA_REQUEST BIT(4)
132 #define SDXC_RX_DATA_REQUEST BIT(5)
133 #define SDXC_RESP_CRC_ERROR BIT(6)
134 #define SDXC_DATA_CRC_ERROR BIT(7)
135 #define SDXC_RESP_TIMEOUT BIT(8)
136 #define SDXC_DATA_TIMEOUT BIT(9)
137 #define SDXC_VOLTAGE_CHANGE_DONE BIT(10)
138 #define SDXC_FIFO_RUN_ERROR BIT(11)
139 #define SDXC_HARD_WARE_LOCKED BIT(12)
140 #define SDXC_START_BIT_ERROR BIT(13)
141 #define SDXC_AUTO_COMMAND_DONE BIT(14)
142 #define SDXC_END_BIT_ERROR BIT(15)
143 #define SDXC_SDIO_INTERRUPT BIT(16)
144 #define SDXC_CARD_INSERT BIT(30)
145 #define SDXC_CARD_REMOVE BIT(31)
146 #define SDXC_INTERRUPT_ERROR_BIT \
147 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
148 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
149 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
150 #define SDXC_INTERRUPT_DONE_BIT \
151 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
152 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
153
154 /* status */
155 #define SDXC_RXWL_FLAG BIT(0)
156 #define SDXC_TXWL_FLAG BIT(1)
157 #define SDXC_FIFO_EMPTY BIT(2)
158 #define SDXC_FIFO_FULL BIT(3)
159 #define SDXC_CARD_PRESENT BIT(8)
160 #define SDXC_CARD_DATA_BUSY BIT(9)
161 #define SDXC_DATA_FSM_BUSY BIT(10)
162 #define SDXC_DMA_REQUEST BIT(31)
163 #define SDXC_FIFO_SIZE 16
164
165 /* Function select */
166 #define SDXC_CEATA_ON (0xceaa << 16)
167 #define SDXC_SEND_IRQ_RESPONSE BIT(0)
168 #define SDXC_SDIO_READ_WAIT BIT(1)
169 #define SDXC_ABORT_READ_DATA BIT(2)
170 #define SDXC_SEND_CCSD BIT(8)
171 #define SDXC_SEND_AUTO_STOPCCSD BIT(9)
172 #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10)
173
174 /* IDMA controller bus mod bit field */
175 #define SDXC_IDMAC_SOFT_RESET BIT(0)
176 #define SDXC_IDMAC_FIX_BURST BIT(1)
177 #define SDXC_IDMAC_IDMA_ON BIT(7)
178 #define SDXC_IDMAC_REFETCH_DES BIT(31)
179
180 /* IDMA status bit field */
181 #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)
182 #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)
183 #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)
184 #define SDXC_IDMAC_DESTINATION_INVALID BIT(4)
185 #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)
186 #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)
187 #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)
188 #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10)
189 #define SDXC_IDMAC_IDLE (0 << 13)
190 #define SDXC_IDMAC_SUSPEND (1 << 13)
191 #define SDXC_IDMAC_DESC_READ (2 << 13)
192 #define SDXC_IDMAC_DESC_CHECK (3 << 13)
193 #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13)
194 #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13)
195 #define SDXC_IDMAC_READ (6 << 13)
196 #define SDXC_IDMAC_WRITE (7 << 13)
197 #define SDXC_IDMAC_DESC_CLOSE (8 << 13)
198
199 /*
200 * If the idma-des-size-bits of property is ie 13, bufsize bits are:
201 * Bits 0-12: buf1 size
202 * Bits 13-25: buf2 size
203 * Bits 26-31: not used
204 * Since we only ever set buf1 size, we can simply store it directly.
205 */
206 #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
207 #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */
208 #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */
209 #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */
210 #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */
211 #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
212 #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
213
214 #define SDXC_CLK_400K 0
215 #define SDXC_CLK_25M 1
216 #define SDXC_CLK_50M 2
217 #define SDXC_CLK_50M_DDR 3
218 #define SDXC_CLK_50M_DDR_8BIT 4
219
220 struct sunxi_mmc_clk_delay {
221 u32 output;
222 u32 sample;
223 };
224
225 struct sunxi_idma_des {
226 u32 config;
227 u32 buf_size;
228 u32 buf_addr_ptr1;
229 u32 buf_addr_ptr2;
230 };
231
232 struct sunxi_mmc_host {
233 struct mmc_host *mmc;
234 struct reset_control *reset;
235
236 /* IO mapping base */
237 void __iomem *reg_base;
238
239 /* clock management */
240 struct clk *clk_ahb;
241 struct clk *clk_mmc;
242 struct clk *clk_sample;
243 struct clk *clk_output;
244 const struct sunxi_mmc_clk_delay *clk_delays;
245
246 /* irq */
247 spinlock_t lock;
248 int irq;
249 u32 int_sum;
250 u32 sdio_imask;
251
252 /* dma */
253 u32 idma_des_size_bits;
254 dma_addr_t sg_dma;
255 void *sg_cpu;
256 bool wait_dma;
257
258 struct mmc_request *mrq;
259 struct mmc_request *manual_stop_mrq;
260 int ferror;
261
262 /* vqmmc */
263 bool vqmmc_enabled;
264 };
265
266 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
267 {
268 unsigned long expire = jiffies + msecs_to_jiffies(250);
269 u32 rval;
270
271 mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET);
272 do {
273 rval = mmc_readl(host, REG_GCTRL);
274 } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));
275
276 if (rval & SDXC_HARDWARE_RESET) {
277 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");
278 return -EIO;
279 }
280
281 return 0;
282 }
283
284 static int sunxi_mmc_init_host(struct mmc_host *mmc)
285 {
286 u32 rval;
287 struct sunxi_mmc_host *host = mmc_priv(mmc);
288
289 if (sunxi_mmc_reset_host(host))
290 return -EIO;
291
292 /*
293 * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
294 *
295 * TODO: sun9i has a larger FIFO and supports higher trigger values
296 */
297 mmc_writel(host, REG_FTRGL, 0x20070008);
298 /* Maximum timeout value */
299 mmc_writel(host, REG_TMOUT, 0xffffffff);
300 /* Unmask SDIO interrupt if needed */
301 mmc_writel(host, REG_IMASK, host->sdio_imask);
302 /* Clear all pending interrupts */
303 mmc_writel(host, REG_RINTR, 0xffffffff);
304 /* Debug register? undocumented */
305 mmc_writel(host, REG_DBGC, 0xdeb);
306 /* Enable CEATA support */
307 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
308 /* Set DMA descriptor list base address */
309 mmc_writel(host, REG_DLBA, host->sg_dma);
310
311 rval = mmc_readl(host, REG_GCTRL);
312 rval |= SDXC_INTERRUPT_ENABLE_BIT;
313 /* Undocumented, but found in Allwinner code */
314 rval &= ~SDXC_ACCESS_DONE_DIRECT;
315 mmc_writel(host, REG_GCTRL, rval);
316
317 return 0;
318 }
319
320 static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
321 struct mmc_data *data)
322 {
323 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
324 dma_addr_t next_desc = host->sg_dma;
325 int i, max_len = (1 << host->idma_des_size_bits);
326
327 for (i = 0; i < data->sg_len; i++) {
328 pdes[i].config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN |
329 SDXC_IDMAC_DES0_DIC;
330
331 if (data->sg[i].length == max_len)
332 pdes[i].buf_size = 0; /* 0 == max_len */
333 else
334 pdes[i].buf_size = data->sg[i].length;
335
336 next_desc += sizeof(struct sunxi_idma_des);
337 pdes[i].buf_addr_ptr1 = sg_dma_address(&data->sg[i]);
338 pdes[i].buf_addr_ptr2 = (u32)next_desc;
339 }
340
341 pdes[0].config |= SDXC_IDMAC_DES0_FD;
342 pdes[i - 1].config |= SDXC_IDMAC_DES0_LD | SDXC_IDMAC_DES0_ER;
343 pdes[i - 1].config &= ~SDXC_IDMAC_DES0_DIC;
344 pdes[i - 1].buf_addr_ptr2 = 0;
345
346 /*
347 * Avoid the io-store starting the idmac hitting io-mem before the
348 * descriptors hit the main-mem.
349 */
350 wmb();
351 }
352
353 static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data)
354 {
355 if (data->flags & MMC_DATA_WRITE)
356 return DMA_TO_DEVICE;
357 else
358 return DMA_FROM_DEVICE;
359 }
360
361 static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,
362 struct mmc_data *data)
363 {
364 u32 i, dma_len;
365 struct scatterlist *sg;
366
367 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
368 sunxi_mmc_get_dma_dir(data));
369 if (dma_len == 0) {
370 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
371 return -ENOMEM;
372 }
373
374 for_each_sg(data->sg, sg, data->sg_len, i) {
375 if (sg->offset & 3 || sg->length & 3) {
376 dev_err(mmc_dev(host->mmc),
377 "unaligned scatterlist: os %x length %d\n",
378 sg->offset, sg->length);
379 return -EINVAL;
380 }
381 }
382
383 return 0;
384 }
385
386 static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,
387 struct mmc_data *data)
388 {
389 u32 rval;
390
391 sunxi_mmc_init_idma_des(host, data);
392
393 rval = mmc_readl(host, REG_GCTRL);
394 rval |= SDXC_DMA_ENABLE_BIT;
395 mmc_writel(host, REG_GCTRL, rval);
396 rval |= SDXC_DMA_RESET;
397 mmc_writel(host, REG_GCTRL, rval);
398
399 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
400
401 if (!(data->flags & MMC_DATA_WRITE))
402 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
403
404 mmc_writel(host, REG_DMAC,
405 SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
406 }
407
408 static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
409 struct mmc_request *req)
410 {
411 u32 arg, cmd_val, ri;
412 unsigned long expire = jiffies + msecs_to_jiffies(1000);
413
414 cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
415 SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;
416
417 if (req->cmd->opcode == SD_IO_RW_EXTENDED) {
418 cmd_val |= SD_IO_RW_DIRECT;
419 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
420 ((req->cmd->arg >> 28) & 0x7);
421 } else {
422 cmd_val |= MMC_STOP_TRANSMISSION;
423 arg = 0;
424 }
425
426 mmc_writel(host, REG_CARG, arg);
427 mmc_writel(host, REG_CMDR, cmd_val);
428
429 do {
430 ri = mmc_readl(host, REG_RINTR);
431 } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
432 time_before(jiffies, expire));
433
434 if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {
435 dev_err(mmc_dev(host->mmc), "send stop command failed\n");
436 if (req->stop)
437 req->stop->resp[0] = -ETIMEDOUT;
438 } else {
439 if (req->stop)
440 req->stop->resp[0] = mmc_readl(host, REG_RESP0);
441 }
442
443 mmc_writel(host, REG_RINTR, 0xffff);
444 }
445
446 static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)
447 {
448 struct mmc_command *cmd = host->mrq->cmd;
449 struct mmc_data *data = host->mrq->data;
450
451 /* For some cmds timeout is normal with sd/mmc cards */
452 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
453 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
454 cmd->opcode == SD_IO_RW_DIRECT))
455 return;
456
457 dev_err(mmc_dev(host->mmc),
458 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
459 host->mmc->index, cmd->opcode,
460 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
461 host->int_sum & SDXC_RESP_ERROR ? " RE" : "",
462 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "",
463 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "",
464 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "",
465 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "",
466 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "",
467 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "",
468 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "",
469 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : ""
470 );
471 }
472
473 /* Called in interrupt context! */
474 static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
475 {
476 struct mmc_request *mrq = host->mrq;
477 struct mmc_data *data = mrq->data;
478 u32 rval;
479
480 mmc_writel(host, REG_IMASK, host->sdio_imask);
481 mmc_writel(host, REG_IDIE, 0);
482
483 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
484 sunxi_mmc_dump_errinfo(host);
485 mrq->cmd->error = -ETIMEDOUT;
486
487 if (data) {
488 data->error = -ETIMEDOUT;
489 host->manual_stop_mrq = mrq;
490 }
491
492 if (mrq->stop)
493 mrq->stop->error = -ETIMEDOUT;
494 } else {
495 if (mrq->cmd->flags & MMC_RSP_136) {
496 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);
497 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);
498 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);
499 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);
500 } else {
501 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);
502 }
503
504 if (data)
505 data->bytes_xfered = data->blocks * data->blksz;
506 }
507
508 if (data) {
509 mmc_writel(host, REG_IDST, 0x337);
510 mmc_writel(host, REG_DMAC, 0);
511 rval = mmc_readl(host, REG_GCTRL);
512 rval |= SDXC_DMA_RESET;
513 mmc_writel(host, REG_GCTRL, rval);
514 rval &= ~SDXC_DMA_ENABLE_BIT;
515 mmc_writel(host, REG_GCTRL, rval);
516 rval |= SDXC_FIFO_RESET;
517 mmc_writel(host, REG_GCTRL, rval);
518 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
519 sunxi_mmc_get_dma_dir(data));
520 }
521
522 mmc_writel(host, REG_RINTR, 0xffff);
523
524 host->mrq = NULL;
525 host->int_sum = 0;
526 host->wait_dma = false;
527
528 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;
529 }
530
531 static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
532 {
533 struct sunxi_mmc_host *host = dev_id;
534 struct mmc_request *mrq;
535 u32 msk_int, idma_int;
536 bool finalize = false;
537 bool sdio_int = false;
538 irqreturn_t ret = IRQ_HANDLED;
539
540 spin_lock(&host->lock);
541
542 idma_int = mmc_readl(host, REG_IDST);
543 msk_int = mmc_readl(host, REG_MISTA);
544
545 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
546 host->mrq, msk_int, idma_int);
547
548 mrq = host->mrq;
549 if (mrq) {
550 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
551 host->wait_dma = false;
552
553 host->int_sum |= msk_int;
554
555 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */
556 if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
557 !(host->int_sum & SDXC_COMMAND_DONE))
558 mmc_writel(host, REG_IMASK,
559 host->sdio_imask | SDXC_COMMAND_DONE);
560 /* Don't wait for dma on error */
561 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
562 finalize = true;
563 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
564 !host->wait_dma)
565 finalize = true;
566 }
567
568 if (msk_int & SDXC_SDIO_INTERRUPT)
569 sdio_int = true;
570
571 mmc_writel(host, REG_RINTR, msk_int);
572 mmc_writel(host, REG_IDST, idma_int);
573
574 if (finalize)
575 ret = sunxi_mmc_finalize_request(host);
576
577 spin_unlock(&host->lock);
578
579 if (finalize && ret == IRQ_HANDLED)
580 mmc_request_done(host->mmc, mrq);
581
582 if (sdio_int)
583 mmc_signal_sdio_irq(host->mmc);
584
585 return ret;
586 }
587
588 static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)
589 {
590 struct sunxi_mmc_host *host = dev_id;
591 struct mmc_request *mrq;
592 unsigned long iflags;
593
594 spin_lock_irqsave(&host->lock, iflags);
595 mrq = host->manual_stop_mrq;
596 spin_unlock_irqrestore(&host->lock, iflags);
597
598 if (!mrq) {
599 dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
600 return IRQ_HANDLED;
601 }
602
603 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
604
605 /*
606 * We will never have more than one outstanding request,
607 * and we do not complete the request until after
608 * we've cleared host->manual_stop_mrq so we do not need to
609 * spin lock this function.
610 * Additionally we have wait states within this function
611 * so having it in a lock is a very bad idea.
612 */
613 sunxi_mmc_send_manual_stop(host, mrq);
614
615 spin_lock_irqsave(&host->lock, iflags);
616 host->manual_stop_mrq = NULL;
617 spin_unlock_irqrestore(&host->lock, iflags);
618
619 mmc_request_done(host->mmc, mrq);
620
621 return IRQ_HANDLED;
622 }
623
624 static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
625 {
626 unsigned long expire = jiffies + msecs_to_jiffies(750);
627 u32 rval;
628
629 rval = mmc_readl(host, REG_CLKCR);
630 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON);
631
632 if (oclk_en)
633 rval |= SDXC_CARD_CLOCK_ON;
634
635 mmc_writel(host, REG_CLKCR, rval);
636
637 rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
638 mmc_writel(host, REG_CMDR, rval);
639
640 do {
641 rval = mmc_readl(host, REG_CMDR);
642 } while (time_before(jiffies, expire) && (rval & SDXC_START));
643
644 /* clear irq status bits set by the command */
645 mmc_writel(host, REG_RINTR,
646 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
647
648 if (rval & SDXC_START) {
649 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
650 return -EIO;
651 }
652
653 return 0;
654 }
655
656 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
657 struct mmc_ios *ios)
658 {
659 u32 rate, oclk_dly, rval, sclk_dly;
660 u32 clock = ios->clock;
661 int ret;
662
663 /* 8 bit DDR requires a higher module clock */
664 if (ios->timing == MMC_TIMING_MMC_DDR52 &&
665 ios->bus_width == MMC_BUS_WIDTH_8)
666 clock <<= 1;
667
668 rate = clk_round_rate(host->clk_mmc, clock);
669 dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %d\n",
670 clock, rate);
671
672 /* setting clock rate */
673 ret = clk_set_rate(host->clk_mmc, rate);
674 if (ret) {
675 dev_err(mmc_dev(host->mmc), "error setting clk to %d: %d\n",
676 rate, ret);
677 return ret;
678 }
679
680 ret = sunxi_mmc_oclk_onoff(host, 0);
681 if (ret)
682 return ret;
683
684 /* clear internal divider */
685 rval = mmc_readl(host, REG_CLKCR);
686 rval &= ~0xff;
687 /* set internal divider for 8 bit eMMC DDR, so card clock is right */
688 if (ios->timing == MMC_TIMING_MMC_DDR52 &&
689 ios->bus_width == MMC_BUS_WIDTH_8) {
690 rval |= 1;
691 rate >>= 1;
692 }
693 mmc_writel(host, REG_CLKCR, rval);
694
695 /* determine delays */
696 if (rate <= 400000) {
697 oclk_dly = host->clk_delays[SDXC_CLK_400K].output;
698 sclk_dly = host->clk_delays[SDXC_CLK_400K].sample;
699 } else if (rate <= 25000000) {
700 oclk_dly = host->clk_delays[SDXC_CLK_25M].output;
701 sclk_dly = host->clk_delays[SDXC_CLK_25M].sample;
702 } else if (rate <= 52000000) {
703 if (ios->timing != MMC_TIMING_UHS_DDR50 &&
704 ios->timing != MMC_TIMING_MMC_DDR52) {
705 oclk_dly = host->clk_delays[SDXC_CLK_50M].output;
706 sclk_dly = host->clk_delays[SDXC_CLK_50M].sample;
707 } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
708 oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR_8BIT].output;
709 sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR_8BIT].sample;
710 } else {
711 oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].output;
712 sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].sample;
713 }
714 } else {
715 return -EINVAL;
716 }
717
718 clk_set_phase(host->clk_sample, sclk_dly);
719 clk_set_phase(host->clk_output, oclk_dly);
720
721 return sunxi_mmc_oclk_onoff(host, 1);
722 }
723
724 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
725 {
726 struct sunxi_mmc_host *host = mmc_priv(mmc);
727 u32 rval;
728
729 /* Set the power state */
730 switch (ios->power_mode) {
731 case MMC_POWER_ON:
732 break;
733
734 case MMC_POWER_UP:
735 host->ferror = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
736 ios->vdd);
737 if (host->ferror)
738 return;
739
740 if (!IS_ERR(mmc->supply.vqmmc)) {
741 host->ferror = regulator_enable(mmc->supply.vqmmc);
742 if (host->ferror) {
743 dev_err(mmc_dev(mmc),
744 "failed to enable vqmmc\n");
745 return;
746 }
747 host->vqmmc_enabled = true;
748 }
749
750 host->ferror = sunxi_mmc_init_host(mmc);
751 if (host->ferror)
752 return;
753
754 dev_dbg(mmc_dev(mmc), "power on!\n");
755 break;
756
757 case MMC_POWER_OFF:
758 dev_dbg(mmc_dev(mmc), "power off!\n");
759 sunxi_mmc_reset_host(host);
760 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
761 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
762 regulator_disable(mmc->supply.vqmmc);
763 host->vqmmc_enabled = false;
764 break;
765 }
766
767 /* set bus width */
768 switch (ios->bus_width) {
769 case MMC_BUS_WIDTH_1:
770 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
771 break;
772 case MMC_BUS_WIDTH_4:
773 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
774 break;
775 case MMC_BUS_WIDTH_8:
776 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
777 break;
778 }
779
780 /* set ddr mode */
781 rval = mmc_readl(host, REG_GCTRL);
782 if (ios->timing == MMC_TIMING_UHS_DDR50 ||
783 ios->timing == MMC_TIMING_MMC_DDR52)
784 rval |= SDXC_DDR_MODE;
785 else
786 rval &= ~SDXC_DDR_MODE;
787 mmc_writel(host, REG_GCTRL, rval);
788
789 /* set up clock */
790 if (ios->clock && ios->power_mode) {
791 host->ferror = sunxi_mmc_clk_set_rate(host, ios);
792 /* Android code had a usleep_range(50000, 55000); here */
793 }
794 }
795
796 static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
797 {
798 /* vqmmc regulator is available */
799 if (!IS_ERR(mmc->supply.vqmmc))
800 return mmc_regulator_set_vqmmc(mmc, ios);
801
802 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
803 if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
804 return 0;
805
806 return -EINVAL;
807 }
808
809 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
810 {
811 struct sunxi_mmc_host *host = mmc_priv(mmc);
812 unsigned long flags;
813 u32 imask;
814
815 spin_lock_irqsave(&host->lock, flags);
816
817 imask = mmc_readl(host, REG_IMASK);
818 if (enable) {
819 host->sdio_imask = SDXC_SDIO_INTERRUPT;
820 imask |= SDXC_SDIO_INTERRUPT;
821 } else {
822 host->sdio_imask = 0;
823 imask &= ~SDXC_SDIO_INTERRUPT;
824 }
825 mmc_writel(host, REG_IMASK, imask);
826 spin_unlock_irqrestore(&host->lock, flags);
827 }
828
829 static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
830 {
831 struct sunxi_mmc_host *host = mmc_priv(mmc);
832 mmc_writel(host, REG_HWRST, 0);
833 udelay(10);
834 mmc_writel(host, REG_HWRST, 1);
835 udelay(300);
836 }
837
838 static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
839 {
840 struct sunxi_mmc_host *host = mmc_priv(mmc);
841 struct mmc_command *cmd = mrq->cmd;
842 struct mmc_data *data = mrq->data;
843 unsigned long iflags;
844 u32 imask = SDXC_INTERRUPT_ERROR_BIT;
845 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
846 bool wait_dma = host->wait_dma;
847 int ret;
848
849 /* Check for set_ios errors (should never happen) */
850 if (host->ferror) {
851 mrq->cmd->error = host->ferror;
852 mmc_request_done(mmc, mrq);
853 return;
854 }
855
856 if (data) {
857 ret = sunxi_mmc_map_dma(host, data);
858 if (ret < 0) {
859 dev_err(mmc_dev(mmc), "map DMA failed\n");
860 cmd->error = ret;
861 data->error = ret;
862 mmc_request_done(mmc, mrq);
863 return;
864 }
865 }
866
867 if (cmd->opcode == MMC_GO_IDLE_STATE) {
868 cmd_val |= SDXC_SEND_INIT_SEQUENCE;
869 imask |= SDXC_COMMAND_DONE;
870 }
871
872 if (cmd->flags & MMC_RSP_PRESENT) {
873 cmd_val |= SDXC_RESP_EXPIRE;
874 if (cmd->flags & MMC_RSP_136)
875 cmd_val |= SDXC_LONG_RESPONSE;
876 if (cmd->flags & MMC_RSP_CRC)
877 cmd_val |= SDXC_CHECK_RESPONSE_CRC;
878
879 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
880 cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
881
882 if (cmd->data->stop) {
883 imask |= SDXC_AUTO_COMMAND_DONE;
884 cmd_val |= SDXC_SEND_AUTO_STOP;
885 } else {
886 imask |= SDXC_DATA_OVER;
887 }
888
889 if (cmd->data->flags & MMC_DATA_WRITE)
890 cmd_val |= SDXC_WRITE;
891 else
892 wait_dma = true;
893 } else {
894 imask |= SDXC_COMMAND_DONE;
895 }
896 } else {
897 imask |= SDXC_COMMAND_DONE;
898 }
899
900 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
901 cmd_val & 0x3f, cmd_val, cmd->arg, imask,
902 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
903
904 spin_lock_irqsave(&host->lock, iflags);
905
906 if (host->mrq || host->manual_stop_mrq) {
907 spin_unlock_irqrestore(&host->lock, iflags);
908
909 if (data)
910 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
911 sunxi_mmc_get_dma_dir(data));
912
913 dev_err(mmc_dev(mmc), "request already pending\n");
914 mrq->cmd->error = -EBUSY;
915 mmc_request_done(mmc, mrq);
916 return;
917 }
918
919 if (data) {
920 mmc_writel(host, REG_BLKSZ, data->blksz);
921 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);
922 sunxi_mmc_start_dma(host, data);
923 }
924
925 host->mrq = mrq;
926 host->wait_dma = wait_dma;
927 mmc_writel(host, REG_IMASK, host->sdio_imask | imask);
928 mmc_writel(host, REG_CARG, cmd->arg);
929 mmc_writel(host, REG_CMDR, cmd_val);
930
931 spin_unlock_irqrestore(&host->lock, iflags);
932 }
933
934 static int sunxi_mmc_card_busy(struct mmc_host *mmc)
935 {
936 struct sunxi_mmc_host *host = mmc_priv(mmc);
937
938 return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);
939 }
940
941 static const struct of_device_id sunxi_mmc_of_match[] = {
942 { .compatible = "allwinner,sun4i-a10-mmc", },
943 { .compatible = "allwinner,sun5i-a13-mmc", },
944 { .compatible = "allwinner,sun9i-a80-mmc", },
945 { /* sentinel */ }
946 };
947 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
948
949 static struct mmc_host_ops sunxi_mmc_ops = {
950 .request = sunxi_mmc_request,
951 .set_ios = sunxi_mmc_set_ios,
952 .get_ro = mmc_gpio_get_ro,
953 .get_cd = mmc_gpio_get_cd,
954 .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
955 .start_signal_voltage_switch = sunxi_mmc_volt_switch,
956 .hw_reset = sunxi_mmc_hw_reset,
957 .card_busy = sunxi_mmc_card_busy,
958 };
959
960 static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
961 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
962 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
963 [SDXC_CLK_50M] = { .output = 90, .sample = 120 },
964 [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 },
965 /* Value from A83T "new timing mode". Works but might not be right. */
966 [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 },
967 };
968
969 static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
970 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
971 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
972 [SDXC_CLK_50M] = { .output = 150, .sample = 120 },
973 [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 },
974 [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 },
975 };
976
977 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
978 struct platform_device *pdev)
979 {
980 struct device_node *np = pdev->dev.of_node;
981 int ret;
982
983 if (of_device_is_compatible(np, "allwinner,sun4i-a10-mmc"))
984 host->idma_des_size_bits = 13;
985 else
986 host->idma_des_size_bits = 16;
987
988 if (of_device_is_compatible(np, "allwinner,sun9i-a80-mmc"))
989 host->clk_delays = sun9i_mmc_clk_delays;
990 else
991 host->clk_delays = sunxi_mmc_clk_delays;
992
993 ret = mmc_regulator_get_supply(host->mmc);
994 if (ret) {
995 if (ret != -EPROBE_DEFER)
996 dev_err(&pdev->dev, "Could not get vmmc supply\n");
997 return ret;
998 }
999
1000 host->reg_base = devm_ioremap_resource(&pdev->dev,
1001 platform_get_resource(pdev, IORESOURCE_MEM, 0));
1002 if (IS_ERR(host->reg_base))
1003 return PTR_ERR(host->reg_base);
1004
1005 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1006 if (IS_ERR(host->clk_ahb)) {
1007 dev_err(&pdev->dev, "Could not get ahb clock\n");
1008 return PTR_ERR(host->clk_ahb);
1009 }
1010
1011 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");
1012 if (IS_ERR(host->clk_mmc)) {
1013 dev_err(&pdev->dev, "Could not get mmc clock\n");
1014 return PTR_ERR(host->clk_mmc);
1015 }
1016
1017 host->clk_output = devm_clk_get(&pdev->dev, "output");
1018 if (IS_ERR(host->clk_output)) {
1019 dev_err(&pdev->dev, "Could not get output clock\n");
1020 return PTR_ERR(host->clk_output);
1021 }
1022
1023 host->clk_sample = devm_clk_get(&pdev->dev, "sample");
1024 if (IS_ERR(host->clk_sample)) {
1025 dev_err(&pdev->dev, "Could not get sample clock\n");
1026 return PTR_ERR(host->clk_sample);
1027 }
1028
1029 host->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
1030 if (PTR_ERR(host->reset) == -EPROBE_DEFER)
1031 return PTR_ERR(host->reset);
1032
1033 ret = clk_prepare_enable(host->clk_ahb);
1034 if (ret) {
1035 dev_err(&pdev->dev, "Enable ahb clk err %d\n", ret);
1036 return ret;
1037 }
1038
1039 ret = clk_prepare_enable(host->clk_mmc);
1040 if (ret) {
1041 dev_err(&pdev->dev, "Enable mmc clk err %d\n", ret);
1042 goto error_disable_clk_ahb;
1043 }
1044
1045 ret = clk_prepare_enable(host->clk_output);
1046 if (ret) {
1047 dev_err(&pdev->dev, "Enable output clk err %d\n", ret);
1048 goto error_disable_clk_mmc;
1049 }
1050
1051 ret = clk_prepare_enable(host->clk_sample);
1052 if (ret) {
1053 dev_err(&pdev->dev, "Enable sample clk err %d\n", ret);
1054 goto error_disable_clk_output;
1055 }
1056
1057 if (!IS_ERR(host->reset)) {
1058 ret = reset_control_deassert(host->reset);
1059 if (ret) {
1060 dev_err(&pdev->dev, "reset err %d\n", ret);
1061 goto error_disable_clk_sample;
1062 }
1063 }
1064
1065 /*
1066 * Sometimes the controller asserts the irq on boot for some reason,
1067 * make sure the controller is in a sane state before enabling irqs.
1068 */
1069 ret = sunxi_mmc_reset_host(host);
1070 if (ret)
1071 goto error_assert_reset;
1072
1073 host->irq = platform_get_irq(pdev, 0);
1074 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,
1075 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);
1076
1077 error_assert_reset:
1078 if (!IS_ERR(host->reset))
1079 reset_control_assert(host->reset);
1080 error_disable_clk_sample:
1081 clk_disable_unprepare(host->clk_sample);
1082 error_disable_clk_output:
1083 clk_disable_unprepare(host->clk_output);
1084 error_disable_clk_mmc:
1085 clk_disable_unprepare(host->clk_mmc);
1086 error_disable_clk_ahb:
1087 clk_disable_unprepare(host->clk_ahb);
1088 return ret;
1089 }
1090
1091 static int sunxi_mmc_probe(struct platform_device *pdev)
1092 {
1093 struct sunxi_mmc_host *host;
1094 struct mmc_host *mmc;
1095 int ret;
1096
1097 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
1098 if (!mmc) {
1099 dev_err(&pdev->dev, "mmc alloc host failed\n");
1100 return -ENOMEM;
1101 }
1102
1103 host = mmc_priv(mmc);
1104 host->mmc = mmc;
1105 spin_lock_init(&host->lock);
1106
1107 ret = sunxi_mmc_resource_request(host, pdev);
1108 if (ret)
1109 goto error_free_host;
1110
1111 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1112 &host->sg_dma, GFP_KERNEL);
1113 if (!host->sg_cpu) {
1114 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
1115 ret = -ENOMEM;
1116 goto error_free_host;
1117 }
1118
1119 mmc->ops = &sunxi_mmc_ops;
1120 mmc->max_blk_count = 8192;
1121 mmc->max_blk_size = 4096;
1122 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
1123 mmc->max_seg_size = (1 << host->idma_des_size_bits);
1124 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
1125 /* 400kHz ~ 52MHz */
1126 mmc->f_min = 400000;
1127 mmc->f_max = 52000000;
1128 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1129 MMC_CAP_1_8V_DDR |
1130 MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
1131
1132 ret = mmc_of_parse(mmc);
1133 if (ret)
1134 goto error_free_dma;
1135
1136 ret = mmc_add_host(mmc);
1137 if (ret)
1138 goto error_free_dma;
1139
1140 dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
1141 platform_set_drvdata(pdev, mmc);
1142 return 0;
1143
1144 error_free_dma:
1145 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1146 error_free_host:
1147 mmc_free_host(mmc);
1148 return ret;
1149 }
1150
1151 static int sunxi_mmc_remove(struct platform_device *pdev)
1152 {
1153 struct mmc_host *mmc = platform_get_drvdata(pdev);
1154 struct sunxi_mmc_host *host = mmc_priv(mmc);
1155
1156 mmc_remove_host(mmc);
1157 disable_irq(host->irq);
1158 sunxi_mmc_reset_host(host);
1159
1160 if (!IS_ERR(host->reset))
1161 reset_control_assert(host->reset);
1162
1163 clk_disable_unprepare(host->clk_mmc);
1164 clk_disable_unprepare(host->clk_ahb);
1165
1166 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1167 mmc_free_host(mmc);
1168
1169 return 0;
1170 }
1171
1172 static struct platform_driver sunxi_mmc_driver = {
1173 .driver = {
1174 .name = "sunxi-mmc",
1175 .of_match_table = of_match_ptr(sunxi_mmc_of_match),
1176 },
1177 .probe = sunxi_mmc_probe,
1178 .remove = sunxi_mmc_remove,
1179 };
1180 module_platform_driver(sunxi_mmc_driver);
1181
1182 MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
1183 MODULE_LICENSE("GPL v2");
1184 MODULE_AUTHOR("David Lanzend�rfer <david.lanzendoerfer@o2s.ch>");
1185 MODULE_ALIAS("platform:sunxi-mmc");
Linux with added FPC-III support