arch/c6x/boot/dts/tms320c6455.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 / {
   4         #address-cells = <1>;
   5         #size-cells = <1>;
   6
   7         cpus {
   8                 #address-cells = <1>;
   9                 #size-cells = <0>;
  10
  11                 cpu@0 {
  12                         device_type = "cpu";
  13                         model = "ti,c64x+";
  14                         reg = <0>;
  15                 };
  16         };
  17
  18         soc {
  19                 compatible = "simple-bus";
  20                 model = "tms320c6455";
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23                 ranges;
  24
  25                 core_pic: interrupt-controller {
  26                           interrupt-controller;
  27                           #interrupt-cells = <1>;
  28                           compatible = "ti,c64x+core-pic";
  29                 };
  30
  31                 /*
  32                  * Megamodule interrupt controller
  33                  */
  34                 megamod_pic: interrupt-controller@1800000 {
  35                        compatible = "ti,c64x+megamod-pic";
  36                        interrupt-controller;
  37                        #interrupt-cells = <1>;
  38                        reg = <0x1800000 0x1000>;
  39                        interrupt-parent = <&core_pic>;
  40                 };
  41
  42                 cache-controller@1840000 {
  43                         compatible = "ti,c64x+cache";
  44                         reg = <0x01840000 0x8400>;
  45                 };
  46
  47                 emifa@70000000 {
  48                         compatible = "ti,c64x+emifa", "simple-bus";
  49                         #address-cells = <2>;
  50                         #size-cells = <1>;
  51                         reg = <0x70000000 0x100>;
  52                         ranges = <0x2 0x0 0xa0000000 0x00000008
  53                                   0x3 0x0 0xb0000000 0x00400000
  54                                   0x4 0x0 0xc0000000 0x10000000
  55                                   0x5 0x0 0xD0000000 0x10000000>;
  56
  57                         ti,dscr-dev-enable = <13>;
  58                         ti,emifa-burst-priority = <255>;
  59                         ti,emifa-ce-config = <0x00240120
  60                                               0x00240120
  61                                               0x00240122
  62                                               0x00240122>;
  63                 };
  64
  65                 timer1: timer@2980000 {
  66                         compatible = "ti,c64x+timer64";
  67                         reg = <0x2980000 0x40>;
  68                         ti,dscr-dev-enable = <4>;
  69                 };
  70
  71                 clock-controller@029a0000 {
  72                         compatible = "ti,c6455-pll", "ti,c64x+pll";
  73                         reg = <0x029a0000 0x200>;
  74                         ti,c64x+pll-bypass-delay = <1440>;
  75                         ti,c64x+pll-reset-delay = <15360>;
  76                         ti,c64x+pll-lock-delay = <24000>;
  77                 };
  78
  79                 device-state-config-regs@2a80000 {
  80                         compatible = "ti,c64x+dscr";
  81                         reg = <0x02a80000 0x41000>;
  82
  83                         ti,dscr-devstat = <0>;
  84                         ti,dscr-silicon-rev = <8 28 0xf>;
  85                         ti,dscr-rmii-resets = <0 0x40020 0x00040000>;
  86
  87                         ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
  88                         ti,dscr-devstate-ctl-regs =
  89                                  <0 12 0x40008 1 0  0  2
  90                                   12 1 0x40008 3 0 30  2
  91                                   13 2 0x4002c 1 0xffffffff 0 1>;
  92                         ti,dscr-devstate-stat-regs =
  93                                 <0 10 0x40014 1 0  0  3
  94                                  10 2 0x40018 1 0  0  3>;
  95                 };
  96         };
  97 };