mm: page_alloc: do not treat a zone that cannot be used for dirty pages as "full"
[linux/fpc-iii.git] / arch / x86 / pci / intel_mid_pci.c
blob84b9d672843db2e0da88d653300991947483628f
1 /*
2 * Intel MID PCI support
3 * Copyright (c) 2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Moorestown has an interesting PCI implementation:
7 * - configuration space is memory mapped (as defined by MCFG)
8 * - Lincroft devices also have a real, type 1 configuration space
9 * - Early Lincroft silicon has a type 1 access bug that will cause
10 * a hang if non-existent devices are accessed
11 * - some devices have the "fixed BAR" capability, which means
12 * they can't be relocated or modified; check for that during
13 * BAR sizing
15 * So, we use the MCFG space for all reads and writes, but also send
16 * Lincroft writes to type 1 space. But only read/write if the device
17 * actually exists, otherwise return all 1s for reads and bit bucket
18 * the writes.
21 #include <linux/sched.h>
22 #include <linux/pci.h>
23 #include <linux/ioport.h>
24 #include <linux/init.h>
25 #include <linux/dmi.h>
26 #include <linux/acpi.h>
27 #include <linux/io.h>
28 #include <linux/smp.h>
30 #include <asm/segment.h>
31 #include <asm/pci_x86.h>
32 #include <asm/hw_irq.h>
33 #include <asm/io_apic.h>
34 #include <asm/intel-mid.h>
36 #define PCIE_CAP_OFFSET 0x100
38 /* Fixed BAR fields */
39 #define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00 /* Fixed BAR (TBD) */
40 #define PCI_FIXED_BAR_0_SIZE 0x04
41 #define PCI_FIXED_BAR_1_SIZE 0x08
42 #define PCI_FIXED_BAR_2_SIZE 0x0c
43 #define PCI_FIXED_BAR_3_SIZE 0x10
44 #define PCI_FIXED_BAR_4_SIZE 0x14
45 #define PCI_FIXED_BAR_5_SIZE 0x1c
47 static int pci_soc_mode;
49 /**
50 * fixed_bar_cap - return the offset of the fixed BAR cap if found
51 * @bus: PCI bus
52 * @devfn: device in question
54 * Look for the fixed BAR cap on @bus and @devfn, returning its offset
55 * if found or 0 otherwise.
57 static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn)
59 int pos;
60 u32 pcie_cap = 0, cap_data;
62 pos = PCIE_CAP_OFFSET;
64 if (!raw_pci_ext_ops)
65 return 0;
67 while (pos) {
68 if (raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
69 devfn, pos, 4, &pcie_cap))
70 return 0;
72 if (PCI_EXT_CAP_ID(pcie_cap) == 0x0000 ||
73 PCI_EXT_CAP_ID(pcie_cap) == 0xffff)
74 break;
76 if (PCI_EXT_CAP_ID(pcie_cap) == PCI_EXT_CAP_ID_VNDR) {
77 raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
78 devfn, pos + 4, 4, &cap_data);
79 if ((cap_data & 0xffff) == PCIE_VNDR_CAP_ID_FIXED_BAR)
80 return pos;
83 pos = PCI_EXT_CAP_NEXT(pcie_cap);
86 return 0;
89 static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
90 int reg, int len, u32 val, int offset)
92 u32 size;
93 unsigned int domain, busnum;
94 int bar = (reg - PCI_BASE_ADDRESS_0) >> 2;
96 domain = pci_domain_nr(bus);
97 busnum = bus->number;
99 if (val == ~0 && len == 4) {
100 unsigned long decode;
102 raw_pci_ext_ops->read(domain, busnum, devfn,
103 offset + 8 + (bar * 4), 4, &size);
105 /* Turn the size into a decode pattern for the sizing code */
106 if (size) {
107 decode = size - 1;
108 decode |= decode >> 1;
109 decode |= decode >> 2;
110 decode |= decode >> 4;
111 decode |= decode >> 8;
112 decode |= decode >> 16;
113 decode++;
114 decode = ~(decode - 1);
115 } else {
116 decode = 0;
120 * If val is all ones, the core code is trying to size the reg,
121 * so update the mmconfig space with the real size.
123 * Note: this assumes the fixed size we got is a power of two.
125 return raw_pci_ext_ops->write(domain, busnum, devfn, reg, 4,
126 decode);
129 /* This is some other kind of BAR write, so just do it. */
130 return raw_pci_ext_ops->write(domain, busnum, devfn, reg, len, val);
134 * type1_access_ok - check whether to use type 1
135 * @bus: bus number
136 * @devfn: device & function in question
138 * If the bus is on a Lincroft chip and it exists, or is not on a Lincroft at
139 * all, the we can go ahead with any reads & writes. If it's on a Lincroft,
140 * but doesn't exist, avoid the access altogether to keep the chip from
141 * hanging.
143 static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
146 * This is a workaround for A0 LNC bug where PCI status register does
147 * not have new CAP bit set. can not be written by SW either.
149 * PCI header type in real LNC indicates a single function device, this
150 * will prevent probing other devices under the same function in PCI
151 * shim. Therefore, use the header type in shim instead.
153 if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE)
154 return false;
155 if (bus == 0 && (devfn == PCI_DEVFN(2, 0)
156 || devfn == PCI_DEVFN(0, 0)
157 || devfn == PCI_DEVFN(3, 0)))
158 return true;
159 return false; /* Langwell on others */
162 static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
163 int size, u32 *value)
165 if (type1_access_ok(bus->number, devfn, where))
166 return pci_direct_conf1.read(pci_domain_nr(bus), bus->number,
167 devfn, where, size, value);
168 return raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
169 devfn, where, size, value);
172 static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
173 int size, u32 value)
175 int offset;
178 * On MRST, there is no PCI ROM BAR, this will cause a subsequent read
179 * to ROM BAR return 0 then being ignored.
181 if (where == PCI_ROM_ADDRESS)
182 return 0;
185 * Devices with fixed BARs need special handling:
186 * - BAR sizing code will save, write ~0, read size, restore
187 * - so writes to fixed BARs need special handling
188 * - other writes to fixed BAR devices should go through mmconfig
190 offset = fixed_bar_cap(bus, devfn);
191 if (offset &&
192 (where >= PCI_BASE_ADDRESS_0 && where <= PCI_BASE_ADDRESS_5)) {
193 return pci_device_update_fixed(bus, devfn, where, size, value,
194 offset);
198 * On Moorestown update both real & mmconfig space
199 * Note: early Lincroft silicon can't handle type 1 accesses to
200 * non-existent devices, so just eat the write in that case.
202 if (type1_access_ok(bus->number, devfn, where))
203 return pci_direct_conf1.write(pci_domain_nr(bus), bus->number,
204 devfn, where, size, value);
205 return raw_pci_ext_ops->write(pci_domain_nr(bus), bus->number, devfn,
206 where, size, value);
209 static int intel_mid_pci_irq_enable(struct pci_dev *dev)
211 u8 pin;
212 struct io_apic_irq_attr irq_attr;
214 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
217 * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
218 * IOAPIC RTE entries, so we just enable RTE for the device.
220 irq_attr.ioapic = mp_find_ioapic(dev->irq);
221 irq_attr.ioapic_pin = dev->irq;
222 irq_attr.trigger = 1; /* level */
223 if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
224 irq_attr.polarity = 0; /* active high */
225 else
226 irq_attr.polarity = 1; /* active low */
227 io_apic_set_pci_routing(&dev->dev, dev->irq, &irq_attr);
229 return 0;
232 struct pci_ops intel_mid_pci_ops = {
233 .read = pci_read,
234 .write = pci_write,
238 * intel_mid_pci_init - installs intel_mid_pci_ops
240 * Moorestown has an interesting PCI implementation (see above).
241 * Called when the early platform detection installs it.
243 int __init intel_mid_pci_init(void)
245 pr_info("Intel MID platform detected, using MID PCI ops\n");
246 pci_mmcfg_late_init();
247 pcibios_enable_irq = intel_mid_pci_irq_enable;
248 pci_root_ops = intel_mid_pci_ops;
249 pci_soc_mode = 1;
250 /* Continue with standard init */
251 return 1;
255 * Langwell devices are not true PCI devices; they are not subject to 10 ms
256 * d3 to d0 delay required by PCI spec.
258 static void pci_d3delay_fixup(struct pci_dev *dev)
261 * PCI fixups are effectively decided compile time. If we have a dual
262 * SoC/non-SoC kernel we don't want to mangle d3 on non-SoC devices.
264 if (!pci_soc_mode)
265 return;
267 * True PCI devices in Lincroft should allow type 1 access, the rest
268 * are Langwell fake PCI devices.
270 if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID))
271 return;
272 dev->d3_delay = 0;
274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup);
276 static void mrst_power_off_unused_dev(struct pci_dev *dev)
278 pci_set_power_state(dev, PCI_D3hot);
280 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0801, mrst_power_off_unused_dev);
281 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0809, mrst_power_off_unused_dev);
282 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x080C, mrst_power_off_unused_dev);
283 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0812, mrst_power_off_unused_dev);
284 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0815, mrst_power_off_unused_dev);
287 * Langwell devices reside at fixed offsets, don't try to move them.
289 static void pci_fixed_bar_fixup(struct pci_dev *dev)
291 unsigned long offset;
292 u32 size;
293 int i;
295 if (!pci_soc_mode)
296 return;
298 /* Must have extended configuration space */
299 if (dev->cfg_size < PCIE_CAP_OFFSET + 4)
300 return;
302 /* Fixup the BAR sizes for fixed BAR devices and make them unmoveable */
303 offset = fixed_bar_cap(dev->bus, dev->devfn);
304 if (!offset || PCI_DEVFN(2, 0) == dev->devfn ||
305 PCI_DEVFN(2, 2) == dev->devfn)
306 return;
308 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
309 pci_read_config_dword(dev, offset + 8 + (i * 4), &size);
310 dev->resource[i].end = dev->resource[i].start + size - 1;
311 dev->resource[i].flags |= IORESOURCE_PCI_FIXED;
314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixed_bar_fixup);