1 /* SPDX-License-Identifier: GPL-2.0 */
3 #ifndef __ABI_CSKY_CACHEFLUSH_H
4 #define __ABI_CSKY_CACHEFLUSH_H
6 /* Keep includes the same across arches. */
10 * The cache doesn't need to be flushed when TLB entries change when
11 * the cache is mapped to physical memory, not virtual memory
13 #define flush_cache_all() do { } while (0)
14 #define flush_cache_mm(mm) do { } while (0)
15 #define flush_cache_dup_mm(mm) do { } while (0)
16 #define flush_cache_range(vma, start, end) do { } while (0)
17 #define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
19 #define PG_dcache_clean PG_arch_1
21 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
22 static inline void flush_dcache_page(struct page
*page
)
24 if (test_bit(PG_dcache_clean
, &page
->flags
))
25 clear_bit(PG_dcache_clean
, &page
->flags
);
28 #define flush_dcache_mmap_lock(mapping) do { } while (0)
29 #define flush_dcache_mmap_unlock(mapping) do { } while (0)
30 #define flush_icache_page(vma, page) do { } while (0)
32 #define flush_icache_range(start, end) cache_wbinv_range(start, end)
34 void flush_icache_mm_range(struct mm_struct
*mm
,
35 unsigned long start
, unsigned long end
);
36 void flush_icache_deferred(struct mm_struct
*mm
);
38 #define flush_cache_vmap(start, end) do { } while (0)
39 #define flush_cache_vunmap(start, end) do { } while (0)
41 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
43 memcpy(dst, src, len); \
44 if (vma->vm_flags & VM_EXEC) { \
45 dcache_wb_range((unsigned long)dst, \
46 (unsigned long)dst + len); \
47 flush_icache_mm_range(current->mm, \
49 (unsigned long)dst + len); \
52 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
55 #endif /* __ABI_CSKY_CACHEFLUSH_H */