drivers/video/fbdev/geode/lxfb.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /* Geode LX framebuffer driver
   3  *
   4  * Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
   5  * Copyright (c) 2008  Andres Salomon <dilinger@debian.org>
   6  */
   7 #ifndef _LXFB_H_
   8 #define _LXFB_H_
   9
  10 #include <linux/fb.h>
  11
  12 #define GP_REG_COUNT    (0x7c / 4)
  13 #define DC_REG_COUNT    (0xf0 / 4)
  14 #define VP_REG_COUNT    (0x158 / 8)
  15 #define FP_REG_COUNT    (0x60 / 8)
  16
  17 #define DC_PAL_COUNT    0x104
  18 #define DC_HFILT_COUNT  0x100
  19 #define DC_VFILT_COUNT  0x100
  20 #define VP_COEFF_SIZE   0x1000
  21 #define VP_PAL_COUNT    0x100
  22
  23 #define OUTPUT_CRT   0x01
  24 #define OUTPUT_PANEL 0x02
  25
  26 struct lxfb_par {
  27         int output;
  28
  29         void __iomem *gp_regs;
  30         void __iomem *dc_regs;
  31         void __iomem *vp_regs;
  32         int powered_down;
  33
  34         /* register state, for power mgmt functionality */
  35         struct {
  36                 uint64_t padsel;
  37                 uint64_t dotpll;
  38                 uint64_t dfglcfg;
  39                 uint64_t dcspare;
  40         } msr;
  41
  42         uint32_t gp[GP_REG_COUNT];
  43         uint32_t dc[DC_REG_COUNT];
  44         uint64_t vp[VP_REG_COUNT];
  45         uint64_t fp[FP_REG_COUNT];
  46
  47         uint32_t dc_pal[DC_PAL_COUNT];
  48         uint32_t vp_pal[VP_PAL_COUNT];
  49         uint32_t hcoeff[DC_HFILT_COUNT * 2];
  50         uint32_t vcoeff[DC_VFILT_COUNT];
  51         uint32_t vp_coeff[VP_COEFF_SIZE / 4];
  52 };
  53
  54 static inline unsigned int lx_get_pitch(unsigned int xres, int bpp)
  55 {
  56         return (((xres * (bpp >> 3)) + 7) & ~7);
  57 }
  58
  59 void lx_set_mode(struct fb_info *);
  60 unsigned int lx_framebuffer_size(void);
  61 int lx_blank_display(struct fb_info *, int);
  62 void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int,
  63                         unsigned int, unsigned int);
  64
  65 int lx_powerdown(struct fb_info *info);
  66 int lx_powerup(struct fb_info *info);
  67
  68 /* Graphics Processor registers (table 6-29 from the data book) */
  69 enum gp_registers {
  70         GP_DST_OFFSET = 0,
  71         GP_SRC_OFFSET,
  72         GP_STRIDE,
  73         GP_WID_HEIGHT,
  74
  75         GP_SRC_COLOR_FG,
  76         GP_SRC_COLOR_BG,
  77         GP_PAT_COLOR_0,
  78         GP_PAT_COLOR_1,
  79
  80         GP_PAT_COLOR_2,
  81         GP_PAT_COLOR_3,
  82         GP_PAT_COLOR_4,
  83         GP_PAT_COLOR_5,
  84
  85         GP_PAT_DATA_0,
  86         GP_PAT_DATA_1,
  87         GP_RASTER_MODE,
  88         GP_VECTOR_MODE,
  89
  90         GP_BLT_MODE,
  91         GP_BLT_STATUS,
  92         GP_HST_SRC,
  93         GP_BASE_OFFSET,
  94
  95         GP_CMD_TOP,
  96         GP_CMD_BOT,
  97         GP_CMD_READ,
  98         GP_CMD_WRITE,
  99
 100         GP_CH3_OFFSET,
 101         GP_CH3_MODE_STR,
 102         GP_CH3_WIDHI,
 103         GP_CH3_HSRC,
 104
 105         GP_LUT_INDEX,
 106         GP_LUT_DATA,
 107         GP_INT_CNTRL, /* 0x78 */
 108 };
 109
 110 #define GP_BLT_STATUS_CE                (1 << 4)        /* cmd buf empty */
 111 #define GP_BLT_STATUS_PB                (1 << 0)        /* primitive busy */
 112
 113
 114 /* Display Controller registers (table 6-47 from the data book) */
 115 enum dc_registers {
 116         DC_UNLOCK = 0,
 117         DC_GENERAL_CFG,
 118         DC_DISPLAY_CFG,
 119         DC_ARB_CFG,
 120
 121         DC_FB_ST_OFFSET,
 122         DC_CB_ST_OFFSET,
 123         DC_CURS_ST_OFFSET,
 124         DC_RSVD_0,
 125
 126         DC_VID_Y_ST_OFFSET,
 127         DC_VID_U_ST_OFFSET,
 128         DC_VID_V_ST_OFFSET,
 129         DC_DV_TOP,
 130
 131         DC_LINE_SIZE,
 132         DC_GFX_PITCH,
 133         DC_VID_YUV_PITCH,
 134         DC_RSVD_1,
 135
 136         DC_H_ACTIVE_TIMING,
 137         DC_H_BLANK_TIMING,
 138         DC_H_SYNC_TIMING,
 139         DC_RSVD_2,
 140
 141         DC_V_ACTIVE_TIMING,
 142         DC_V_BLANK_TIMING,
 143         DC_V_SYNC_TIMING,
 144         DC_FB_ACTIVE,
 145
 146         DC_CURSOR_X,
 147         DC_CURSOR_Y,
 148         DC_RSVD_3,
 149         DC_LINE_CNT,
 150
 151         DC_PAL_ADDRESS,
 152         DC_PAL_DATA,
 153         DC_DFIFO_DIAG,
 154         DC_CFIFO_DIAG,
 155
 156         DC_VID_DS_DELTA,
 157         DC_GLIU0_MEM_OFFSET,
 158         DC_DV_CTL,
 159         DC_DV_ACCESS,
 160
 161         DC_GFX_SCALE,
 162         DC_IRQ_FILT_CTL,
 163         DC_FILT_COEFF1,
 164         DC_FILT_COEFF2,
 165
 166         DC_VBI_EVEN_CTL,
 167         DC_VBI_ODD_CTL,
 168         DC_VBI_HOR,
 169         DC_VBI_LN_ODD,
 170
 171         DC_VBI_LN_EVEN,
 172         DC_VBI_PITCH,
 173         DC_CLR_KEY,
 174         DC_CLR_KEY_MASK,
 175
 176         DC_CLR_KEY_X,
 177         DC_CLR_KEY_Y,
 178         DC_IRQ,
 179         DC_RSVD_4,
 180
 181         DC_RSVD_5,
 182         DC_GENLK_CTL,
 183         DC_VID_EVEN_Y_ST_OFFSET,
 184         DC_VID_EVEN_U_ST_OFFSET,
 185
 186         DC_VID_EVEN_V_ST_OFFSET,
 187         DC_V_ACTIVE_EVEN_TIMING,
 188         DC_V_BLANK_EVEN_TIMING,
 189         DC_V_SYNC_EVEN_TIMING,  /* 0xec */
 190 };
 191
 192 #define DC_UNLOCK_LOCK                  0x00000000
 193 #define DC_UNLOCK_UNLOCK                0x00004758      /* magic value */
 194
 195 #define DC_GENERAL_CFG_FDTY             (1 << 17)
 196 #define DC_GENERAL_CFG_DFHPEL_SHIFT     (12)
 197 #define DC_GENERAL_CFG_DFHPSL_SHIFT     (8)
 198 #define DC_GENERAL_CFG_VGAE             (1 << 7)
 199 #define DC_GENERAL_CFG_DECE             (1 << 6)
 200 #define DC_GENERAL_CFG_CMPE             (1 << 5)
 201 #define DC_GENERAL_CFG_VIDE             (1 << 3)
 202 #define DC_GENERAL_CFG_DFLE             (1 << 0)
 203
 204 #define DC_DISPLAY_CFG_VISL             (1 << 27)
 205 #define DC_DISPLAY_CFG_PALB             (1 << 25)
 206 #define DC_DISPLAY_CFG_DCEN             (1 << 24)
 207 #define DC_DISPLAY_CFG_DISP_MODE_24BPP  (1 << 9)
 208 #define DC_DISPLAY_CFG_DISP_MODE_16BPP  (1 << 8)
 209 #define DC_DISPLAY_CFG_DISP_MODE_8BPP   (0)
 210 #define DC_DISPLAY_CFG_TRUP             (1 << 6)
 211 #define DC_DISPLAY_CFG_VDEN             (1 << 4)
 212 #define DC_DISPLAY_CFG_GDEN             (1 << 3)
 213 #define DC_DISPLAY_CFG_TGEN             (1 << 0)
 214
 215 #define DC_DV_TOP_DV_TOP_EN             (1 << 0)
 216
 217 #define DC_DV_CTL_DV_LINE_SIZE          ((1 << 10) | (1 << 11))
 218 #define DC_DV_CTL_DV_LINE_SIZE_1K       (0)
 219 #define DC_DV_CTL_DV_LINE_SIZE_2K       (1 << 10)
 220 #define DC_DV_CTL_DV_LINE_SIZE_4K       (1 << 11)
 221 #define DC_DV_CTL_DV_LINE_SIZE_8K       ((1 << 10) | (1 << 11))
 222 #define DC_DV_CTL_CLEAR_DV_RAM          (1 << 0)
 223
 224 #define DC_IRQ_FILT_CTL_H_FILT_SEL      (1 << 10)
 225
 226 #define DC_CLR_KEY_CLR_KEY_EN           (1 << 24)
 227
 228 #define DC_IRQ_VIP_VSYNC_IRQ_STATUS     (1 << 21)       /* undocumented? */
 229 #define DC_IRQ_STATUS                   (1 << 20)       /* undocumented? */
 230 #define DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK  (1 << 1)
 231 #define DC_IRQ_MASK                     (1 << 0)
 232
 233 #define DC_GENLK_CTL_FLICK_SEL_MASK     (0x0F << 28)
 234 #define DC_GENLK_CTL_ALPHA_FLICK_EN     (1 << 25)
 235 #define DC_GENLK_CTL_FLICK_EN           (1 << 24)
 236 #define DC_GENLK_CTL_GENLK_EN           (1 << 18)
 237
 238
 239 /*
 240  * Video Processor registers (table 6-71).
 241  * There is space for 64 bit values, but we never use more than the
 242  * lower 32 bits.  The actual register save/restore code only bothers
 243  * to restore those 32 bits.
 244  */
 245 enum vp_registers {
 246         VP_VCFG = 0,
 247         VP_DCFG,
 248
 249         VP_VX,
 250         VP_VY,
 251
 252         VP_SCL,
 253         VP_VCK,
 254
 255         VP_VCM,
 256         VP_PAR,
 257
 258         VP_PDR,
 259         VP_SLR,
 260
 261         VP_MISC,
 262         VP_CCS,
 263
 264         VP_VYS,
 265         VP_VXS,
 266
 267         VP_RSVD_0,
 268         VP_VDC,
 269
 270         VP_RSVD_1,
 271         VP_CRC,
 272
 273         VP_CRC32,
 274         VP_VDE,
 275
 276         VP_CCK,
 277         VP_CCM,
 278
 279         VP_CC1,
 280         VP_CC2,
 281
 282         VP_A1X,
 283         VP_A1Y,
 284
 285         VP_A1C,
 286         VP_A1T,
 287
 288         VP_A2X,
 289         VP_A2Y,
 290
 291         VP_A2C,
 292         VP_A2T,
 293
 294         VP_A3X,
 295         VP_A3Y,
 296
 297         VP_A3C,
 298         VP_A3T,
 299
 300         VP_VRR,
 301         VP_AWT,
 302
 303         VP_VTM,
 304         VP_VYE,
 305
 306         VP_A1YE,
 307         VP_A2YE,
 308
 309         VP_A3YE,        /* 0x150 */
 310
 311         VP_VCR = 0x1000, /* 0x1000 - 0x1fff */
 312 };
 313
 314 #define VP_VCFG_VID_EN                  (1 << 0)
 315
 316 #define VP_DCFG_GV_GAM                  (1 << 21)
 317 #define VP_DCFG_PWR_SEQ_DELAY           ((1 << 17) | (1 << 18) | (1 << 19))
 318 #define VP_DCFG_PWR_SEQ_DELAY_DEFAULT   (1 << 19)       /* undocumented */
 319 #define VP_DCFG_CRT_SYNC_SKW            ((1 << 14) | (1 << 15) | (1 << 16))
 320 #define VP_DCFG_CRT_SYNC_SKW_DEFAULT    (1 << 16)
 321 #define VP_DCFG_CRT_VSYNC_POL           (1 << 9)
 322 #define VP_DCFG_CRT_HSYNC_POL           (1 << 8)
 323 #define VP_DCFG_DAC_BL_EN               (1 << 3)
 324 #define VP_DCFG_VSYNC_EN                (1 << 2)
 325 #define VP_DCFG_HSYNC_EN                (1 << 1)
 326 #define VP_DCFG_CRT_EN                  (1 << 0)
 327
 328 #define VP_MISC_APWRDN                  (1 << 11)
 329 #define VP_MISC_DACPWRDN                (1 << 10)
 330 #define VP_MISC_BYP_BOTH                (1 << 0)
 331
 332
 333 /*
 334  * Flat Panel registers (table 6-71).
 335  * Also 64 bit registers; see above note about 32-bit handling.
 336  */
 337
 338 /* we're actually in the VP register space, starting at address 0x400 */
 339 #define VP_FP_START     0x400
 340
 341 enum fp_registers {
 342         FP_PT1 = 0,
 343         FP_PT2,
 344
 345         FP_PM,
 346         FP_DFC,
 347
 348         FP_RSVD_0,
 349         FP_RSVD_1,
 350
 351         FP_RSVD_2,
 352         FP_RSVD_3,
 353
 354         FP_RSVD_4,
 355         FP_DCA,
 356
 357         FP_DMD,
 358         FP_CRC, /* 0x458 */
 359 };
 360
 361 #define FP_PT2_HSP                      (1 << 22)
 362 #define FP_PT2_VSP                      (1 << 23)
 363 #define FP_PT2_SCRC                     (1 << 27)       /* shfclk free */
 364
 365 #define FP_PM_P                         (1 << 24)       /* panel power ctl */
 366 #define FP_PM_PANEL_PWR_UP              (1 << 3)        /* r/o */
 367 #define FP_PM_PANEL_PWR_DOWN            (1 << 2)        /* r/o */
 368 #define FP_PM_PANEL_OFF                 (1 << 1)        /* r/o */
 369 #define FP_PM_PANEL_ON                  (1 << 0)        /* r/o */
 370
 371 #define FP_DFC_BC                       ((1 << 4) | (1 << 5) | (1 << 6))
 372
 373
 374 /* register access functions */
 375
 376 static inline uint32_t read_gp(struct lxfb_par *par, int reg)
 377 {
 378         return readl(par->gp_regs + 4*reg);
 379 }
 380
 381 static inline void write_gp(struct lxfb_par *par, int reg, uint32_t val)
 382 {
 383         writel(val, par->gp_regs + 4*reg);
 384 }
 385
 386 static inline uint32_t read_dc(struct lxfb_par *par, int reg)
 387 {
 388         return readl(par->dc_regs + 4*reg);
 389 }
 390
 391 static inline void write_dc(struct lxfb_par *par, int reg, uint32_t val)
 392 {
 393         writel(val, par->dc_regs + 4*reg);
 394 }
 395
 396 static inline uint32_t read_vp(struct lxfb_par *par, int reg)
 397 {
 398         return readl(par->vp_regs + 8*reg);
 399 }
 400
 401 static inline void write_vp(struct lxfb_par *par, int reg, uint32_t val)
 402 {
 403         writel(val, par->vp_regs + 8*reg);
 404 }
 405
 406 static inline uint32_t read_fp(struct lxfb_par *par, int reg)
 407 {
 408         return readl(par->vp_regs + 8*reg + VP_FP_START);
 409 }
 410
 411 static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val)
 412 {
 413         writel(val, par->vp_regs + 8*reg + VP_FP_START);
 414 }
 415
 416
 417 /* MSRs are defined in linux/cs5535.h; their bitfields are here */
 418
 419 #define MSR_GLCP_DOTPLL_LOCK            (1 << 25)       /* r/o */
 420 #define MSR_GLCP_DOTPLL_HALFPIX         (1 << 24)
 421 #define MSR_GLCP_DOTPLL_BYPASS          (1 << 15)
 422 #define MSR_GLCP_DOTPLL_DOTRESET        (1 << 0)
 423
 424 /* note: this is actually the VP's GLD_MSR_CONFIG */
 425 #define MSR_LX_GLD_MSR_CONFIG_FMT       ((1 << 3) | (1 << 4) | (1 << 5))
 426 #define MSR_LX_GLD_MSR_CONFIG_FMT_FP    (1 << 3)
 427 #define MSR_LX_GLD_MSR_CONFIG_FMT_CRT   (0)
 428 #define MSR_LX_GLD_MSR_CONFIG_FPC       (1 << 15)       /* FP *and* CRT */
 429
 430 #define MSR_LX_MSR_PADSEL_TFT_SEL_LOW   0xDFFFFFFF      /* ??? */
 431 #define MSR_LX_MSR_PADSEL_TFT_SEL_HIGH  0x0000003F      /* ??? */
 432
 433 #define MSR_LX_SPARE_MSR_DIS_CFIFO_HGO  (1 << 11)       /* undocumented */
 434 #define MSR_LX_SPARE_MSR_VFIFO_ARB_SEL  (1 << 10)       /* undocumented */
 435 #define MSR_LX_SPARE_MSR_WM_LPEN_OVRD   (1 << 9)        /* undocumented */
 436 #define MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M (1 << 8)        /* undocumented */
 437 #define MSR_LX_SPARE_MSR_DIS_INIT_V_PRI (1 << 7)        /* undocumented */
 438 #define MSR_LX_SPARE_MSR_DIS_VIFO_WM    (1 << 6)
 439 #define MSR_LX_SPARE_MSR_DIS_CWD_CHECK  (1 << 5)        /* undocumented */
 440 #define MSR_LX_SPARE_MSR_PIX8_PAN_FIX   (1 << 4)        /* undocumented */
 441 #define MSR_LX_SPARE_MSR_FIRST_REQ_MASK (1 << 1)        /* undocumented */
 442
 443 #endif