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Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux/fpc-iii.git] / drivers / clk / clk-aspeed.c
blob9f7f931d6b2f717f786255bfcf74b6a74e212cde
1 // SPDX-License-Identifier: GPL-2.0+
2
3 #define pr_fmt(fmt) "clk-aspeed: " fmt
4
5 #include <linux/clk-provider.h>
6 #include <linux/mfd/syscon.h>
7 #include <linux/of_address.h>
8 #include <linux/of_device.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
11 #include <linux/reset-controller.h>
12 #include <linux/slab.h>
13 #include <linux/spinlock.h>
14
15 #include <dt-bindings/clock/aspeed-clock.h>
16
17 #define ASPEED_NUM_CLKS 35
18
19 #define ASPEED_RESET_CTRL 0x04
20 #define ASPEED_CLK_SELECTION 0x08
21 #define ASPEED_CLK_STOP_CTRL 0x0c
22 #define ASPEED_MPLL_PARAM 0x20
23 #define ASPEED_HPLL_PARAM 0x24
24 #define AST2500_HPLL_BYPASS_EN BIT(20)
25 #define AST2400_HPLL_STRAPPED BIT(18)
26 #define AST2400_HPLL_BYPASS_EN BIT(17)
27 #define ASPEED_MISC_CTRL 0x2c
28 #define UART_DIV13_EN BIT(12)
29 #define ASPEED_STRAP 0x70
30 #define CLKIN_25MHZ_EN BIT(23)
31 #define AST2400_CLK_SOURCE_SEL BIT(18)
32 #define ASPEED_CLK_SELECTION_2 0xd8
33
34 /* Globally visible clocks */
35 static DEFINE_SPINLOCK(aspeed_clk_lock);
36
37 /* Keeps track of all clocks */
38 static struct clk_hw_onecell_data *aspeed_clk_data;
39
40 static void __iomem *scu_base;
41
42 /**
43 * struct aspeed_gate_data - Aspeed gated clocks
44 * @clock_idx: bit used to gate this clock in the clock register
45 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
46 * reset is required when enabling the clock
47 * @name: the clock name
48 * @parent_name: the name of the parent clock
49 * @flags: standard clock framework flags
50 */
51 struct aspeed_gate_data {
52 u8 clock_idx;
53 s8 reset_idx;
54 const char *name;
55 const char *parent_name;
56 unsigned long flags;
57 };
58
59 /**
60 * struct aspeed_clk_gate - Aspeed specific clk_gate structure
61 * @hw: handle between common and hardware-specific interfaces
62 * @reg: register controlling gate
63 * @clock_idx: bit used to gate this clock in the clock register
64 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
65 * reset is required when enabling the clock
66 * @flags: hardware-specific flags
67 * @lock: register lock
68 *
69 * Some of the clocks in the Aspeed SoC must be put in reset before enabling.
70 * This modified version of clk_gate allows an optional reset bit to be
71 * specified.
72 */
73 struct aspeed_clk_gate {
74 struct clk_hw hw;
75 struct regmap *map;
76 u8 clock_idx;
77 s8 reset_idx;
78 u8 flags;
79 spinlock_t *lock;
80 };
81
82 #define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
83
84 /* TODO: ask Aspeed about the actual parent data */
85 static const struct aspeed_gate_data aspeed_gates[] = {
86 /* clk rst name parent flags */
87 [ASPEED_CLK_GATE_ECLK] = { 0, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */
88 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
89 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
90 [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
91 [ASPEED_CLK_GATE_BCLK] = { 4, 10, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
92 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, 0 }, /* DAC */
93 [ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL },
94 [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
95 [ASPEED_CLK_GATE_LCLK] = { 8, 5, "lclk-gate", NULL, 0 }, /* LPC */
96 [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */
97 [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", NULL, 0 }, /* GFX CRT */
98 [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
99 [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
100 [ASPEED_CLK_GATE_UART1CLK] = { 15, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
101 [ASPEED_CLK_GATE_UART2CLK] = { 16, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
102 [ASPEED_CLK_GATE_UART5CLK] = { 17, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
103 [ASPEED_CLK_GATE_ESPICLK] = { 19, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
104 [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac", 0 }, /* MAC1 */
105 [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac", 0 }, /* MAC2 */
106 [ASPEED_CLK_GATE_RSACLK] = { 24, -1, "rsaclk-gate", NULL, 0 }, /* RSA */
107 [ASPEED_CLK_GATE_UART3CLK] = { 25, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
108 [ASPEED_CLK_GATE_UART4CLK] = { 26, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
109 [ASPEED_CLK_GATE_SDCLKCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
110 [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
111 };
112
113 static const struct clk_div_table ast2500_mac_div_table[] = {
114 { 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */
115 { 0x1, 4 },
116 { 0x2, 6 },
117 { 0x3, 8 },
118 { 0x4, 10 },
119 { 0x5, 12 },
120 { 0x6, 14 },
121 { 0x7, 16 },
122 { 0 }
123 };
124
125 static const struct clk_div_table ast2400_div_table[] = {
126 { 0x0, 2 },
127 { 0x1, 4 },
128 { 0x2, 6 },
129 { 0x3, 8 },
130 { 0x4, 10 },
131 { 0x5, 12 },
132 { 0x6, 14 },
133 { 0x7, 16 },
134 { 0 }
135 };
136
137 static const struct clk_div_table ast2500_div_table[] = {
138 { 0x0, 4 },
139 { 0x1, 8 },
140 { 0x2, 12 },
141 { 0x3, 16 },
142 { 0x4, 20 },
143 { 0x5, 24 },
144 { 0x6, 28 },
145 { 0x7, 32 },
146 { 0 }
147 };
148
149 static struct clk_hw *aspeed_ast2400_calc_pll(const char *name, u32 val)
150 {
151 unsigned int mult, div;
152
153 if (val & AST2400_HPLL_BYPASS_EN) {
154 /* Pass through mode */
155 mult = div = 1;
156 } else {
157 /* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */
158 u32 n = (val >> 5) & 0x3f;
159 u32 od = (val >> 4) & 0x1;
160 u32 d = val & 0xf;
161
162 mult = (2 - od) * (n + 2);
163 div = d + 1;
164 }
165 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
166 mult, div);
167 };
168
169 static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val)
170 {
171 unsigned int mult, div;
172
173 if (val & AST2500_HPLL_BYPASS_EN) {
174 /* Pass through mode */
175 mult = div = 1;
176 } else {
177 /* F = clkin * [(M+1) / (N+1)] / (P + 1) */
178 u32 p = (val >> 13) & 0x3f;
179 u32 m = (val >> 5) & 0xff;
180 u32 n = val & 0x1f;
181
182 mult = (m + 1) / (n + 1);
183 div = p + 1;
184 }
185
186 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
187 mult, div);
188 }
189
190 struct aspeed_clk_soc_data {
191 const struct clk_div_table *div_table;
192 const struct clk_div_table *mac_div_table;
193 struct clk_hw *(*calc_pll)(const char *name, u32 val);
194 };
195
196 static const struct aspeed_clk_soc_data ast2500_data = {
197 .div_table = ast2500_div_table,
198 .mac_div_table = ast2500_mac_div_table,
199 .calc_pll = aspeed_ast2500_calc_pll,
200 };
201
202 static const struct aspeed_clk_soc_data ast2400_data = {
203 .div_table = ast2400_div_table,
204 .mac_div_table = ast2400_div_table,
205 .calc_pll = aspeed_ast2400_calc_pll,
206 };
207
208 static int aspeed_clk_enable(struct clk_hw *hw)
209 {
210 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
211 unsigned long flags;
212 u32 clk = BIT(gate->clock_idx);
213 u32 rst = BIT(gate->reset_idx);
214 u32 enval;
215
216 spin_lock_irqsave(gate->lock, flags);
217
218 if (gate->reset_idx >= 0) {
219 /* Put IP in reset */
220 regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst);
221
222 /* Delay 100us */
223 udelay(100);
224 }
225
226 /* Enable clock */
227 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
228 regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval);
229
230 if (gate->reset_idx >= 0) {
231 /* A delay of 10ms is specified by the ASPEED docs */
232 mdelay(10);
233
234 /* Take IP out of reset */
235 regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, 0);
236 }
237
238 spin_unlock_irqrestore(gate->lock, flags);
239
240 return 0;
241 }
242
243 static void aspeed_clk_disable(struct clk_hw *hw)
244 {
245 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
246 unsigned long flags;
247 u32 clk = BIT(gate->clock_idx);
248 u32 enval;
249
250 spin_lock_irqsave(gate->lock, flags);
251
252 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? clk : 0;
253 regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval);
254
255 spin_unlock_irqrestore(gate->lock, flags);
256 }
257
258 static int aspeed_clk_is_enabled(struct clk_hw *hw)
259 {
260 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
261 u32 clk = BIT(gate->clock_idx);
262 u32 reg;
263
264 regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, &reg);
265
266 return (reg & clk) ? 0 : 1;
267 }
268
269 static const struct clk_ops aspeed_clk_gate_ops = {
270 .enable = aspeed_clk_enable,
271 .disable = aspeed_clk_disable,
272 .is_enabled = aspeed_clk_is_enabled,
273 };
274
275 /**
276 * struct aspeed_reset - Aspeed reset controller
277 * @map: regmap to access the containing system controller
278 * @rcdev: reset controller device
279 */
280 struct aspeed_reset {
281 struct regmap *map;
282 struct reset_controller_dev rcdev;
283 };
284
285 #define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
286
287 static const u8 aspeed_resets[] = {
288 [ASPEED_RESET_XDMA] = 25,
289 [ASPEED_RESET_MCTP] = 24,
290 [ASPEED_RESET_ADC] = 23,
291 [ASPEED_RESET_JTAG_MASTER] = 22,
292 [ASPEED_RESET_MIC] = 18,
293 [ASPEED_RESET_PWM] = 9,
294 [ASPEED_RESET_PCIVGA] = 8,
295 [ASPEED_RESET_I2C] = 2,
296 [ASPEED_RESET_AHB] = 1,
297 };
298
299 static int aspeed_reset_deassert(struct reset_controller_dev *rcdev,
300 unsigned long id)
301 {
302 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
303 u32 rst = BIT(aspeed_resets[id]);
304
305 return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0);
306 }
307
308 static int aspeed_reset_assert(struct reset_controller_dev *rcdev,
309 unsigned long id)
310 {
311 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
312 u32 rst = BIT(aspeed_resets[id]);
313
314 return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst);
315 }
316
317 static int aspeed_reset_status(struct reset_controller_dev *rcdev,
318 unsigned long id)
319 {
320 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
321 u32 val, rst = BIT(aspeed_resets[id]);
322 int ret;
323
324 ret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val);
325 if (ret)
326 return ret;
327
328 return !!(val & rst);
329 }
330
331 static const struct reset_control_ops aspeed_reset_ops = {
332 .assert = aspeed_reset_assert,
333 .deassert = aspeed_reset_deassert,
334 .status = aspeed_reset_status,
335 };
336
337 static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev,
338 const char *name, const char *parent_name, unsigned long flags,
339 struct regmap *map, u8 clock_idx, u8 reset_idx,
340 u8 clk_gate_flags, spinlock_t *lock)
341 {
342 struct aspeed_clk_gate *gate;
343 struct clk_init_data init;
344 struct clk_hw *hw;
345 int ret;
346
347 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
348 if (!gate)
349 return ERR_PTR(-ENOMEM);
350
351 init.name = name;
352 init.ops = &aspeed_clk_gate_ops;
353 init.flags = flags;
354 init.parent_names = parent_name ? &parent_name : NULL;
355 init.num_parents = parent_name ? 1 : 0;
356
357 gate->map = map;
358 gate->clock_idx = clock_idx;
359 gate->reset_idx = reset_idx;
360 gate->flags = clk_gate_flags;
361 gate->lock = lock;
362 gate->hw.init = &init;
363
364 hw = &gate->hw;
365 ret = clk_hw_register(dev, hw);
366 if (ret) {
367 kfree(gate);
368 hw = ERR_PTR(ret);
369 }
370
371 return hw;
372 }
373
374 static int aspeed_clk_probe(struct platform_device *pdev)
375 {
376 const struct aspeed_clk_soc_data *soc_data;
377 struct device *dev = &pdev->dev;
378 struct aspeed_reset *ar;
379 struct regmap *map;
380 struct clk_hw *hw;
381 u32 val, rate;
382 int i, ret;
383
384 map = syscon_node_to_regmap(dev->of_node);
385 if (IS_ERR(map)) {
386 dev_err(dev, "no syscon regmap\n");
387 return PTR_ERR(map);
388 }
389
390 ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
391 if (!ar)
392 return -ENOMEM;
393
394 ar->map = map;
395 ar->rcdev.owner = THIS_MODULE;
396 ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets);
397 ar->rcdev.ops = &aspeed_reset_ops;
398 ar->rcdev.of_node = dev->of_node;
399
400 ret = devm_reset_controller_register(dev, &ar->rcdev);
401 if (ret) {
402 dev_err(dev, "could not register reset controller\n");
403 return ret;
404 }
405
406 /* SoC generations share common layouts but have different divisors */
407 soc_data = of_device_get_match_data(dev);
408 if (!soc_data) {
409 dev_err(dev, "no match data for platform\n");
410 return -EINVAL;
411 }
412
413 /* UART clock div13 setting */
414 regmap_read(map, ASPEED_MISC_CTRL, &val);
415 if (val & UART_DIV13_EN)
416 rate = 24000000 / 13;
417 else
418 rate = 24000000;
419 /* TODO: Find the parent data for the uart clock */
420 hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
421 if (IS_ERR(hw))
422 return PTR_ERR(hw);
423 aspeed_clk_data->hws[ASPEED_CLK_UART] = hw;
424
425 /*
426 * Memory controller (M-PLL) PLL. This clock is configured by the
427 * bootloader, and is exposed to Linux as a read-only clock rate.
428 */
429 regmap_read(map, ASPEED_MPLL_PARAM, &val);
430 hw = soc_data->calc_pll("mpll", val);
431 if (IS_ERR(hw))
432 return PTR_ERR(hw);
433 aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw;
434
435 /* SD/SDIO clock divider (TODO: There's a gate too) */
436 hw = clk_hw_register_divider_table(dev, "sdio", "hpll", 0,
437 scu_base + ASPEED_CLK_SELECTION, 12, 3, 0,
438 soc_data->div_table,
439 &aspeed_clk_lock);
440 if (IS_ERR(hw))
441 return PTR_ERR(hw);
442 aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw;
443
444 /* MAC AHB bus clock divider */
445 hw = clk_hw_register_divider_table(dev, "mac", "hpll", 0,
446 scu_base + ASPEED_CLK_SELECTION, 16, 3, 0,
447 soc_data->mac_div_table,
448 &aspeed_clk_lock);
449 if (IS_ERR(hw))
450 return PTR_ERR(hw);
451 aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw;
452
453 /* LPC Host (LHCLK) clock divider */
454 hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
455 scu_base + ASPEED_CLK_SELECTION, 20, 3, 0,
456 soc_data->div_table,
457 &aspeed_clk_lock);
458 if (IS_ERR(hw))
459 return PTR_ERR(hw);
460 aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
461
462 /* P-Bus (BCLK) clock divider */
463 hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
464 scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0,
465 soc_data->div_table,
466 &aspeed_clk_lock);
467 if (IS_ERR(hw))
468 return PTR_ERR(hw);
469 aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw;
470
471 /*
472 * TODO: There are a number of clocks that not included in this driver
473 * as more information is required:
474 * D2-PLL
475 * D-PLL
476 * YCLK
477 * RGMII
478 * RMII
479 * UART[1..5] clock source mux
480 * Video Engine (ECLK) mux and clock divider
481 */
482
483 for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) {
484 const struct aspeed_gate_data *gd = &aspeed_gates[i];
485 u32 gate_flags;
486
487 /* Special case: the USB port 1 clock (bit 14) is always
488 * working the opposite way from the other ones.
489 */
490 gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE;
491 hw = aspeed_clk_hw_register_gate(dev,
492 gd->name,
493 gd->parent_name,
494 gd->flags,
495 map,
496 gd->clock_idx,
497 gd->reset_idx,
498 gate_flags,
499 &aspeed_clk_lock);
500 if (IS_ERR(hw))
501 return PTR_ERR(hw);
502 aspeed_clk_data->hws[i] = hw;
503 }
504
505 return 0;
506 };
507
508 static const struct of_device_id aspeed_clk_dt_ids[] = {
509 { .compatible = "aspeed,ast2400-scu", .data = &ast2400_data },
510 { .compatible = "aspeed,ast2500-scu", .data = &ast2500_data },
511 { }
512 };
513
514 static struct platform_driver aspeed_clk_driver = {
515 .probe = aspeed_clk_probe,
516 .driver = {
517 .name = "aspeed-clk",
518 .of_match_table = aspeed_clk_dt_ids,
519 .suppress_bind_attrs = true,
520 },
521 };
522 builtin_platform_driver(aspeed_clk_driver);
523
524 static void __init aspeed_ast2400_cc(struct regmap *map)
525 {
526 struct clk_hw *hw;
527 u32 val, freq, div;
528
529 /*
530 * CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by
531 * strapping
532 */
533 regmap_read(map, ASPEED_STRAP, &val);
534 if (val & CLKIN_25MHZ_EN)
535 freq = 25000000;
536 else if (val & AST2400_CLK_SOURCE_SEL)
537 freq = 48000000;
538 else
539 freq = 24000000;
540 hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq);
541 pr_debug("clkin @%u MHz\n", freq / 1000000);
542
543 /*
544 * High-speed PLL clock derived from the crystal. This the CPU clock,
545 * and we assume that it is enabled
546 */
547 regmap_read(map, ASPEED_HPLL_PARAM, &val);
548 WARN(val & AST2400_HPLL_STRAPPED, "hpll is strapped not configured");
549 aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2400_calc_pll("hpll", val);
550
551 /*
552 * Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK)
553 * 00: Select CPU:AHB = 1:1
554 * 01: Select CPU:AHB = 2:1
555 * 10: Select CPU:AHB = 4:1
556 * 11: Select CPU:AHB = 3:1
557 */
558 regmap_read(map, ASPEED_STRAP, &val);
559 val = (val >> 10) & 0x3;
560 div = val + 1;
561 if (div == 3)
562 div = 4;
563 else if (div == 4)
564 div = 3;
565 hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div);
566 aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;
567
568 /* APB clock clock selection register SCU08 (aka PCLK) */
569 hw = clk_hw_register_divider_table(NULL, "apb", "hpll", 0,
570 scu_base + ASPEED_CLK_SELECTION, 23, 3, 0,
571 ast2400_div_table,
572 &aspeed_clk_lock);
573 aspeed_clk_data->hws[ASPEED_CLK_APB] = hw;
574 }
575
576 static void __init aspeed_ast2500_cc(struct regmap *map)
577 {
578 struct clk_hw *hw;
579 u32 val, freq, div;
580
581 /* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */
582 regmap_read(map, ASPEED_STRAP, &val);
583 if (val & CLKIN_25MHZ_EN)
584 freq = 25000000;
585 else
586 freq = 24000000;
587 hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq);
588 pr_debug("clkin @%u MHz\n", freq / 1000000);
589
590 /*
591 * High-speed PLL clock derived from the crystal. This the CPU clock,
592 * and we assume that it is enabled
593 */
594 regmap_read(map, ASPEED_HPLL_PARAM, &val);
595 aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2500_calc_pll("hpll", val);
596
597 /* Strap bits 11:9 define the AXI/AHB clock frequency ratio (aka HCLK)*/
598 regmap_read(map, ASPEED_STRAP, &val);
599 val = (val >> 9) & 0x7;
600 WARN(val == 0, "strapping is zero: cannot determine ahb clock");
601 div = 2 * (val + 1);
602 hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div);
603 aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;
604
605 /* APB clock clock selection register SCU08 (aka PCLK) */
606 regmap_read(map, ASPEED_CLK_SELECTION, &val);
607 val = (val >> 23) & 0x7;
608 div = 4 * (val + 1);
609 hw = clk_hw_register_fixed_factor(NULL, "apb", "hpll", 0, 1, div);
610 aspeed_clk_data->hws[ASPEED_CLK_APB] = hw;
611 };
612
613 static void __init aspeed_cc_init(struct device_node *np)
614 {
615 struct regmap *map;
616 u32 val;
617 int ret;
618 int i;
619
620 scu_base = of_iomap(np, 0);
621 if (!scu_base)
622 return;
623
624 aspeed_clk_data = kzalloc(sizeof(*aspeed_clk_data) +
625 sizeof(*aspeed_clk_data->hws) * ASPEED_NUM_CLKS,
626 GFP_KERNEL);
627 if (!aspeed_clk_data)
628 return;
629
630 /*
631 * This way all clocks fetched before the platform device probes,
632 * except those we assign here for early use, will be deferred.
633 */
634 for (i = 0; i < ASPEED_NUM_CLKS; i++)
635 aspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
636
637 map = syscon_node_to_regmap(np);
638 if (IS_ERR(map)) {
639 pr_err("no syscon regmap\n");
640 return;
641 }
642 /*
643 * We check that the regmap works on this very first access,
644 * but as this is an MMIO-backed regmap, subsequent regmap
645 * access is not going to fail and we skip error checks from
646 * this point.
647 */
648 ret = regmap_read(map, ASPEED_STRAP, &val);
649 if (ret) {
650 pr_err("failed to read strapping register\n");
651 return;
652 }
653
654 if (of_device_is_compatible(np, "aspeed,ast2400-scu"))
655 aspeed_ast2400_cc(map);
656 else if (of_device_is_compatible(np, "aspeed,ast2500-scu"))
657 aspeed_ast2500_cc(map);
658 else
659 pr_err("unknown platform, failed to add clocks\n");
660
661 aspeed_clk_data->num = ASPEED_NUM_CLKS;
662 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data);
663 if (ret)
664 pr_err("failed to add DT provider: %d\n", ret);
665 };
666 CLK_OF_DECLARE_DRIVER(aspeed_cc_g5, "aspeed,ast2500-scu", aspeed_cc_init);
667 CLK_OF_DECLARE_DRIVER(aspeed_cc_g4, "aspeed,ast2400-scu", aspeed_cc_init);
Linux with added FPC-III support