drivers/gpio/gpio-merrifield.c

   1 /*
   2  * Intel Merrifield SoC GPIO driver
   3  *
   4  * Copyright (c) 2016 Intel Corporation.
   5  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/gpio/driver.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/module.h>
  18 #include <linux/pci.h>
  19 #include <linux/pinctrl/consumer.h>
  20
  21 #define GCCR            0x000   /* controller configuration */
  22 #define GPLR            0x004   /* pin level r/o */
  23 #define GPDR            0x01c   /* pin direction */
  24 #define GPSR            0x034   /* pin set w/o */
  25 #define GPCR            0x04c   /* pin clear w/o */
  26 #define GRER            0x064   /* rising edge detect */
  27 #define GFER            0x07c   /* falling edge detect */
  28 #define GFBR            0x094   /* glitch filter bypass */
  29 #define GIMR            0x0ac   /* interrupt mask */
  30 #define GISR            0x0c4   /* interrupt source */
  31 #define GITR            0x300   /* input type */
  32 #define GLPR            0x318   /* level input polarity */
  33 #define GWMR            0x400   /* wake mask */
  34 #define GWSR            0x418   /* wake source */
  35 #define GSIR            0xc00   /* secure input */
  36
  37 /* Intel Merrifield has 192 GPIO pins */
  38 #define MRFLD_NGPIO     192
  39
  40 struct mrfld_gpio_pinrange {
  41         unsigned int gpio_base;
  42         unsigned int pin_base;
  43         unsigned int npins;
  44 };
  45
  46 #define GPIO_PINRANGE(gstart, gend, pstart)             \
  47         {                                               \
  48                 .gpio_base = (gstart),                  \
  49                 .pin_base = (pstart),                   \
  50                 .npins = (gend) - (gstart) + 1,         \
  51         }
  52
  53 struct mrfld_gpio {
  54         struct gpio_chip        chip;
  55         void __iomem            *reg_base;
  56         raw_spinlock_t          lock;
  57         struct device           *dev;
  58 };
  59
  60 static const struct mrfld_gpio_pinrange mrfld_gpio_ranges[] = {
  61         GPIO_PINRANGE(0, 11, 146),
  62         GPIO_PINRANGE(12, 13, 144),
  63         GPIO_PINRANGE(14, 15, 35),
  64         GPIO_PINRANGE(16, 16, 164),
  65         GPIO_PINRANGE(17, 18, 105),
  66         GPIO_PINRANGE(19, 22, 101),
  67         GPIO_PINRANGE(23, 30, 107),
  68         GPIO_PINRANGE(32, 43, 67),
  69         GPIO_PINRANGE(44, 63, 195),
  70         GPIO_PINRANGE(64, 67, 140),
  71         GPIO_PINRANGE(68, 69, 165),
  72         GPIO_PINRANGE(70, 71, 65),
  73         GPIO_PINRANGE(72, 76, 228),
  74         GPIO_PINRANGE(77, 86, 37),
  75         GPIO_PINRANGE(87, 87, 48),
  76         GPIO_PINRANGE(88, 88, 47),
  77         GPIO_PINRANGE(89, 96, 49),
  78         GPIO_PINRANGE(97, 97, 34),
  79         GPIO_PINRANGE(102, 119, 83),
  80         GPIO_PINRANGE(120, 123, 79),
  81         GPIO_PINRANGE(124, 135, 115),
  82         GPIO_PINRANGE(137, 142, 158),
  83         GPIO_PINRANGE(154, 163, 24),
  84         GPIO_PINRANGE(164, 176, 215),
  85         GPIO_PINRANGE(177, 189, 127),
  86         GPIO_PINRANGE(190, 191, 178),
  87 };
  88
  89 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset,
  90                               unsigned int reg_type_offset)
  91 {
  92         struct mrfld_gpio *priv = gpiochip_get_data(chip);
  93         u8 reg = offset / 32;
  94
  95         return priv->reg_base + reg_type_offset + reg * 4;
  96 }
  97
  98 static int mrfld_gpio_get(struct gpio_chip *chip, unsigned int offset)
  99 {
 100         void __iomem *gplr = gpio_reg(chip, offset, GPLR);
 101
 102         return !!(readl(gplr) & BIT(offset % 32));
 103 }
 104
 105 static void mrfld_gpio_set(struct gpio_chip *chip, unsigned int offset,
 106                            int value)
 107 {
 108         struct mrfld_gpio *priv = gpiochip_get_data(chip);
 109         void __iomem *gpsr, *gpcr;
 110         unsigned long flags;
 111
 112         raw_spin_lock_irqsave(&priv->lock, flags);
 113
 114         if (value) {
 115                 gpsr = gpio_reg(chip, offset, GPSR);
 116                 writel(BIT(offset % 32), gpsr);
 117         } else {
 118                 gpcr = gpio_reg(chip, offset, GPCR);
 119                 writel(BIT(offset % 32), gpcr);
 120         }
 121
 122         raw_spin_unlock_irqrestore(&priv->lock, flags);
 123 }
 124
 125 static int mrfld_gpio_direction_input(struct gpio_chip *chip,
 126                                       unsigned int offset)
 127 {
 128         struct mrfld_gpio *priv = gpiochip_get_data(chip);
 129         void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
 130         unsigned long flags;
 131         u32 value;
 132
 133         raw_spin_lock_irqsave(&priv->lock, flags);
 134
 135         value = readl(gpdr);
 136         value &= ~BIT(offset % 32);
 137         writel(value, gpdr);
 138
 139         raw_spin_unlock_irqrestore(&priv->lock, flags);
 140
 141         return 0;
 142 }
 143
 144 static int mrfld_gpio_direction_output(struct gpio_chip *chip,
 145                                        unsigned int offset, int value)
 146 {
 147         struct mrfld_gpio *priv = gpiochip_get_data(chip);
 148         void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
 149         unsigned long flags;
 150
 151         mrfld_gpio_set(chip, offset, value);
 152
 153         raw_spin_lock_irqsave(&priv->lock, flags);
 154
 155         value = readl(gpdr);
 156         value |= BIT(offset % 32);
 157         writel(value, gpdr);
 158
 159         raw_spin_unlock_irqrestore(&priv->lock, flags);
 160
 161         return 0;
 162 }
 163
 164 static void mrfld_irq_ack(struct irq_data *d)
 165 {
 166         struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
 167         u32 gpio = irqd_to_hwirq(d);
 168         void __iomem *gisr = gpio_reg(&priv->chip, gpio, GISR);
 169         unsigned long flags;
 170
 171         raw_spin_lock_irqsave(&priv->lock, flags);
 172
 173         writel(BIT(gpio % 32), gisr);
 174
 175         raw_spin_unlock_irqrestore(&priv->lock, flags);
 176 }
 177
 178 static void mrfld_irq_unmask_mask(struct irq_data *d, bool unmask)
 179 {
 180         struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
 181         u32 gpio = irqd_to_hwirq(d);
 182         void __iomem *gimr = gpio_reg(&priv->chip, gpio, GIMR);
 183         unsigned long flags;
 184         u32 value;
 185
 186         raw_spin_lock_irqsave(&priv->lock, flags);
 187
 188         if (unmask)
 189                 value = readl(gimr) | BIT(gpio % 32);
 190         else
 191                 value = readl(gimr) & ~BIT(gpio % 32);
 192         writel(value, gimr);
 193
 194         raw_spin_unlock_irqrestore(&priv->lock, flags);
 195 }
 196
 197 static void mrfld_irq_mask(struct irq_data *d)
 198 {
 199         mrfld_irq_unmask_mask(d, false);
 200 }
 201
 202 static void mrfld_irq_unmask(struct irq_data *d)
 203 {
 204         mrfld_irq_unmask_mask(d, true);
 205 }
 206
 207 static int mrfld_irq_set_type(struct irq_data *d, unsigned int type)
 208 {
 209         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 210         struct mrfld_gpio *priv = gpiochip_get_data(gc);
 211         u32 gpio = irqd_to_hwirq(d);
 212         void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
 213         void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
 214         void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR);
 215         void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR);
 216         unsigned long flags;
 217         u32 value;
 218
 219         raw_spin_lock_irqsave(&priv->lock, flags);
 220
 221         if (type & IRQ_TYPE_EDGE_RISING)
 222                 value = readl(grer) | BIT(gpio % 32);
 223         else
 224                 value = readl(grer) & ~BIT(gpio % 32);
 225         writel(value, grer);
 226
 227         if (type & IRQ_TYPE_EDGE_FALLING)
 228                 value = readl(gfer) | BIT(gpio % 32);
 229         else
 230                 value = readl(gfer) & ~BIT(gpio % 32);
 231         writel(value, gfer);
 232
 233         /*
 234          * To prevent glitches from triggering an unintended level interrupt,
 235          * configure GLPR register first and then configure GITR.
 236          */
 237         if (type & IRQ_TYPE_LEVEL_LOW)
 238                 value = readl(glpr) | BIT(gpio % 32);
 239         else
 240                 value = readl(glpr) & ~BIT(gpio % 32);
 241         writel(value, glpr);
 242
 243         if (type & IRQ_TYPE_LEVEL_MASK) {
 244                 value = readl(gitr) | BIT(gpio % 32);
 245                 writel(value, gitr);
 246
 247                 irq_set_handler_locked(d, handle_level_irq);
 248         } else if (type & IRQ_TYPE_EDGE_BOTH) {
 249                 value = readl(gitr) & ~BIT(gpio % 32);
 250                 writel(value, gitr);
 251
 252                 irq_set_handler_locked(d, handle_edge_irq);
 253         }
 254
 255         raw_spin_unlock_irqrestore(&priv->lock, flags);
 256
 257         return 0;
 258 }
 259
 260 static int mrfld_irq_set_wake(struct irq_data *d, unsigned int on)
 261 {
 262         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 263         struct mrfld_gpio *priv = gpiochip_get_data(gc);
 264         u32 gpio = irqd_to_hwirq(d);
 265         void __iomem *gwmr = gpio_reg(&priv->chip, gpio, GWMR);
 266         void __iomem *gwsr = gpio_reg(&priv->chip, gpio, GWSR);
 267         unsigned long flags;
 268         u32 value;
 269
 270         raw_spin_lock_irqsave(&priv->lock, flags);
 271
 272         /* Clear the existing wake status */
 273         writel(BIT(gpio % 32), gwsr);
 274
 275         if (on)
 276                 value = readl(gwmr) | BIT(gpio % 32);
 277         else
 278                 value = readl(gwmr) & ~BIT(gpio % 32);
 279         writel(value, gwmr);
 280
 281         raw_spin_unlock_irqrestore(&priv->lock, flags);
 282
 283         dev_dbg(priv->dev, "%sable wake for gpio %u\n", on ? "en" : "dis", gpio);
 284         return 0;
 285 }
 286
 287 static struct irq_chip mrfld_irqchip = {
 288         .name           = "gpio-merrifield",
 289         .irq_ack        = mrfld_irq_ack,
 290         .irq_mask       = mrfld_irq_mask,
 291         .irq_unmask     = mrfld_irq_unmask,
 292         .irq_set_type   = mrfld_irq_set_type,
 293         .irq_set_wake   = mrfld_irq_set_wake,
 294 };
 295
 296 static void mrfld_irq_handler(struct irq_desc *desc)
 297 {
 298         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 299         struct mrfld_gpio *priv = gpiochip_get_data(gc);
 300         struct irq_chip *irqchip = irq_desc_get_chip(desc);
 301         unsigned long base, gpio;
 302
 303         chained_irq_enter(irqchip, desc);
 304
 305         /* Check GPIO controller to check which pin triggered the interrupt */
 306         for (base = 0; base < priv->chip.ngpio; base += 32) {
 307                 void __iomem *gisr = gpio_reg(&priv->chip, base, GISR);
 308                 void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR);
 309                 unsigned long pending, enabled;
 310
 311                 pending = readl(gisr);
 312                 enabled = readl(gimr);
 313
 314                 /* Only interrupts that are enabled */
 315                 pending &= enabled;
 316
 317                 for_each_set_bit(gpio, &pending, 32) {
 318                         unsigned int irq;
 319
 320                         irq = irq_find_mapping(gc->irqdomain, base + gpio);
 321                         generic_handle_irq(irq);
 322                 }
 323         }
 324
 325         chained_irq_exit(irqchip, desc);
 326 }
 327
 328 static void mrfld_irq_init_hw(struct mrfld_gpio *priv)
 329 {
 330         void __iomem *reg;
 331         unsigned int base;
 332
 333         for (base = 0; base < priv->chip.ngpio; base += 32) {
 334                 /* Clear the rising-edge detect register */
 335                 reg = gpio_reg(&priv->chip, base, GRER);
 336                 writel(0, reg);
 337                 /* Clear the falling-edge detect register */
 338                 reg = gpio_reg(&priv->chip, base, GFER);
 339                 writel(0, reg);
 340         }
 341 }
 342
 343 static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 344 {
 345         const struct mrfld_gpio_pinrange *range;
 346         struct mrfld_gpio *priv;
 347         u32 gpio_base, irq_base;
 348         void __iomem *base;
 349         unsigned int i;
 350         int retval;
 351
 352         retval = pcim_enable_device(pdev);
 353         if (retval)
 354                 return retval;
 355
 356         retval = pcim_iomap_regions(pdev, BIT(1) | BIT(0), pci_name(pdev));
 357         if (retval) {
 358                 dev_err(&pdev->dev, "I/O memory mapping error\n");
 359                 return retval;
 360         }
 361
 362         base = pcim_iomap_table(pdev)[1];
 363
 364         irq_base = readl(base);
 365         gpio_base = readl(sizeof(u32) + base);
 366
 367         /* Release the IO mapping, since we already get the info from BAR1 */
 368         pcim_iounmap_regions(pdev, BIT(1));
 369
 370         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 371         if (!priv) {
 372                 dev_err(&pdev->dev, "can't allocate chip data\n");
 373                 return -ENOMEM;
 374         }
 375
 376         priv->dev = &pdev->dev;
 377         priv->reg_base = pcim_iomap_table(pdev)[0];
 378
 379         priv->chip.label = dev_name(&pdev->dev);
 380         priv->chip.parent = &pdev->dev;
 381         priv->chip.request = gpiochip_generic_request;
 382         priv->chip.free = gpiochip_generic_free;
 383         priv->chip.direction_input = mrfld_gpio_direction_input;
 384         priv->chip.direction_output = mrfld_gpio_direction_output;
 385         priv->chip.get = mrfld_gpio_get;
 386         priv->chip.set = mrfld_gpio_set;
 387         priv->chip.base = gpio_base;
 388         priv->chip.ngpio = MRFLD_NGPIO;
 389         priv->chip.can_sleep = false;
 390
 391         raw_spin_lock_init(&priv->lock);
 392
 393         pci_set_drvdata(pdev, priv);
 394         retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
 395         if (retval) {
 396                 dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
 397                 return retval;
 398         }
 399
 400         for (i = 0; i < ARRAY_SIZE(mrfld_gpio_ranges); i++) {
 401                 range = &mrfld_gpio_ranges[i];
 402                 retval = gpiochip_add_pin_range(&priv->chip,
 403                                                 "pinctrl-merrifield",
 404                                                 range->gpio_base,
 405                                                 range->pin_base,
 406                                                 range->npins);
 407                 if (retval) {
 408                         dev_err(&pdev->dev, "failed to add GPIO pin range\n");
 409                         return retval;
 410                 }
 411         }
 412
 413         retval = gpiochip_irqchip_add(&priv->chip, &mrfld_irqchip, irq_base,
 414                                       handle_simple_irq, IRQ_TYPE_NONE);
 415         if (retval) {
 416                 dev_err(&pdev->dev, "could not connect irqchip to gpiochip\n");
 417                 return retval;
 418         }
 419
 420         mrfld_irq_init_hw(priv);
 421
 422         gpiochip_set_chained_irqchip(&priv->chip, &mrfld_irqchip, pdev->irq,
 423                                      mrfld_irq_handler);
 424
 425         return 0;
 426 }
 427
 428 static const struct pci_device_id mrfld_gpio_ids[] = {
 429         { PCI_VDEVICE(INTEL, 0x1199) },
 430         { }
 431 };
 432 MODULE_DEVICE_TABLE(pci, mrfld_gpio_ids);
 433
 434 static struct pci_driver mrfld_gpio_driver = {
 435         .name           = "gpio-merrifield",
 436         .id_table       = mrfld_gpio_ids,
 437         .probe          = mrfld_gpio_probe,
 438 };
 439
 440 module_pci_driver(mrfld_gpio_driver);
 441
 442 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
 443 MODULE_DESCRIPTION("Intel Merrifield SoC GPIO driver");
 444 MODULE_LICENSE("GPL v2");