drivers/gpio/gpio-mxc.c

   1 /*
   2  * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * Based on code from Freescale,
   6  * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/irq.h>
  26 #include <linux/irqdomain.h>
  27 #include <linux/gpio.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/slab.h>
  30 #include <linux/basic_mmio_gpio.h>
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33 #include <linux/module.h>
  34 #include <asm-generic/bug.h>
  35 #include <asm/mach/irq.h>
  36
  37 enum mxc_gpio_hwtype {
  38         IMX1_GPIO,      /* runs on i.mx1 */
  39         IMX21_GPIO,     /* runs on i.mx21 and i.mx27 */
  40         IMX31_GPIO,     /* runs on i.mx31 */
  41         IMX35_GPIO,     /* runs on all other i.mx */
  42 };
  43
  44 /* device type dependent stuff */
  45 struct mxc_gpio_hwdata {
  46         unsigned dr_reg;
  47         unsigned gdir_reg;
  48         unsigned psr_reg;
  49         unsigned icr1_reg;
  50         unsigned icr2_reg;
  51         unsigned imr_reg;
  52         unsigned isr_reg;
  53         int edge_sel_reg;
  54         unsigned low_level;
  55         unsigned high_level;
  56         unsigned rise_edge;
  57         unsigned fall_edge;
  58 };
  59
  60 struct mxc_gpio_port {
  61         struct list_head node;
  62         void __iomem *base;
  63         int irq;
  64         int irq_high;
  65         struct irq_domain *domain;
  66         struct bgpio_chip bgc;
  67         u32 both_edges;
  68 };
  69
  70 static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
  71         .dr_reg         = 0x1c,
  72         .gdir_reg       = 0x00,
  73         .psr_reg        = 0x24,
  74         .icr1_reg       = 0x28,
  75         .icr2_reg       = 0x2c,
  76         .imr_reg        = 0x30,
  77         .isr_reg        = 0x34,
  78         .edge_sel_reg   = -EINVAL,
  79         .low_level      = 0x03,
  80         .high_level     = 0x02,
  81         .rise_edge      = 0x00,
  82         .fall_edge      = 0x01,
  83 };
  84
  85 static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
  86         .dr_reg         = 0x00,
  87         .gdir_reg       = 0x04,
  88         .psr_reg        = 0x08,
  89         .icr1_reg       = 0x0c,
  90         .icr2_reg       = 0x10,
  91         .imr_reg        = 0x14,
  92         .isr_reg        = 0x18,
  93         .edge_sel_reg   = -EINVAL,
  94         .low_level      = 0x00,
  95         .high_level     = 0x01,
  96         .rise_edge      = 0x02,
  97         .fall_edge      = 0x03,
  98 };
  99
 100 static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
 101         .dr_reg         = 0x00,
 102         .gdir_reg       = 0x04,
 103         .psr_reg        = 0x08,
 104         .icr1_reg       = 0x0c,
 105         .icr2_reg       = 0x10,
 106         .imr_reg        = 0x14,
 107         .isr_reg        = 0x18,
 108         .edge_sel_reg   = 0x1c,
 109         .low_level      = 0x00,
 110         .high_level     = 0x01,
 111         .rise_edge      = 0x02,
 112         .fall_edge      = 0x03,
 113 };
 114
 115 static enum mxc_gpio_hwtype mxc_gpio_hwtype;
 116 static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
 117
 118 #define GPIO_DR                 (mxc_gpio_hwdata->dr_reg)
 119 #define GPIO_GDIR               (mxc_gpio_hwdata->gdir_reg)
 120 #define GPIO_PSR                (mxc_gpio_hwdata->psr_reg)
 121 #define GPIO_ICR1               (mxc_gpio_hwdata->icr1_reg)
 122 #define GPIO_ICR2               (mxc_gpio_hwdata->icr2_reg)
 123 #define GPIO_IMR                (mxc_gpio_hwdata->imr_reg)
 124 #define GPIO_ISR                (mxc_gpio_hwdata->isr_reg)
 125 #define GPIO_EDGE_SEL           (mxc_gpio_hwdata->edge_sel_reg)
 126
 127 #define GPIO_INT_LOW_LEV        (mxc_gpio_hwdata->low_level)
 128 #define GPIO_INT_HIGH_LEV       (mxc_gpio_hwdata->high_level)
 129 #define GPIO_INT_RISE_EDGE      (mxc_gpio_hwdata->rise_edge)
 130 #define GPIO_INT_FALL_EDGE      (mxc_gpio_hwdata->fall_edge)
 131 #define GPIO_INT_BOTH_EDGES     0x4
 132
 133 static struct platform_device_id mxc_gpio_devtype[] = {
 134         {
 135                 .name = "imx1-gpio",
 136                 .driver_data = IMX1_GPIO,
 137         }, {
 138                 .name = "imx21-gpio",
 139                 .driver_data = IMX21_GPIO,
 140         }, {
 141                 .name = "imx31-gpio",
 142                 .driver_data = IMX31_GPIO,
 143         }, {
 144                 .name = "imx35-gpio",
 145                 .driver_data = IMX35_GPIO,
 146         }, {
 147                 /* sentinel */
 148         }
 149 };
 150
 151 static const struct of_device_id mxc_gpio_dt_ids[] = {
 152         { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
 153         { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
 154         { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
 155         { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
 156         { /* sentinel */ }
 157 };
 158
 159 /*
 160  * MX2 has one interrupt *for all* gpio ports. The list is used
 161  * to save the references to all ports, so that mx2_gpio_irq_handler
 162  * can walk through all interrupt status registers.
 163  */
 164 static LIST_HEAD(mxc_gpio_ports);
 165
 166 /* Note: This driver assumes 32 GPIOs are handled in one register */
 167
 168 static int gpio_set_irq_type(struct irq_data *d, u32 type)
 169 {
 170         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 171         struct mxc_gpio_port *port = gc->private;
 172         u32 bit, val;
 173         u32 gpio_idx = d->hwirq;
 174         u32 gpio = port->bgc.gc.base + gpio_idx;
 175         int edge;
 176         void __iomem *reg = port->base;
 177
 178         port->both_edges &= ~(1 << gpio_idx);
 179         switch (type) {
 180         case IRQ_TYPE_EDGE_RISING:
 181                 edge = GPIO_INT_RISE_EDGE;
 182                 break;
 183         case IRQ_TYPE_EDGE_FALLING:
 184                 edge = GPIO_INT_FALL_EDGE;
 185                 break;
 186         case IRQ_TYPE_EDGE_BOTH:
 187                 if (GPIO_EDGE_SEL >= 0) {
 188                         edge = GPIO_INT_BOTH_EDGES;
 189                 } else {
 190                         val = gpio_get_value(gpio);
 191                         if (val) {
 192                                 edge = GPIO_INT_LOW_LEV;
 193                                 pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
 194                         } else {
 195                                 edge = GPIO_INT_HIGH_LEV;
 196                                 pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
 197                         }
 198                         port->both_edges |= 1 << gpio_idx;
 199                 }
 200                 break;
 201         case IRQ_TYPE_LEVEL_LOW:
 202                 edge = GPIO_INT_LOW_LEV;
 203                 break;
 204         case IRQ_TYPE_LEVEL_HIGH:
 205                 edge = GPIO_INT_HIGH_LEV;
 206                 break;
 207         default:
 208                 return -EINVAL;
 209         }
 210
 211         if (GPIO_EDGE_SEL >= 0) {
 212                 val = readl(port->base + GPIO_EDGE_SEL);
 213                 if (edge == GPIO_INT_BOTH_EDGES)
 214                         writel(val | (1 << gpio_idx),
 215                                 port->base + GPIO_EDGE_SEL);
 216                 else
 217                         writel(val & ~(1 << gpio_idx),
 218                                 port->base + GPIO_EDGE_SEL);
 219         }
 220
 221         if (edge != GPIO_INT_BOTH_EDGES) {
 222                 reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
 223                 bit = gpio_idx & 0xf;
 224                 val = readl(reg) & ~(0x3 << (bit << 1));
 225                 writel(val | (edge << (bit << 1)), reg);
 226         }
 227
 228         writel(1 << gpio_idx, port->base + GPIO_ISR);
 229
 230         return 0;
 231 }
 232
 233 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
 234 {
 235         void __iomem *reg = port->base;
 236         u32 bit, val;
 237         int edge;
 238
 239         reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
 240         bit = gpio & 0xf;
 241         val = readl(reg);
 242         edge = (val >> (bit << 1)) & 3;
 243         val &= ~(0x3 << (bit << 1));
 244         if (edge == GPIO_INT_HIGH_LEV) {
 245                 edge = GPIO_INT_LOW_LEV;
 246                 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
 247         } else if (edge == GPIO_INT_LOW_LEV) {
 248                 edge = GPIO_INT_HIGH_LEV;
 249                 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
 250         } else {
 251                 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
 252                        gpio, edge);
 253                 return;
 254         }
 255         writel(val | (edge << (bit << 1)), reg);
 256 }
 257
 258 /* handle 32 interrupts in one status register */
 259 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
 260 {
 261         while (irq_stat != 0) {
 262                 int irqoffset = fls(irq_stat) - 1;
 263
 264                 if (port->both_edges & (1 << irqoffset))
 265                         mxc_flip_edge(port, irqoffset);
 266
 267                 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
 268
 269                 irq_stat &= ~(1 << irqoffset);
 270         }
 271 }
 272
 273 /* MX1 and MX3 has one interrupt *per* gpio port */
 274 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 275 {
 276         u32 irq_stat;
 277         struct mxc_gpio_port *port = irq_get_handler_data(irq);
 278         struct irq_chip *chip = irq_get_chip(irq);
 279
 280         chained_irq_enter(chip, desc);
 281
 282         irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
 283
 284         mxc_gpio_irq_handler(port, irq_stat);
 285
 286         chained_irq_exit(chip, desc);
 287 }
 288
 289 /* MX2 has one interrupt *for all* gpio ports */
 290 static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 291 {
 292         u32 irq_msk, irq_stat;
 293         struct mxc_gpio_port *port;
 294
 295         /* walk through all interrupt status registers */
 296         list_for_each_entry(port, &mxc_gpio_ports, node) {
 297                 irq_msk = readl(port->base + GPIO_IMR);
 298                 if (!irq_msk)
 299                         continue;
 300
 301                 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
 302                 if (irq_stat)
 303                         mxc_gpio_irq_handler(port, irq_stat);
 304         }
 305 }
 306
 307 /*
 308  * Set interrupt number "irq" in the GPIO as a wake-up source.
 309  * While system is running, all registered GPIO interrupts need to have
 310  * wake-up enabled. When system is suspended, only selected GPIO interrupts
 311  * need to have wake-up enabled.
 312  * @param  irq          interrupt source number
 313  * @param  enable       enable as wake-up if equal to non-zero
 314  * @return       This function returns 0 on success.
 315  */
 316 static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
 317 {
 318         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 319         struct mxc_gpio_port *port = gc->private;
 320         u32 gpio_idx = d->hwirq;
 321
 322         if (enable) {
 323                 if (port->irq_high && (gpio_idx >= 16))
 324                         enable_irq_wake(port->irq_high);
 325                 else
 326                         enable_irq_wake(port->irq);
 327         } else {
 328                 if (port->irq_high && (gpio_idx >= 16))
 329                         disable_irq_wake(port->irq_high);
 330                 else
 331                         disable_irq_wake(port->irq);
 332         }
 333
 334         return 0;
 335 }
 336
 337 static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
 338 {
 339         struct irq_chip_generic *gc;
 340         struct irq_chip_type *ct;
 341
 342         gc = irq_alloc_generic_chip("gpio-mxc", 1, irq_base,
 343                                     port->base, handle_level_irq);
 344         gc->private = port;
 345
 346         ct = gc->chip_types;
 347         ct->chip.irq_ack = irq_gc_ack_set_bit;
 348         ct->chip.irq_mask = irq_gc_mask_clr_bit;
 349         ct->chip.irq_unmask = irq_gc_mask_set_bit;
 350         ct->chip.irq_set_type = gpio_set_irq_type;
 351         ct->chip.irq_set_wake = gpio_set_wake_irq;
 352         ct->regs.ack = GPIO_ISR;
 353         ct->regs.mask = GPIO_IMR;
 354
 355         irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
 356                                IRQ_NOREQUEST, 0);
 357 }
 358
 359 static void __devinit mxc_gpio_get_hw(struct platform_device *pdev)
 360 {
 361         const struct of_device_id *of_id =
 362                         of_match_device(mxc_gpio_dt_ids, &pdev->dev);
 363         enum mxc_gpio_hwtype hwtype;
 364
 365         if (of_id)
 366                 pdev->id_entry = of_id->data;
 367         hwtype = pdev->id_entry->driver_data;
 368
 369         if (mxc_gpio_hwtype) {
 370                 /*
 371                  * The driver works with a reasonable presupposition,
 372                  * that is all gpio ports must be the same type when
 373                  * running on one soc.
 374                  */
 375                 BUG_ON(mxc_gpio_hwtype != hwtype);
 376                 return;
 377         }
 378
 379         if (hwtype == IMX35_GPIO)
 380                 mxc_gpio_hwdata = &imx35_gpio_hwdata;
 381         else if (hwtype == IMX31_GPIO)
 382                 mxc_gpio_hwdata = &imx31_gpio_hwdata;
 383         else
 384                 mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
 385
 386         mxc_gpio_hwtype = hwtype;
 387 }
 388
 389 static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 390 {
 391         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 392         struct mxc_gpio_port *port =
 393                 container_of(bgc, struct mxc_gpio_port, bgc);
 394
 395         return irq_find_mapping(port->domain, offset);
 396 }
 397
 398 static int __devinit mxc_gpio_probe(struct platform_device *pdev)
 399 {
 400         struct device_node *np = pdev->dev.of_node;
 401         struct mxc_gpio_port *port;
 402         struct resource *iores;
 403         int irq_base;
 404         int err;
 405
 406         mxc_gpio_get_hw(pdev);
 407
 408         port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
 409         if (!port)
 410                 return -ENOMEM;
 411
 412         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 413         if (!iores) {
 414                 err = -ENODEV;
 415                 goto out_kfree;
 416         }
 417
 418         if (!request_mem_region(iores->start, resource_size(iores),
 419                                 pdev->name)) {
 420                 err = -EBUSY;
 421                 goto out_kfree;
 422         }
 423
 424         port->base = ioremap(iores->start, resource_size(iores));
 425         if (!port->base) {
 426                 err = -ENOMEM;
 427                 goto out_release_mem;
 428         }
 429
 430         port->irq_high = platform_get_irq(pdev, 1);
 431         port->irq = platform_get_irq(pdev, 0);
 432         if (port->irq < 0) {
 433                 err = -EINVAL;
 434                 goto out_iounmap;
 435         }
 436
 437         /* disable the interrupt and clear the status */
 438         writel(0, port->base + GPIO_IMR);
 439         writel(~0, port->base + GPIO_ISR);
 440
 441         if (mxc_gpio_hwtype == IMX21_GPIO) {
 442                 /*
 443                  * Setup one handler for all GPIO interrupts. Actually setting
 444                  * the handler is needed only once, but doing it for every port
 445                  * is more robust and easier.
 446                  */
 447                 irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
 448         } else {
 449                 /* setup one handler for each entry */
 450                 irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
 451                 irq_set_handler_data(port->irq, port);
 452                 if (port->irq_high > 0) {
 453                         /* setup handler for GPIO 16 to 31 */
 454                         irq_set_chained_handler(port->irq_high,
 455                                                 mx3_gpio_irq_handler);
 456                         irq_set_handler_data(port->irq_high, port);
 457                 }
 458         }
 459
 460         err = bgpio_init(&port->bgc, &pdev->dev, 4,
 461                          port->base + GPIO_PSR,
 462                          port->base + GPIO_DR, NULL,
 463                          port->base + GPIO_GDIR, NULL, 0);
 464         if (err)
 465                 goto out_iounmap;
 466
 467         port->bgc.gc.to_irq = mxc_gpio_to_irq;
 468         port->bgc.gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
 469                                              pdev->id * 32;
 470
 471         err = gpiochip_add(&port->bgc.gc);
 472         if (err)
 473                 goto out_bgpio_remove;
 474
 475         irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
 476         if (irq_base < 0) {
 477                 err = irq_base;
 478                 goto out_gpiochip_remove;
 479         }
 480
 481         port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
 482                                              &irq_domain_simple_ops, NULL);
 483         if (!port->domain) {
 484                 err = -ENODEV;
 485                 goto out_irqdesc_free;
 486         }
 487
 488         /* gpio-mxc can be a generic irq chip */
 489         mxc_gpio_init_gc(port, irq_base);
 490
 491         list_add_tail(&port->node, &mxc_gpio_ports);
 492
 493         return 0;
 494
 495 out_irqdesc_free:
 496         irq_free_descs(irq_base, 32);
 497 out_gpiochip_remove:
 498         WARN_ON(gpiochip_remove(&port->bgc.gc) < 0);
 499 out_bgpio_remove:
 500         bgpio_remove(&port->bgc);
 501 out_iounmap:
 502         iounmap(port->base);
 503 out_release_mem:
 504         release_mem_region(iores->start, resource_size(iores));
 505 out_kfree:
 506         kfree(port);
 507         dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
 508         return err;
 509 }
 510
 511 static struct platform_driver mxc_gpio_driver = {
 512         .driver         = {
 513                 .name   = "gpio-mxc",
 514                 .owner  = THIS_MODULE,
 515                 .of_match_table = mxc_gpio_dt_ids,
 516         },
 517         .probe          = mxc_gpio_probe,
 518         .id_table       = mxc_gpio_devtype,
 519 };
 520
 521 static int __init gpio_mxc_init(void)
 522 {
 523         return platform_driver_register(&mxc_gpio_driver);
 524 }
 525 postcore_initcall(gpio_mxc_init);
 526
 527 MODULE_AUTHOR("Freescale Semiconductor, "
 528               "Daniel Mack <danielncaiaq.de>, "
 529               "Juergen Beisert <kernel@pengutronix.de>");
 530 MODULE_DESCRIPTION("Freescale MXC GPIO");
 531 MODULE_LICENSE("GPL");