drivers/gpio/gpio-ich.c

   1 /*
   2  * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
   3  *
   4  * Copyright (C) 2010 Extreme Engineering Solutions.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22
  23 #include <linux/module.h>
  24 #include <linux/pci.h>
  25 #include <linux/gpio.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/mfd/lpc_ich.h>
  28
  29 #define DRV_NAME "gpio_ich"
  30
  31 /*
  32  * GPIO register offsets in GPIO I/O space.
  33  * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
  34  * LVLx registers.  Logic in the read/write functions takes a register and
  35  * an absolute bit number and determines the proper register offset and bit
  36  * number in that register.  For example, to read the value of GPIO bit 50
  37  * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
  38  * bit 18 (50%32).
  39  */
  40 enum GPIO_REG {
  41         GPIO_USE_SEL = 0,
  42         GPIO_IO_SEL,
  43         GPIO_LVL,
  44         GPO_BLINK
  45 };
  46
  47 static const u8 ichx_regs[4][3] = {
  48         {0x00, 0x30, 0x40},     /* USE_SEL[1-3] offsets */
  49         {0x04, 0x34, 0x44},     /* IO_SEL[1-3] offsets */
  50         {0x0c, 0x38, 0x48},     /* LVL[1-3] offsets */
  51         {0x18, 0x18, 0x18},     /* BLINK offset */
  52 };
  53
  54 static const u8 ichx_reglen[3] = {
  55         0x30, 0x10, 0x10,
  56 };
  57
  58 static const u8 avoton_regs[4][3] = {
  59         {0x00, 0x80, 0x00},
  60         {0x04, 0x84, 0x00},
  61         {0x08, 0x88, 0x00},
  62 };
  63
  64 static const u8 avoton_reglen[3] = {
  65         0x10, 0x10, 0x00,
  66 };
  67
  68 #define ICHX_WRITE(val, reg, base_res)  outl(val, (reg) + (base_res)->start)
  69 #define ICHX_READ(reg, base_res)        inl((reg) + (base_res)->start)
  70
  71 struct ichx_desc {
  72         /* Max GPIO pins the chipset can have */
  73         uint ngpio;
  74
  75         /* chipset registers */
  76         const u8 (*regs)[3];
  77         const u8 *reglen;
  78
  79         /* GPO_BLINK is available on this chipset */
  80         bool have_blink;
  81
  82         /* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
  83         bool uses_gpe0;
  84
  85         /* USE_SEL is bogus on some chipsets, eg 3100 */
  86         u32 use_sel_ignore[3];
  87
  88         /* Some chipsets have quirks, let these use their own request/get */
  89         int (*request)(struct gpio_chip *chip, unsigned offset);
  90         int (*get)(struct gpio_chip *chip, unsigned offset);
  91
  92         /*
  93          * Some chipsets don't let reading output values on GPIO_LVL register
  94          * this option allows driver caching written output values
  95          */
  96         bool use_outlvl_cache;
  97 };
  98
  99 static struct {
 100         spinlock_t lock;
 101         struct platform_device *dev;
 102         struct gpio_chip chip;
 103         struct resource *gpio_base;     /* GPIO IO base */
 104         struct resource *pm_base;       /* Power Mangagment IO base */
 105         struct ichx_desc *desc; /* Pointer to chipset-specific description */
 106         u32 orig_gpio_ctrl;     /* Orig CTRL value, used to restore on exit */
 107         u8 use_gpio;            /* Which GPIO groups are usable */
 108         int outlvl_cache[3];    /* cached output values */
 109 } ichx_priv;
 110
 111 static int modparam_gpiobase = -1;      /* dynamic */
 112 module_param_named(gpiobase, modparam_gpiobase, int, 0444);
 113 MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
 114                            "which is the default.");
 115
 116 static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
 117 {
 118         unsigned long flags;
 119         u32 data, tmp;
 120         int reg_nr = nr / 32;
 121         int bit = nr & 0x1f;
 122         int ret = 0;
 123
 124         spin_lock_irqsave(&ichx_priv.lock, flags);
 125
 126         if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
 127                 data = ichx_priv.outlvl_cache[reg_nr];
 128         else
 129                 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
 130                                  ichx_priv.gpio_base);
 131
 132         if (val)
 133                 data |= 1 << bit;
 134         else
 135                 data &= ~(1 << bit);
 136         ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
 137                          ichx_priv.gpio_base);
 138         if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
 139                 ichx_priv.outlvl_cache[reg_nr] = data;
 140
 141         tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
 142                         ichx_priv.gpio_base);
 143         if (verify && data != tmp)
 144                 ret = -EPERM;
 145
 146         spin_unlock_irqrestore(&ichx_priv.lock, flags);
 147
 148         return ret;
 149 }
 150
 151 static int ichx_read_bit(int reg, unsigned nr)
 152 {
 153         unsigned long flags;
 154         u32 data;
 155         int reg_nr = nr / 32;
 156         int bit = nr & 0x1f;
 157
 158         spin_lock_irqsave(&ichx_priv.lock, flags);
 159
 160         data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
 161                          ichx_priv.gpio_base);
 162
 163         if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
 164                 data = ichx_priv.outlvl_cache[reg_nr] | data;
 165
 166         spin_unlock_irqrestore(&ichx_priv.lock, flags);
 167
 168         return data & (1 << bit) ? 1 : 0;
 169 }
 170
 171 static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr)
 172 {
 173         return !!(ichx_priv.use_gpio & (1 << (nr / 32)));
 174 }
 175
 176 static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
 177 {
 178         /*
 179          * Try setting pin as an input and verify it worked since many pins
 180          * are output-only.
 181          */
 182         if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
 183                 return -EINVAL;
 184
 185         return 0;
 186 }
 187
 188 static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
 189                                         int val)
 190 {
 191         /* Disable blink hardware which is available for GPIOs from 0 to 31. */
 192         if (nr < 32 && ichx_priv.desc->have_blink)
 193                 ichx_write_bit(GPO_BLINK, nr, 0, 0);
 194
 195         /* Set GPIO output value. */
 196         ichx_write_bit(GPIO_LVL, nr, val, 0);
 197
 198         /*
 199          * Try setting pin as an output and verify it worked since many pins
 200          * are input-only.
 201          */
 202         if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
 203                 return -EINVAL;
 204
 205         return 0;
 206 }
 207
 208 static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
 209 {
 210         return ichx_read_bit(GPIO_LVL, nr);
 211 }
 212
 213 static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
 214 {
 215         unsigned long flags;
 216         u32 data;
 217
 218         /*
 219          * GPI 0 - 15 need to be read from the power management registers on
 220          * a ICH6/3100 bridge.
 221          */
 222         if (nr < 16) {
 223                 if (!ichx_priv.pm_base)
 224                         return -ENXIO;
 225
 226                 spin_lock_irqsave(&ichx_priv.lock, flags);
 227
 228                 /* GPI 0 - 15 are latched, write 1 to clear*/
 229                 ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base);
 230                 data = ICHX_READ(0, ichx_priv.pm_base);
 231
 232                 spin_unlock_irqrestore(&ichx_priv.lock, flags);
 233
 234                 return (data >> 16) & (1 << nr) ? 1 : 0;
 235         } else {
 236                 return ichx_gpio_get(chip, nr);
 237         }
 238 }
 239
 240 static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
 241 {
 242         if (!ichx_gpio_check_available(chip, nr))
 243                 return -ENXIO;
 244
 245         /*
 246          * Note we assume the BIOS properly set a bridge's USE value.  Some
 247          * chips (eg Intel 3100) have bogus USE values though, so first see if
 248          * the chipset's USE value can be trusted for this specific bit.
 249          * If it can't be trusted, assume that the pin can be used as a GPIO.
 250          */
 251         if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f)))
 252                 return 0;
 253
 254         return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
 255 }
 256
 257 static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
 258 {
 259         /*
 260          * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
 261          * bridge as they are controlled by USE register bits 0 and 1.  See
 262          * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
 263          * additional info.
 264          */
 265         if (nr == 16 || nr == 17)
 266                 nr -= 16;
 267
 268         return ichx_gpio_request(chip, nr);
 269 }
 270
 271 static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
 272 {
 273         ichx_write_bit(GPIO_LVL, nr, val, 0);
 274 }
 275
 276 static void ichx_gpiolib_setup(struct gpio_chip *chip)
 277 {
 278         chip->owner = THIS_MODULE;
 279         chip->label = DRV_NAME;
 280         chip->dev = &ichx_priv.dev->dev;
 281
 282         /* Allow chip-specific overrides of request()/get() */
 283         chip->request = ichx_priv.desc->request ?
 284                 ichx_priv.desc->request : ichx_gpio_request;
 285         chip->get = ichx_priv.desc->get ?
 286                 ichx_priv.desc->get : ichx_gpio_get;
 287
 288         chip->set = ichx_gpio_set;
 289         chip->direction_input = ichx_gpio_direction_input;
 290         chip->direction_output = ichx_gpio_direction_output;
 291         chip->base = modparam_gpiobase;
 292         chip->ngpio = ichx_priv.desc->ngpio;
 293         chip->can_sleep = false;
 294         chip->dbg_show = NULL;
 295 }
 296
 297 /* ICH6-based, 631xesb-based */
 298 static struct ichx_desc ich6_desc = {
 299         /* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
 300         .request = ich6_gpio_request,
 301         .get = ich6_gpio_get,
 302
 303         /* GPIO 0-15 are read in the GPE0_STS PM register */
 304         .uses_gpe0 = true,
 305
 306         .ngpio = 50,
 307         .have_blink = true,
 308 };
 309
 310 /* Intel 3100 */
 311 static struct ichx_desc i3100_desc = {
 312         /*
 313          * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
 314          * the Intel 3100.  See "Table 712. GPIO Summary Table" of 3100
 315          * Datasheet for more info.
 316          */
 317         .use_sel_ignore = {0x00130000, 0x00010000, 0x0},
 318
 319         /* The 3100 needs fixups for GPIO 0 - 17 */
 320         .request = ich6_gpio_request,
 321         .get = ich6_gpio_get,
 322
 323         /* GPIO 0-15 are read in the GPE0_STS PM register */
 324         .uses_gpe0 = true,
 325
 326         .ngpio = 50,
 327 };
 328
 329 /* ICH7 and ICH8-based */
 330 static struct ichx_desc ich7_desc = {
 331         .ngpio = 50,
 332         .have_blink = true,
 333         .regs = ichx_regs,
 334         .reglen = ichx_reglen,
 335 };
 336
 337 /* ICH9-based */
 338 static struct ichx_desc ich9_desc = {
 339         .ngpio = 61,
 340         .have_blink = true,
 341         .regs = ichx_regs,
 342         .reglen = ichx_reglen,
 343 };
 344
 345 /* ICH10-based - Consumer/corporate versions have different amount of GPIO */
 346 static struct ichx_desc ich10_cons_desc = {
 347         .ngpio = 61,
 348         .have_blink = true,
 349         .regs = ichx_regs,
 350         .reglen = ichx_reglen,
 351 };
 352 static struct ichx_desc ich10_corp_desc = {
 353         .ngpio = 72,
 354         .have_blink = true,
 355         .regs = ichx_regs,
 356         .reglen = ichx_reglen,
 357 };
 358
 359 /* Intel 5 series, 6 series, 3400 series, and C200 series */
 360 static struct ichx_desc intel5_desc = {
 361         .ngpio = 76,
 362         .regs = ichx_regs,
 363         .reglen = ichx_reglen,
 364 };
 365
 366 /* Avoton */
 367 static struct ichx_desc avoton_desc = {
 368         /* Avoton has only 59 GPIOs, but we assume the first set of register
 369          * (Core) has 32 instead of 31 to keep gpio-ich compliance
 370          */
 371         .ngpio = 60,
 372         .regs = avoton_regs,
 373         .reglen = avoton_reglen,
 374         .use_outlvl_cache = true,
 375 };
 376
 377 static int ichx_gpio_request_regions(struct resource *res_base,
 378                                                 const char *name, u8 use_gpio)
 379 {
 380         int i;
 381
 382         if (!res_base || !res_base->start || !res_base->end)
 383                 return -ENODEV;
 384
 385         for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
 386                 if (!(use_gpio & (1 << i)))
 387                         continue;
 388                 if (!request_region(
 389                                 res_base->start + ichx_priv.desc->regs[0][i],
 390                                 ichx_priv.desc->reglen[i], name))
 391                         goto request_err;
 392         }
 393         return 0;
 394
 395 request_err:
 396         /* Clean up: release already requested regions, if any */
 397         for (i--; i >= 0; i--) {
 398                 if (!(use_gpio & (1 << i)))
 399                         continue;
 400                 release_region(res_base->start + ichx_priv.desc->regs[0][i],
 401                                ichx_priv.desc->reglen[i]);
 402         }
 403         return -EBUSY;
 404 }
 405
 406 static void ichx_gpio_release_regions(struct resource *res_base, u8 use_gpio)
 407 {
 408         int i;
 409
 410         for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
 411                 if (!(use_gpio & (1 << i)))
 412                         continue;
 413                 release_region(res_base->start + ichx_priv.desc->regs[0][i],
 414                                ichx_priv.desc->reglen[i]);
 415         }
 416 }
 417
 418 static int ichx_gpio_probe(struct platform_device *pdev)
 419 {
 420         struct resource *res_base, *res_pm;
 421         int err;
 422         struct lpc_ich_info *ich_info = dev_get_platdata(&pdev->dev);
 423
 424         if (!ich_info)
 425                 return -ENODEV;
 426
 427         ichx_priv.dev = pdev;
 428
 429         switch (ich_info->gpio_version) {
 430         case ICH_I3100_GPIO:
 431                 ichx_priv.desc = &i3100_desc;
 432                 break;
 433         case ICH_V5_GPIO:
 434                 ichx_priv.desc = &intel5_desc;
 435                 break;
 436         case ICH_V6_GPIO:
 437                 ichx_priv.desc = &ich6_desc;
 438                 break;
 439         case ICH_V7_GPIO:
 440                 ichx_priv.desc = &ich7_desc;
 441                 break;
 442         case ICH_V9_GPIO:
 443                 ichx_priv.desc = &ich9_desc;
 444                 break;
 445         case ICH_V10CORP_GPIO:
 446                 ichx_priv.desc = &ich10_corp_desc;
 447                 break;
 448         case ICH_V10CONS_GPIO:
 449                 ichx_priv.desc = &ich10_cons_desc;
 450                 break;
 451         case AVOTON_GPIO:
 452                 ichx_priv.desc = &avoton_desc;
 453                 break;
 454         default:
 455                 return -ENODEV;
 456         }
 457
 458         spin_lock_init(&ichx_priv.lock);
 459         res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
 460         ichx_priv.use_gpio = ich_info->use_gpio;
 461         err = ichx_gpio_request_regions(res_base, pdev->name,
 462                                         ichx_priv.use_gpio);
 463         if (err)
 464                 return err;
 465
 466         ichx_priv.gpio_base = res_base;
 467
 468         /*
 469          * If necessary, determine the I/O address of ACPI/power management
 470          * registers which are needed to read the the GPE0 register for GPI pins
 471          * 0 - 15 on some chipsets.
 472          */
 473         if (!ichx_priv.desc->uses_gpe0)
 474                 goto init;
 475
 476         res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
 477         if (!res_pm) {
 478                 pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
 479                 goto init;
 480         }
 481
 482         if (!request_region(res_pm->start, resource_size(res_pm),
 483                         pdev->name)) {
 484                 pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
 485                 goto init;
 486         }
 487
 488         ichx_priv.pm_base = res_pm;
 489
 490 init:
 491         ichx_gpiolib_setup(&ichx_priv.chip);
 492         err = gpiochip_add(&ichx_priv.chip);
 493         if (err) {
 494                 pr_err("Failed to register GPIOs\n");
 495                 goto add_err;
 496         }
 497
 498         pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
 499                ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);
 500
 501         return 0;
 502
 503 add_err:
 504         ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
 505         if (ichx_priv.pm_base)
 506                 release_region(ichx_priv.pm_base->start,
 507                                 resource_size(ichx_priv.pm_base));
 508         return err;
 509 }
 510
 511 static int ichx_gpio_remove(struct platform_device *pdev)
 512 {
 513         int err;
 514
 515         err = gpiochip_remove(&ichx_priv.chip);
 516         if (err) {
 517                 dev_err(&pdev->dev, "%s failed, %d\n",
 518                                 "gpiochip_remove()", err);
 519                 return err;
 520         }
 521
 522         ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio);
 523         if (ichx_priv.pm_base)
 524                 release_region(ichx_priv.pm_base->start,
 525                                 resource_size(ichx_priv.pm_base));
 526
 527         return 0;
 528 }
 529
 530 static struct platform_driver ichx_gpio_driver = {
 531         .driver         = {
 532                 .owner  = THIS_MODULE,
 533                 .name   = DRV_NAME,
 534         },
 535         .probe          = ichx_gpio_probe,
 536         .remove         = ichx_gpio_remove,
 537 };
 538
 539 module_platform_driver(ichx_gpio_driver);
 540
 541 MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
 542 MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
 543 MODULE_LICENSE("GPL");
 544 MODULE_ALIAS("platform:"DRV_NAME);