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ARM: dts: omap5: Add bus_dma_limit for L3 bus
[linux/fpc-iii.git] / sound / soc / codecs / max98088.c
blobf031d2caa8b774d542ce4249e94a14342ee2a418
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * max98088.c -- MAX98088 ALSA SoC Audio driver
4 *
5 * Copyright 2010 Maxim Integrated Products
6 */
7
8 #include <linux/module.h>
9 #include <linux/moduleparam.h>
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/i2c.h>
15 #include <linux/regmap.h>
16 #include <linux/clk.h>
17 #include <sound/core.h>
18 #include <sound/pcm.h>
19 #include <sound/pcm_params.h>
20 #include <sound/soc.h>
21 #include <sound/initval.h>
22 #include <sound/tlv.h>
23 #include <linux/slab.h>
24 #include <asm/div64.h>
25 #include <sound/max98088.h>
26 #include "max98088.h"
27
28 enum max98088_type {
29 MAX98088,
30 MAX98089,
31 };
32
33 struct max98088_cdata {
34 unsigned int rate;
35 unsigned int fmt;
36 int eq_sel;
37 };
38
39 struct max98088_priv {
40 struct regmap *regmap;
41 enum max98088_type devtype;
42 struct max98088_pdata *pdata;
43 struct clk *mclk;
44 unsigned int sysclk;
45 struct max98088_cdata dai[2];
46 int eq_textcnt;
47 const char **eq_texts;
48 struct soc_enum eq_enum;
49 u8 ina_state;
50 u8 inb_state;
51 unsigned int ex_mode;
52 unsigned int digmic;
53 unsigned int mic1pre;
54 unsigned int mic2pre;
55 unsigned int extmic_mode;
56 };
57
58 static const struct reg_default max98088_reg[] = {
59 { 0xf, 0x00 }, /* 0F interrupt enable */
60
61 { 0x10, 0x00 }, /* 10 master clock */
62 { 0x11, 0x00 }, /* 11 DAI1 clock mode */
63 { 0x12, 0x00 }, /* 12 DAI1 clock control */
64 { 0x13, 0x00 }, /* 13 DAI1 clock control */
65 { 0x14, 0x00 }, /* 14 DAI1 format */
66 { 0x15, 0x00 }, /* 15 DAI1 clock */
67 { 0x16, 0x00 }, /* 16 DAI1 config */
68 { 0x17, 0x00 }, /* 17 DAI1 TDM */
69 { 0x18, 0x00 }, /* 18 DAI1 filters */
70 { 0x19, 0x00 }, /* 19 DAI2 clock mode */
71 { 0x1a, 0x00 }, /* 1A DAI2 clock control */
72 { 0x1b, 0x00 }, /* 1B DAI2 clock control */
73 { 0x1c, 0x00 }, /* 1C DAI2 format */
74 { 0x1d, 0x00 }, /* 1D DAI2 clock */
75 { 0x1e, 0x00 }, /* 1E DAI2 config */
76 { 0x1f, 0x00 }, /* 1F DAI2 TDM */
77
78 { 0x20, 0x00 }, /* 20 DAI2 filters */
79 { 0x21, 0x00 }, /* 21 data config */
80 { 0x22, 0x00 }, /* 22 DAC mixer */
81 { 0x23, 0x00 }, /* 23 left ADC mixer */
82 { 0x24, 0x00 }, /* 24 right ADC mixer */
83 { 0x25, 0x00 }, /* 25 left HP mixer */
84 { 0x26, 0x00 }, /* 26 right HP mixer */
85 { 0x27, 0x00 }, /* 27 HP control */
86 { 0x28, 0x00 }, /* 28 left REC mixer */
87 { 0x29, 0x00 }, /* 29 right REC mixer */
88 { 0x2a, 0x00 }, /* 2A REC control */
89 { 0x2b, 0x00 }, /* 2B left SPK mixer */
90 { 0x2c, 0x00 }, /* 2C right SPK mixer */
91 { 0x2d, 0x00 }, /* 2D SPK control */
92 { 0x2e, 0x00 }, /* 2E sidetone */
93 { 0x2f, 0x00 }, /* 2F DAI1 playback level */
94
95 { 0x30, 0x00 }, /* 30 DAI1 playback level */
96 { 0x31, 0x00 }, /* 31 DAI2 playback level */
97 { 0x32, 0x00 }, /* 32 DAI2 playbakc level */
98 { 0x33, 0x00 }, /* 33 left ADC level */
99 { 0x34, 0x00 }, /* 34 right ADC level */
100 { 0x35, 0x00 }, /* 35 MIC1 level */
101 { 0x36, 0x00 }, /* 36 MIC2 level */
102 { 0x37, 0x00 }, /* 37 INA level */
103 { 0x38, 0x00 }, /* 38 INB level */
104 { 0x39, 0x00 }, /* 39 left HP volume */
105 { 0x3a, 0x00 }, /* 3A right HP volume */
106 { 0x3b, 0x00 }, /* 3B left REC volume */
107 { 0x3c, 0x00 }, /* 3C right REC volume */
108 { 0x3d, 0x00 }, /* 3D left SPK volume */
109 { 0x3e, 0x00 }, /* 3E right SPK volume */
110 { 0x3f, 0x00 }, /* 3F MIC config */
111
112 { 0x40, 0x00 }, /* 40 MIC threshold */
113 { 0x41, 0x00 }, /* 41 excursion limiter filter */
114 { 0x42, 0x00 }, /* 42 excursion limiter threshold */
115 { 0x43, 0x00 }, /* 43 ALC */
116 { 0x44, 0x00 }, /* 44 power limiter threshold */
117 { 0x45, 0x00 }, /* 45 power limiter config */
118 { 0x46, 0x00 }, /* 46 distortion limiter config */
119 { 0x47, 0x00 }, /* 47 audio input */
120 { 0x48, 0x00 }, /* 48 microphone */
121 { 0x49, 0x00 }, /* 49 level control */
122 { 0x4a, 0x00 }, /* 4A bypass switches */
123 { 0x4b, 0x00 }, /* 4B jack detect */
124 { 0x4c, 0x00 }, /* 4C input enable */
125 { 0x4d, 0x00 }, /* 4D output enable */
126 { 0x4e, 0xF0 }, /* 4E bias control */
127 { 0x4f, 0x00 }, /* 4F DAC power */
128
129 { 0x50, 0x0F }, /* 50 DAC power */
130 { 0x51, 0x00 }, /* 51 system */
131 { 0x52, 0x00 }, /* 52 DAI1 EQ1 */
132 { 0x53, 0x00 }, /* 53 DAI1 EQ1 */
133 { 0x54, 0x00 }, /* 54 DAI1 EQ1 */
134 { 0x55, 0x00 }, /* 55 DAI1 EQ1 */
135 { 0x56, 0x00 }, /* 56 DAI1 EQ1 */
136 { 0x57, 0x00 }, /* 57 DAI1 EQ1 */
137 { 0x58, 0x00 }, /* 58 DAI1 EQ1 */
138 { 0x59, 0x00 }, /* 59 DAI1 EQ1 */
139 { 0x5a, 0x00 }, /* 5A DAI1 EQ1 */
140 { 0x5b, 0x00 }, /* 5B DAI1 EQ1 */
141 { 0x5c, 0x00 }, /* 5C DAI1 EQ2 */
142 { 0x5d, 0x00 }, /* 5D DAI1 EQ2 */
143 { 0x5e, 0x00 }, /* 5E DAI1 EQ2 */
144 { 0x5f, 0x00 }, /* 5F DAI1 EQ2 */
145
146 { 0x60, 0x00 }, /* 60 DAI1 EQ2 */
147 { 0x61, 0x00 }, /* 61 DAI1 EQ2 */
148 { 0x62, 0x00 }, /* 62 DAI1 EQ2 */
149 { 0x63, 0x00 }, /* 63 DAI1 EQ2 */
150 { 0x64, 0x00 }, /* 64 DAI1 EQ2 */
151 { 0x65, 0x00 }, /* 65 DAI1 EQ2 */
152 { 0x66, 0x00 }, /* 66 DAI1 EQ3 */
153 { 0x67, 0x00 }, /* 67 DAI1 EQ3 */
154 { 0x68, 0x00 }, /* 68 DAI1 EQ3 */
155 { 0x69, 0x00 }, /* 69 DAI1 EQ3 */
156 { 0x6a, 0x00 }, /* 6A DAI1 EQ3 */
157 { 0x6b, 0x00 }, /* 6B DAI1 EQ3 */
158 { 0x6c, 0x00 }, /* 6C DAI1 EQ3 */
159 { 0x6d, 0x00 }, /* 6D DAI1 EQ3 */
160 { 0x6e, 0x00 }, /* 6E DAI1 EQ3 */
161 { 0x6f, 0x00 }, /* 6F DAI1 EQ3 */
162
163 { 0x70, 0x00 }, /* 70 DAI1 EQ4 */
164 { 0x71, 0x00 }, /* 71 DAI1 EQ4 */
165 { 0x72, 0x00 }, /* 72 DAI1 EQ4 */
166 { 0x73, 0x00 }, /* 73 DAI1 EQ4 */
167 { 0x74, 0x00 }, /* 74 DAI1 EQ4 */
168 { 0x75, 0x00 }, /* 75 DAI1 EQ4 */
169 { 0x76, 0x00 }, /* 76 DAI1 EQ4 */
170 { 0x77, 0x00 }, /* 77 DAI1 EQ4 */
171 { 0x78, 0x00 }, /* 78 DAI1 EQ4 */
172 { 0x79, 0x00 }, /* 79 DAI1 EQ4 */
173 { 0x7a, 0x00 }, /* 7A DAI1 EQ5 */
174 { 0x7b, 0x00 }, /* 7B DAI1 EQ5 */
175 { 0x7c, 0x00 }, /* 7C DAI1 EQ5 */
176 { 0x7d, 0x00 }, /* 7D DAI1 EQ5 */
177 { 0x7e, 0x00 }, /* 7E DAI1 EQ5 */
178 { 0x7f, 0x00 }, /* 7F DAI1 EQ5 */
179
180 { 0x80, 0x00 }, /* 80 DAI1 EQ5 */
181 { 0x81, 0x00 }, /* 81 DAI1 EQ5 */
182 { 0x82, 0x00 }, /* 82 DAI1 EQ5 */
183 { 0x83, 0x00 }, /* 83 DAI1 EQ5 */
184 { 0x84, 0x00 }, /* 84 DAI2 EQ1 */
185 { 0x85, 0x00 }, /* 85 DAI2 EQ1 */
186 { 0x86, 0x00 }, /* 86 DAI2 EQ1 */
187 { 0x87, 0x00 }, /* 87 DAI2 EQ1 */
188 { 0x88, 0x00 }, /* 88 DAI2 EQ1 */
189 { 0x89, 0x00 }, /* 89 DAI2 EQ1 */
190 { 0x8a, 0x00 }, /* 8A DAI2 EQ1 */
191 { 0x8b, 0x00 }, /* 8B DAI2 EQ1 */
192 { 0x8c, 0x00 }, /* 8C DAI2 EQ1 */
193 { 0x8d, 0x00 }, /* 8D DAI2 EQ1 */
194 { 0x8e, 0x00 }, /* 8E DAI2 EQ2 */
195 { 0x8f, 0x00 }, /* 8F DAI2 EQ2 */
196
197 { 0x90, 0x00 }, /* 90 DAI2 EQ2 */
198 { 0x91, 0x00 }, /* 91 DAI2 EQ2 */
199 { 0x92, 0x00 }, /* 92 DAI2 EQ2 */
200 { 0x93, 0x00 }, /* 93 DAI2 EQ2 */
201 { 0x94, 0x00 }, /* 94 DAI2 EQ2 */
202 { 0x95, 0x00 }, /* 95 DAI2 EQ2 */
203 { 0x96, 0x00 }, /* 96 DAI2 EQ2 */
204 { 0x97, 0x00 }, /* 97 DAI2 EQ2 */
205 { 0x98, 0x00 }, /* 98 DAI2 EQ3 */
206 { 0x99, 0x00 }, /* 99 DAI2 EQ3 */
207 { 0x9a, 0x00 }, /* 9A DAI2 EQ3 */
208 { 0x9b, 0x00 }, /* 9B DAI2 EQ3 */
209 { 0x9c, 0x00 }, /* 9C DAI2 EQ3 */
210 { 0x9d, 0x00 }, /* 9D DAI2 EQ3 */
211 { 0x9e, 0x00 }, /* 9E DAI2 EQ3 */
212 { 0x9f, 0x00 }, /* 9F DAI2 EQ3 */
213
214 { 0xa0, 0x00 }, /* A0 DAI2 EQ3 */
215 { 0xa1, 0x00 }, /* A1 DAI2 EQ3 */
216 { 0xa2, 0x00 }, /* A2 DAI2 EQ4 */
217 { 0xa3, 0x00 }, /* A3 DAI2 EQ4 */
218 { 0xa4, 0x00 }, /* A4 DAI2 EQ4 */
219 { 0xa5, 0x00 }, /* A5 DAI2 EQ4 */
220 { 0xa6, 0x00 }, /* A6 DAI2 EQ4 */
221 { 0xa7, 0x00 }, /* A7 DAI2 EQ4 */
222 { 0xa8, 0x00 }, /* A8 DAI2 EQ4 */
223 { 0xa9, 0x00 }, /* A9 DAI2 EQ4 */
224 { 0xaa, 0x00 }, /* AA DAI2 EQ4 */
225 { 0xab, 0x00 }, /* AB DAI2 EQ4 */
226 { 0xac, 0x00 }, /* AC DAI2 EQ5 */
227 { 0xad, 0x00 }, /* AD DAI2 EQ5 */
228 { 0xae, 0x00 }, /* AE DAI2 EQ5 */
229 { 0xaf, 0x00 }, /* AF DAI2 EQ5 */
230
231 { 0xb0, 0x00 }, /* B0 DAI2 EQ5 */
232 { 0xb1, 0x00 }, /* B1 DAI2 EQ5 */
233 { 0xb2, 0x00 }, /* B2 DAI2 EQ5 */
234 { 0xb3, 0x00 }, /* B3 DAI2 EQ5 */
235 { 0xb4, 0x00 }, /* B4 DAI2 EQ5 */
236 { 0xb5, 0x00 }, /* B5 DAI2 EQ5 */
237 { 0xb6, 0x00 }, /* B6 DAI1 biquad */
238 { 0xb7, 0x00 }, /* B7 DAI1 biquad */
239 { 0xb8 ,0x00 }, /* B8 DAI1 biquad */
240 { 0xb9, 0x00 }, /* B9 DAI1 biquad */
241 { 0xba, 0x00 }, /* BA DAI1 biquad */
242 { 0xbb, 0x00 }, /* BB DAI1 biquad */
243 { 0xbc, 0x00 }, /* BC DAI1 biquad */
244 { 0xbd, 0x00 }, /* BD DAI1 biquad */
245 { 0xbe, 0x00 }, /* BE DAI1 biquad */
246 { 0xbf, 0x00 }, /* BF DAI1 biquad */
247
248 { 0xc0, 0x00 }, /* C0 DAI2 biquad */
249 { 0xc1, 0x00 }, /* C1 DAI2 biquad */
250 { 0xc2, 0x00 }, /* C2 DAI2 biquad */
251 { 0xc3, 0x00 }, /* C3 DAI2 biquad */
252 { 0xc4, 0x00 }, /* C4 DAI2 biquad */
253 { 0xc5, 0x00 }, /* C5 DAI2 biquad */
254 { 0xc6, 0x00 }, /* C6 DAI2 biquad */
255 { 0xc7, 0x00 }, /* C7 DAI2 biquad */
256 { 0xc8, 0x00 }, /* C8 DAI2 biquad */
257 { 0xc9, 0x00 }, /* C9 DAI2 biquad */
258 };
259
260 static bool max98088_readable_register(struct device *dev, unsigned int reg)
261 {
262 switch (reg) {
263 case M98088_REG_00_IRQ_STATUS ... 0xC9:
264 case M98088_REG_FF_REV_ID:
265 return true;
266 default:
267 return false;
268 }
269 }
270
271 static bool max98088_writeable_register(struct device *dev, unsigned int reg)
272 {
273 switch (reg) {
274 case M98088_REG_03_BATTERY_VOLTAGE ... 0xC9:
275 return true;
276 default:
277 return false;
278 }
279 }
280
281 static bool max98088_volatile_register(struct device *dev, unsigned int reg)
282 {
283 switch (reg) {
284 case M98088_REG_00_IRQ_STATUS ... M98088_REG_03_BATTERY_VOLTAGE:
285 case M98088_REG_FF_REV_ID:
286 return true;
287 default:
288 return false;
289 }
290 }
291
292 static const struct regmap_config max98088_regmap = {
293 .reg_bits = 8,
294 .val_bits = 8,
295
296 .readable_reg = max98088_readable_register,
297 .writeable_reg = max98088_writeable_register,
298 .volatile_reg = max98088_volatile_register,
299 .max_register = 0xff,
300
301 .reg_defaults = max98088_reg,
302 .num_reg_defaults = ARRAY_SIZE(max98088_reg),
303 .cache_type = REGCACHE_RBTREE,
304 };
305
306 /*
307 * Load equalizer DSP coefficient configurations registers
308 */
309 static void m98088_eq_band(struct snd_soc_component *component, unsigned int dai,
310 unsigned int band, u16 *coefs)
311 {
312 unsigned int eq_reg;
313 unsigned int i;
314
315 if (WARN_ON(band > 4) ||
316 WARN_ON(dai > 1))
317 return;
318
319 /* Load the base register address */
320 eq_reg = dai ? M98088_REG_84_DAI2_EQ_BASE : M98088_REG_52_DAI1_EQ_BASE;
321
322 /* Add the band address offset, note adjustment for word address */
323 eq_reg += band * (M98088_COEFS_PER_BAND << 1);
324
325 /* Step through the registers and coefs */
326 for (i = 0; i < M98088_COEFS_PER_BAND; i++) {
327 snd_soc_component_write(component, eq_reg++, M98088_BYTE1(coefs[i]));
328 snd_soc_component_write(component, eq_reg++, M98088_BYTE0(coefs[i]));
329 }
330 }
331
332 /*
333 * Excursion limiter modes
334 */
335 static const char *max98088_exmode_texts[] = {
336 "Off", "100Hz", "400Hz", "600Hz", "800Hz", "1000Hz", "200-400Hz",
337 "400-600Hz", "400-800Hz",
338 };
339
340 static const unsigned int max98088_exmode_values[] = {
341 0x00, 0x43, 0x10, 0x20, 0x30, 0x40, 0x11, 0x22, 0x32
342 };
343
344 static SOC_VALUE_ENUM_SINGLE_DECL(max98088_exmode_enum,
345 M98088_REG_41_SPKDHP, 0, 127,
346 max98088_exmode_texts,
347 max98088_exmode_values);
348
349 static const char *max98088_ex_thresh[] = { /* volts PP */
350 "0.6", "1.2", "1.8", "2.4", "3.0", "3.6", "4.2", "4.8"};
351 static SOC_ENUM_SINGLE_DECL(max98088_ex_thresh_enum,
352 M98088_REG_42_SPKDHP_THRESH, 0,
353 max98088_ex_thresh);
354
355 static const char *max98088_fltr_mode[] = {"Voice", "Music" };
356 static SOC_ENUM_SINGLE_DECL(max98088_filter_mode_enum,
357 M98088_REG_18_DAI1_FILTERS, 7,
358 max98088_fltr_mode);
359
360 static const char *max98088_extmic_text[] = { "None", "MIC1", "MIC2" };
361
362 static SOC_ENUM_SINGLE_DECL(max98088_extmic_enum,
363 M98088_REG_48_CFG_MIC, 0,
364 max98088_extmic_text);
365
366 static const struct snd_kcontrol_new max98088_extmic_mux =
367 SOC_DAPM_ENUM("External MIC Mux", max98088_extmic_enum);
368
369 static const char *max98088_dai1_fltr[] = {
370 "Off", "fc=258/fs=16k", "fc=500/fs=16k",
371 "fc=258/fs=8k", "fc=500/fs=8k", "fc=200"};
372 static SOC_ENUM_SINGLE_DECL(max98088_dai1_dac_filter_enum,
373 M98088_REG_18_DAI1_FILTERS, 0,
374 max98088_dai1_fltr);
375 static SOC_ENUM_SINGLE_DECL(max98088_dai1_adc_filter_enum,
376 M98088_REG_18_DAI1_FILTERS, 4,
377 max98088_dai1_fltr);
378
379 static int max98088_mic1pre_set(struct snd_kcontrol *kcontrol,
380 struct snd_ctl_elem_value *ucontrol)
381 {
382 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
383 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
384 unsigned int sel = ucontrol->value.integer.value[0];
385
386 max98088->mic1pre = sel;
387 snd_soc_component_update_bits(component, M98088_REG_35_LVL_MIC1, M98088_MICPRE_MASK,
388 (1+sel)<<M98088_MICPRE_SHIFT);
389
390 return 0;
391 }
392
393 static int max98088_mic1pre_get(struct snd_kcontrol *kcontrol,
394 struct snd_ctl_elem_value *ucontrol)
395 {
396 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
397 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
398
399 ucontrol->value.integer.value[0] = max98088->mic1pre;
400 return 0;
401 }
402
403 static int max98088_mic2pre_set(struct snd_kcontrol *kcontrol,
404 struct snd_ctl_elem_value *ucontrol)
405 {
406 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
407 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
408 unsigned int sel = ucontrol->value.integer.value[0];
409
410 max98088->mic2pre = sel;
411 snd_soc_component_update_bits(component, M98088_REG_36_LVL_MIC2, M98088_MICPRE_MASK,
412 (1+sel)<<M98088_MICPRE_SHIFT);
413
414 return 0;
415 }
416
417 static int max98088_mic2pre_get(struct snd_kcontrol *kcontrol,
418 struct snd_ctl_elem_value *ucontrol)
419 {
420 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
421 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
422
423 ucontrol->value.integer.value[0] = max98088->mic2pre;
424 return 0;
425 }
426
427 static const DECLARE_TLV_DB_RANGE(max98088_micboost_tlv,
428 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
429 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
430 );
431
432 static const DECLARE_TLV_DB_RANGE(max98088_hp_tlv,
433 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
434 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
435 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
436 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
437 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
438 );
439
440 static const DECLARE_TLV_DB_RANGE(max98088_spk_tlv,
441 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
442 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
443 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
444 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
445 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
446 );
447
448 static const struct snd_kcontrol_new max98088_snd_controls[] = {
449
450 SOC_DOUBLE_R_TLV("Headphone Volume", M98088_REG_39_LVL_HP_L,
451 M98088_REG_3A_LVL_HP_R, 0, 31, 0, max98088_hp_tlv),
452 SOC_DOUBLE_R_TLV("Speaker Volume", M98088_REG_3D_LVL_SPK_L,
453 M98088_REG_3E_LVL_SPK_R, 0, 31, 0, max98088_spk_tlv),
454 SOC_DOUBLE_R_TLV("Receiver Volume", M98088_REG_3B_LVL_REC_L,
455 M98088_REG_3C_LVL_REC_R, 0, 31, 0, max98088_spk_tlv),
456
457 SOC_DOUBLE_R("Headphone Switch", M98088_REG_39_LVL_HP_L,
458 M98088_REG_3A_LVL_HP_R, 7, 1, 1),
459 SOC_DOUBLE_R("Speaker Switch", M98088_REG_3D_LVL_SPK_L,
460 M98088_REG_3E_LVL_SPK_R, 7, 1, 1),
461 SOC_DOUBLE_R("Receiver Switch", M98088_REG_3B_LVL_REC_L,
462 M98088_REG_3C_LVL_REC_R, 7, 1, 1),
463
464 SOC_SINGLE("MIC1 Volume", M98088_REG_35_LVL_MIC1, 0, 31, 1),
465 SOC_SINGLE("MIC2 Volume", M98088_REG_36_LVL_MIC2, 0, 31, 1),
466
467 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
468 M98088_REG_35_LVL_MIC1, 5, 2, 0,
469 max98088_mic1pre_get, max98088_mic1pre_set,
470 max98088_micboost_tlv),
471 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
472 M98088_REG_36_LVL_MIC2, 5, 2, 0,
473 max98088_mic2pre_get, max98088_mic2pre_set,
474 max98088_micboost_tlv),
475
476 SOC_SINGLE("INA Volume", M98088_REG_37_LVL_INA, 0, 7, 1),
477 SOC_SINGLE("INB Volume", M98088_REG_38_LVL_INB, 0, 7, 1),
478
479 SOC_SINGLE("ADCL Volume", M98088_REG_33_LVL_ADC_L, 0, 15, 0),
480 SOC_SINGLE("ADCR Volume", M98088_REG_34_LVL_ADC_R, 0, 15, 0),
481
482 SOC_SINGLE("ADCL Boost Volume", M98088_REG_33_LVL_ADC_L, 4, 3, 0),
483 SOC_SINGLE("ADCR Boost Volume", M98088_REG_34_LVL_ADC_R, 4, 3, 0),
484
485 SOC_SINGLE("EQ1 Switch", M98088_REG_49_CFG_LEVEL, 0, 1, 0),
486 SOC_SINGLE("EQ2 Switch", M98088_REG_49_CFG_LEVEL, 1, 1, 0),
487
488 SOC_ENUM("EX Limiter Mode", max98088_exmode_enum),
489 SOC_ENUM("EX Limiter Threshold", max98088_ex_thresh_enum),
490
491 SOC_ENUM("DAI1 Filter Mode", max98088_filter_mode_enum),
492 SOC_ENUM("DAI1 DAC Filter", max98088_dai1_dac_filter_enum),
493 SOC_ENUM("DAI1 ADC Filter", max98088_dai1_adc_filter_enum),
494 SOC_SINGLE("DAI2 DC Block Switch", M98088_REG_20_DAI2_FILTERS,
495 0, 1, 0),
496
497 SOC_SINGLE("ALC Switch", M98088_REG_43_SPKALC_COMP, 7, 1, 0),
498 SOC_SINGLE("ALC Threshold", M98088_REG_43_SPKALC_COMP, 0, 7, 0),
499 SOC_SINGLE("ALC Multiband", M98088_REG_43_SPKALC_COMP, 3, 1, 0),
500 SOC_SINGLE("ALC Release Time", M98088_REG_43_SPKALC_COMP, 4, 7, 0),
501
502 SOC_SINGLE("PWR Limiter Threshold", M98088_REG_44_PWRLMT_CFG,
503 4, 15, 0),
504 SOC_SINGLE("PWR Limiter Weight", M98088_REG_44_PWRLMT_CFG, 0, 7, 0),
505 SOC_SINGLE("PWR Limiter Time1", M98088_REG_45_PWRLMT_TIME, 0, 15, 0),
506 SOC_SINGLE("PWR Limiter Time2", M98088_REG_45_PWRLMT_TIME, 4, 15, 0),
507
508 SOC_SINGLE("THD Limiter Threshold", M98088_REG_46_THDLMT_CFG, 4, 15, 0),
509 SOC_SINGLE("THD Limiter Time", M98088_REG_46_THDLMT_CFG, 0, 7, 0),
510 };
511
512 /* Left speaker mixer switch */
513 static const struct snd_kcontrol_new max98088_left_speaker_mixer_controls[] = {
514 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
515 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
516 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
517 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
518 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 5, 1, 0),
519 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 6, 1, 0),
520 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 1, 1, 0),
521 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 2, 1, 0),
522 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 3, 1, 0),
523 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 4, 1, 0),
524 };
525
526 /* Right speaker mixer switch */
527 static const struct snd_kcontrol_new max98088_right_speaker_mixer_controls[] = {
528 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
529 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
530 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
531 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
532 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 5, 1, 0),
533 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 6, 1, 0),
534 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 1, 1, 0),
535 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 2, 1, 0),
536 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 3, 1, 0),
537 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 4, 1, 0),
538 };
539
540 /* Left headphone mixer switch */
541 static const struct snd_kcontrol_new max98088_left_hp_mixer_controls[] = {
542 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
543 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
544 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
545 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
546 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_25_MIX_HP_LEFT, 5, 1, 0),
547 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_25_MIX_HP_LEFT, 6, 1, 0),
548 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_25_MIX_HP_LEFT, 1, 1, 0),
549 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_25_MIX_HP_LEFT, 2, 1, 0),
550 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_25_MIX_HP_LEFT, 3, 1, 0),
551 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_25_MIX_HP_LEFT, 4, 1, 0),
552 };
553
554 /* Right headphone mixer switch */
555 static const struct snd_kcontrol_new max98088_right_hp_mixer_controls[] = {
556 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
557 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
558 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
559 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
560 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 5, 1, 0),
561 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 6, 1, 0),
562 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_26_MIX_HP_RIGHT, 1, 1, 0),
563 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_26_MIX_HP_RIGHT, 2, 1, 0),
564 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_26_MIX_HP_RIGHT, 3, 1, 0),
565 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_26_MIX_HP_RIGHT, 4, 1, 0),
566 };
567
568 /* Left earpiece/receiver mixer switch */
569 static const struct snd_kcontrol_new max98088_left_rec_mixer_controls[] = {
570 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
571 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
572 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
573 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
574 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_28_MIX_REC_LEFT, 5, 1, 0),
575 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_28_MIX_REC_LEFT, 6, 1, 0),
576 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_28_MIX_REC_LEFT, 1, 1, 0),
577 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_28_MIX_REC_LEFT, 2, 1, 0),
578 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_28_MIX_REC_LEFT, 3, 1, 0),
579 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_28_MIX_REC_LEFT, 4, 1, 0),
580 };
581
582 /* Right earpiece/receiver mixer switch */
583 static const struct snd_kcontrol_new max98088_right_rec_mixer_controls[] = {
584 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
585 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
586 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
587 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
588 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 5, 1, 0),
589 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 6, 1, 0),
590 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_29_MIX_REC_RIGHT, 1, 1, 0),
591 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_29_MIX_REC_RIGHT, 2, 1, 0),
592 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_29_MIX_REC_RIGHT, 3, 1, 0),
593 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_29_MIX_REC_RIGHT, 4, 1, 0),
594 };
595
596 /* Left ADC mixer switch */
597 static const struct snd_kcontrol_new max98088_left_ADC_mixer_controls[] = {
598 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_23_MIX_ADC_LEFT, 7, 1, 0),
599 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_23_MIX_ADC_LEFT, 6, 1, 0),
600 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_23_MIX_ADC_LEFT, 3, 1, 0),
601 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_23_MIX_ADC_LEFT, 2, 1, 0),
602 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_23_MIX_ADC_LEFT, 1, 1, 0),
603 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_23_MIX_ADC_LEFT, 0, 1, 0),
604 };
605
606 /* Right ADC mixer switch */
607 static const struct snd_kcontrol_new max98088_right_ADC_mixer_controls[] = {
608 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 7, 1, 0),
609 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 6, 1, 0),
610 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 3, 1, 0),
611 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 2, 1, 0),
612 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 1, 1, 0),
613 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 0, 1, 0),
614 };
615
616 static int max98088_mic_event(struct snd_soc_dapm_widget *w,
617 struct snd_kcontrol *kcontrol, int event)
618 {
619 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
620 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
621
622 switch (event) {
623 case SND_SOC_DAPM_POST_PMU:
624 if (w->reg == M98088_REG_35_LVL_MIC1) {
625 snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK,
626 (1+max98088->mic1pre)<<M98088_MICPRE_SHIFT);
627 } else {
628 snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK,
629 (1+max98088->mic2pre)<<M98088_MICPRE_SHIFT);
630 }
631 break;
632 case SND_SOC_DAPM_POST_PMD:
633 snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK, 0);
634 break;
635 default:
636 return -EINVAL;
637 }
638
639 return 0;
640 }
641
642 /*
643 * The line inputs are 2-channel stereo inputs with the left
644 * and right channels sharing a common PGA power control signal.
645 */
646 static int max98088_line_pga(struct snd_soc_dapm_widget *w,
647 int event, int line, u8 channel)
648 {
649 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
650 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
651 u8 *state;
652
653 if (WARN_ON(!(channel == 1 || channel == 2)))
654 return -EINVAL;
655
656 switch (line) {
657 case LINE_INA:
658 state = &max98088->ina_state;
659 break;
660 case LINE_INB:
661 state = &max98088->inb_state;
662 break;
663 default:
664 return -EINVAL;
665 }
666
667 switch (event) {
668 case SND_SOC_DAPM_POST_PMU:
669 *state |= channel;
670 snd_soc_component_update_bits(component, w->reg,
671 (1 << w->shift), (1 << w->shift));
672 break;
673 case SND_SOC_DAPM_POST_PMD:
674 *state &= ~channel;
675 if (*state == 0) {
676 snd_soc_component_update_bits(component, w->reg,
677 (1 << w->shift), 0);
678 }
679 break;
680 default:
681 return -EINVAL;
682 }
683
684 return 0;
685 }
686
687 static int max98088_pga_ina1_event(struct snd_soc_dapm_widget *w,
688 struct snd_kcontrol *k, int event)
689 {
690 return max98088_line_pga(w, event, LINE_INA, 1);
691 }
692
693 static int max98088_pga_ina2_event(struct snd_soc_dapm_widget *w,
694 struct snd_kcontrol *k, int event)
695 {
696 return max98088_line_pga(w, event, LINE_INA, 2);
697 }
698
699 static int max98088_pga_inb1_event(struct snd_soc_dapm_widget *w,
700 struct snd_kcontrol *k, int event)
701 {
702 return max98088_line_pga(w, event, LINE_INB, 1);
703 }
704
705 static int max98088_pga_inb2_event(struct snd_soc_dapm_widget *w,
706 struct snd_kcontrol *k, int event)
707 {
708 return max98088_line_pga(w, event, LINE_INB, 2);
709 }
710
711 static const struct snd_soc_dapm_widget max98088_dapm_widgets[] = {
712
713 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 1, 0),
714 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 0, 0),
715
716 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
717 M98088_REG_4D_PWR_EN_OUT, 1, 0),
718 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
719 M98088_REG_4D_PWR_EN_OUT, 0, 0),
720 SND_SOC_DAPM_DAC("DACL2", "Aux Playback",
721 M98088_REG_4D_PWR_EN_OUT, 1, 0),
722 SND_SOC_DAPM_DAC("DACR2", "Aux Playback",
723 M98088_REG_4D_PWR_EN_OUT, 0, 0),
724
725 SND_SOC_DAPM_PGA("HP Left Out", M98088_REG_4D_PWR_EN_OUT,
726 7, 0, NULL, 0),
727 SND_SOC_DAPM_PGA("HP Right Out", M98088_REG_4D_PWR_EN_OUT,
728 6, 0, NULL, 0),
729
730 SND_SOC_DAPM_PGA("SPK Left Out", M98088_REG_4D_PWR_EN_OUT,
731 5, 0, NULL, 0),
732 SND_SOC_DAPM_PGA("SPK Right Out", M98088_REG_4D_PWR_EN_OUT,
733 4, 0, NULL, 0),
734
735 SND_SOC_DAPM_PGA("REC Left Out", M98088_REG_4D_PWR_EN_OUT,
736 3, 0, NULL, 0),
737 SND_SOC_DAPM_PGA("REC Right Out", M98088_REG_4D_PWR_EN_OUT,
738 2, 0, NULL, 0),
739
740 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
741 &max98088_extmic_mux),
742
743 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
744 &max98088_left_hp_mixer_controls[0],
745 ARRAY_SIZE(max98088_left_hp_mixer_controls)),
746
747 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
748 &max98088_right_hp_mixer_controls[0],
749 ARRAY_SIZE(max98088_right_hp_mixer_controls)),
750
751 SND_SOC_DAPM_MIXER("Left SPK Mixer", SND_SOC_NOPM, 0, 0,
752 &max98088_left_speaker_mixer_controls[0],
753 ARRAY_SIZE(max98088_left_speaker_mixer_controls)),
754
755 SND_SOC_DAPM_MIXER("Right SPK Mixer", SND_SOC_NOPM, 0, 0,
756 &max98088_right_speaker_mixer_controls[0],
757 ARRAY_SIZE(max98088_right_speaker_mixer_controls)),
758
759 SND_SOC_DAPM_MIXER("Left REC Mixer", SND_SOC_NOPM, 0, 0,
760 &max98088_left_rec_mixer_controls[0],
761 ARRAY_SIZE(max98088_left_rec_mixer_controls)),
762
763 SND_SOC_DAPM_MIXER("Right REC Mixer", SND_SOC_NOPM, 0, 0,
764 &max98088_right_rec_mixer_controls[0],
765 ARRAY_SIZE(max98088_right_rec_mixer_controls)),
766
767 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
768 &max98088_left_ADC_mixer_controls[0],
769 ARRAY_SIZE(max98088_left_ADC_mixer_controls)),
770
771 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
772 &max98088_right_ADC_mixer_controls[0],
773 ARRAY_SIZE(max98088_right_ADC_mixer_controls)),
774
775 SND_SOC_DAPM_PGA_E("MIC1 Input", M98088_REG_35_LVL_MIC1,
776 5, 0, NULL, 0, max98088_mic_event,
777 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
778
779 SND_SOC_DAPM_PGA_E("MIC2 Input", M98088_REG_36_LVL_MIC2,
780 5, 0, NULL, 0, max98088_mic_event,
781 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
782
783 SND_SOC_DAPM_PGA_E("INA1 Input", M98088_REG_4C_PWR_EN_IN,
784 7, 0, NULL, 0, max98088_pga_ina1_event,
785 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
786
787 SND_SOC_DAPM_PGA_E("INA2 Input", M98088_REG_4C_PWR_EN_IN,
788 7, 0, NULL, 0, max98088_pga_ina2_event,
789 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
790
791 SND_SOC_DAPM_PGA_E("INB1 Input", M98088_REG_4C_PWR_EN_IN,
792 6, 0, NULL, 0, max98088_pga_inb1_event,
793 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
794
795 SND_SOC_DAPM_PGA_E("INB2 Input", M98088_REG_4C_PWR_EN_IN,
796 6, 0, NULL, 0, max98088_pga_inb2_event,
797 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
798
799 SND_SOC_DAPM_MICBIAS("MICBIAS", M98088_REG_4C_PWR_EN_IN, 3, 0),
800
801 SND_SOC_DAPM_OUTPUT("HPL"),
802 SND_SOC_DAPM_OUTPUT("HPR"),
803 SND_SOC_DAPM_OUTPUT("SPKL"),
804 SND_SOC_DAPM_OUTPUT("SPKR"),
805 SND_SOC_DAPM_OUTPUT("RECL"),
806 SND_SOC_DAPM_OUTPUT("RECR"),
807
808 SND_SOC_DAPM_INPUT("MIC1"),
809 SND_SOC_DAPM_INPUT("MIC2"),
810 SND_SOC_DAPM_INPUT("INA1"),
811 SND_SOC_DAPM_INPUT("INA2"),
812 SND_SOC_DAPM_INPUT("INB1"),
813 SND_SOC_DAPM_INPUT("INB2"),
814 };
815
816 static const struct snd_soc_dapm_route max98088_audio_map[] = {
817 /* Left headphone output mixer */
818 {"Left HP Mixer", "Left DAC1 Switch", "DACL1"},
819 {"Left HP Mixer", "Left DAC2 Switch", "DACL2"},
820 {"Left HP Mixer", "Right DAC1 Switch", "DACR1"},
821 {"Left HP Mixer", "Right DAC2 Switch", "DACR2"},
822 {"Left HP Mixer", "MIC1 Switch", "MIC1 Input"},
823 {"Left HP Mixer", "MIC2 Switch", "MIC2 Input"},
824 {"Left HP Mixer", "INA1 Switch", "INA1 Input"},
825 {"Left HP Mixer", "INA2 Switch", "INA2 Input"},
826 {"Left HP Mixer", "INB1 Switch", "INB1 Input"},
827 {"Left HP Mixer", "INB2 Switch", "INB2 Input"},
828
829 /* Right headphone output mixer */
830 {"Right HP Mixer", "Left DAC1 Switch", "DACL1"},
831 {"Right HP Mixer", "Left DAC2 Switch", "DACL2" },
832 {"Right HP Mixer", "Right DAC1 Switch", "DACR1"},
833 {"Right HP Mixer", "Right DAC2 Switch", "DACR2"},
834 {"Right HP Mixer", "MIC1 Switch", "MIC1 Input"},
835 {"Right HP Mixer", "MIC2 Switch", "MIC2 Input"},
836 {"Right HP Mixer", "INA1 Switch", "INA1 Input"},
837 {"Right HP Mixer", "INA2 Switch", "INA2 Input"},
838 {"Right HP Mixer", "INB1 Switch", "INB1 Input"},
839 {"Right HP Mixer", "INB2 Switch", "INB2 Input"},
840
841 /* Left speaker output mixer */
842 {"Left SPK Mixer", "Left DAC1 Switch", "DACL1"},
843 {"Left SPK Mixer", "Left DAC2 Switch", "DACL2"},
844 {"Left SPK Mixer", "Right DAC1 Switch", "DACR1"},
845 {"Left SPK Mixer", "Right DAC2 Switch", "DACR2"},
846 {"Left SPK Mixer", "MIC1 Switch", "MIC1 Input"},
847 {"Left SPK Mixer", "MIC2 Switch", "MIC2 Input"},
848 {"Left SPK Mixer", "INA1 Switch", "INA1 Input"},
849 {"Left SPK Mixer", "INA2 Switch", "INA2 Input"},
850 {"Left SPK Mixer", "INB1 Switch", "INB1 Input"},
851 {"Left SPK Mixer", "INB2 Switch", "INB2 Input"},
852
853 /* Right speaker output mixer */
854 {"Right SPK Mixer", "Left DAC1 Switch", "DACL1"},
855 {"Right SPK Mixer", "Left DAC2 Switch", "DACL2"},
856 {"Right SPK Mixer", "Right DAC1 Switch", "DACR1"},
857 {"Right SPK Mixer", "Right DAC2 Switch", "DACR2"},
858 {"Right SPK Mixer", "MIC1 Switch", "MIC1 Input"},
859 {"Right SPK Mixer", "MIC2 Switch", "MIC2 Input"},
860 {"Right SPK Mixer", "INA1 Switch", "INA1 Input"},
861 {"Right SPK Mixer", "INA2 Switch", "INA2 Input"},
862 {"Right SPK Mixer", "INB1 Switch", "INB1 Input"},
863 {"Right SPK Mixer", "INB2 Switch", "INB2 Input"},
864
865 /* Earpiece/Receiver output mixer */
866 {"Left REC Mixer", "Left DAC1 Switch", "DACL1"},
867 {"Left REC Mixer", "Left DAC2 Switch", "DACL2"},
868 {"Left REC Mixer", "Right DAC1 Switch", "DACR1"},
869 {"Left REC Mixer", "Right DAC2 Switch", "DACR2"},
870 {"Left REC Mixer", "MIC1 Switch", "MIC1 Input"},
871 {"Left REC Mixer", "MIC2 Switch", "MIC2 Input"},
872 {"Left REC Mixer", "INA1 Switch", "INA1 Input"},
873 {"Left REC Mixer", "INA2 Switch", "INA2 Input"},
874 {"Left REC Mixer", "INB1 Switch", "INB1 Input"},
875 {"Left REC Mixer", "INB2 Switch", "INB2 Input"},
876
877 /* Earpiece/Receiver output mixer */
878 {"Right REC Mixer", "Left DAC1 Switch", "DACL1"},
879 {"Right REC Mixer", "Left DAC2 Switch", "DACL2"},
880 {"Right REC Mixer", "Right DAC1 Switch", "DACR1"},
881 {"Right REC Mixer", "Right DAC2 Switch", "DACR2"},
882 {"Right REC Mixer", "MIC1 Switch", "MIC1 Input"},
883 {"Right REC Mixer", "MIC2 Switch", "MIC2 Input"},
884 {"Right REC Mixer", "INA1 Switch", "INA1 Input"},
885 {"Right REC Mixer", "INA2 Switch", "INA2 Input"},
886 {"Right REC Mixer", "INB1 Switch", "INB1 Input"},
887 {"Right REC Mixer", "INB2 Switch", "INB2 Input"},
888
889 {"HP Left Out", NULL, "Left HP Mixer"},
890 {"HP Right Out", NULL, "Right HP Mixer"},
891 {"SPK Left Out", NULL, "Left SPK Mixer"},
892 {"SPK Right Out", NULL, "Right SPK Mixer"},
893 {"REC Left Out", NULL, "Left REC Mixer"},
894 {"REC Right Out", NULL, "Right REC Mixer"},
895
896 {"HPL", NULL, "HP Left Out"},
897 {"HPR", NULL, "HP Right Out"},
898 {"SPKL", NULL, "SPK Left Out"},
899 {"SPKR", NULL, "SPK Right Out"},
900 {"RECL", NULL, "REC Left Out"},
901 {"RECR", NULL, "REC Right Out"},
902
903 /* Left ADC input mixer */
904 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
905 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
906 {"Left ADC Mixer", "INA1 Switch", "INA1 Input"},
907 {"Left ADC Mixer", "INA2 Switch", "INA2 Input"},
908 {"Left ADC Mixer", "INB1 Switch", "INB1 Input"},
909 {"Left ADC Mixer", "INB2 Switch", "INB2 Input"},
910
911 /* Right ADC input mixer */
912 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
913 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
914 {"Right ADC Mixer", "INA1 Switch", "INA1 Input"},
915 {"Right ADC Mixer", "INA2 Switch", "INA2 Input"},
916 {"Right ADC Mixer", "INB1 Switch", "INB1 Input"},
917 {"Right ADC Mixer", "INB2 Switch", "INB2 Input"},
918
919 /* Inputs */
920 {"ADCL", NULL, "Left ADC Mixer"},
921 {"ADCR", NULL, "Right ADC Mixer"},
922 {"INA1 Input", NULL, "INA1"},
923 {"INA2 Input", NULL, "INA2"},
924 {"INB1 Input", NULL, "INB1"},
925 {"INB2 Input", NULL, "INB2"},
926 {"MIC1 Input", NULL, "MIC1"},
927 {"MIC2 Input", NULL, "MIC2"},
928 };
929
930 /* codec mclk clock divider coefficients */
931 static const struct {
932 u32 rate;
933 u8 sr;
934 } rate_table[] = {
935 {8000, 0x10},
936 {11025, 0x20},
937 {16000, 0x30},
938 {22050, 0x40},
939 {24000, 0x50},
940 {32000, 0x60},
941 {44100, 0x70},
942 {48000, 0x80},
943 {88200, 0x90},
944 {96000, 0xA0},
945 };
946
947 static inline int rate_value(int rate, u8 *value)
948 {
949 int i;
950
951 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
952 if (rate_table[i].rate >= rate) {
953 *value = rate_table[i].sr;
954 return 0;
955 }
956 }
957 *value = rate_table[0].sr;
958 return -EINVAL;
959 }
960
961 static int max98088_dai1_hw_params(struct snd_pcm_substream *substream,
962 struct snd_pcm_hw_params *params,
963 struct snd_soc_dai *dai)
964 {
965 struct snd_soc_component *component = dai->component;
966 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
967 struct max98088_cdata *cdata;
968 unsigned long long ni;
969 unsigned int rate;
970 u8 regval;
971
972 cdata = &max98088->dai[0];
973
974 rate = params_rate(params);
975
976 switch (params_width(params)) {
977 case 16:
978 snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT,
979 M98088_DAI_WS, 0);
980 break;
981 case 24:
982 snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT,
983 M98088_DAI_WS, M98088_DAI_WS);
984 break;
985 default:
986 return -EINVAL;
987 }
988
989 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
990
991 if (rate_value(rate, &regval))
992 return -EINVAL;
993
994 snd_soc_component_update_bits(component, M98088_REG_11_DAI1_CLKMODE,
995 M98088_CLKMODE_MASK, regval);
996 cdata->rate = rate;
997
998 /* Configure NI when operating as master */
999 if (snd_soc_component_read32(component, M98088_REG_14_DAI1_FORMAT)
1000 & M98088_DAI_MAS) {
1001 if (max98088->sysclk == 0) {
1002 dev_err(component->dev, "Invalid system clock frequency\n");
1003 return -EINVAL;
1004 }
1005 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1006 * (unsigned long long int)rate;
1007 do_div(ni, (unsigned long long int)max98088->sysclk);
1008 snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI,
1009 (ni >> 8) & 0x7F);
1010 snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO,
1011 ni & 0xFF);
1012 }
1013
1014 /* Update sample rate mode */
1015 if (rate < 50000)
1016 snd_soc_component_update_bits(component, M98088_REG_18_DAI1_FILTERS,
1017 M98088_DAI_DHF, 0);
1018 else
1019 snd_soc_component_update_bits(component, M98088_REG_18_DAI1_FILTERS,
1020 M98088_DAI_DHF, M98088_DAI_DHF);
1021
1022 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
1023 M98088_SHDNRUN);
1024
1025 return 0;
1026 }
1027
1028 static int max98088_dai2_hw_params(struct snd_pcm_substream *substream,
1029 struct snd_pcm_hw_params *params,
1030 struct snd_soc_dai *dai)
1031 {
1032 struct snd_soc_component *component = dai->component;
1033 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1034 struct max98088_cdata *cdata;
1035 unsigned long long ni;
1036 unsigned int rate;
1037 u8 regval;
1038
1039 cdata = &max98088->dai[1];
1040
1041 rate = params_rate(params);
1042
1043 switch (params_width(params)) {
1044 case 16:
1045 snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT,
1046 M98088_DAI_WS, 0);
1047 break;
1048 case 24:
1049 snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT,
1050 M98088_DAI_WS, M98088_DAI_WS);
1051 break;
1052 default:
1053 return -EINVAL;
1054 }
1055
1056 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
1057
1058 if (rate_value(rate, &regval))
1059 return -EINVAL;
1060
1061 snd_soc_component_update_bits(component, M98088_REG_19_DAI2_CLKMODE,
1062 M98088_CLKMODE_MASK, regval);
1063 cdata->rate = rate;
1064
1065 /* Configure NI when operating as master */
1066 if (snd_soc_component_read32(component, M98088_REG_1C_DAI2_FORMAT)
1067 & M98088_DAI_MAS) {
1068 if (max98088->sysclk == 0) {
1069 dev_err(component->dev, "Invalid system clock frequency\n");
1070 return -EINVAL;
1071 }
1072 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1073 * (unsigned long long int)rate;
1074 do_div(ni, (unsigned long long int)max98088->sysclk);
1075 snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI,
1076 (ni >> 8) & 0x7F);
1077 snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO,
1078 ni & 0xFF);
1079 }
1080
1081 /* Update sample rate mode */
1082 if (rate < 50000)
1083 snd_soc_component_update_bits(component, M98088_REG_20_DAI2_FILTERS,
1084 M98088_DAI_DHF, 0);
1085 else
1086 snd_soc_component_update_bits(component, M98088_REG_20_DAI2_FILTERS,
1087 M98088_DAI_DHF, M98088_DAI_DHF);
1088
1089 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
1090 M98088_SHDNRUN);
1091
1092 return 0;
1093 }
1094
1095 static int max98088_dai_set_sysclk(struct snd_soc_dai *dai,
1096 int clk_id, unsigned int freq, int dir)
1097 {
1098 struct snd_soc_component *component = dai->component;
1099 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1100
1101 /* Requested clock frequency is already setup */
1102 if (freq == max98088->sysclk)
1103 return 0;
1104
1105 if (!IS_ERR(max98088->mclk)) {
1106 freq = clk_round_rate(max98088->mclk, freq);
1107 clk_set_rate(max98088->mclk, freq);
1108 }
1109
1110 /* Setup clocks for slave mode, and using the PLL
1111 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1112 * 0x02 (when master clk is 20MHz to 30MHz)..
1113 */
1114 if ((freq >= 10000000) && (freq < 20000000)) {
1115 snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x10);
1116 } else if ((freq >= 20000000) && (freq < 30000000)) {
1117 snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x20);
1118 } else {
1119 dev_err(component->dev, "Invalid master clock frequency\n");
1120 return -EINVAL;
1121 }
1122
1123 if (snd_soc_component_read32(component, M98088_REG_51_PWR_SYS) & M98088_SHDNRUN) {
1124 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS,
1125 M98088_SHDNRUN, 0);
1126 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS,
1127 M98088_SHDNRUN, M98088_SHDNRUN);
1128 }
1129
1130 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1131
1132 max98088->sysclk = freq;
1133 return 0;
1134 }
1135
1136 static int max98088_dai1_set_fmt(struct snd_soc_dai *codec_dai,
1137 unsigned int fmt)
1138 {
1139 struct snd_soc_component *component = codec_dai->component;
1140 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1141 struct max98088_cdata *cdata;
1142 u8 reg15val;
1143 u8 reg14val = 0;
1144
1145 cdata = &max98088->dai[0];
1146
1147 if (fmt != cdata->fmt) {
1148 cdata->fmt = fmt;
1149
1150 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1151 case SND_SOC_DAIFMT_CBS_CFS:
1152 /* Slave mode PLL */
1153 snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI,
1154 0x80);
1155 snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO,
1156 0x00);
1157 break;
1158 case SND_SOC_DAIFMT_CBM_CFM:
1159 /* Set to master mode */
1160 reg14val |= M98088_DAI_MAS;
1161 break;
1162 case SND_SOC_DAIFMT_CBS_CFM:
1163 case SND_SOC_DAIFMT_CBM_CFS:
1164 default:
1165 dev_err(component->dev, "Clock mode unsupported");
1166 return -EINVAL;
1167 }
1168
1169 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1170 case SND_SOC_DAIFMT_I2S:
1171 reg14val |= M98088_DAI_DLY;
1172 break;
1173 case SND_SOC_DAIFMT_LEFT_J:
1174 break;
1175 default:
1176 return -EINVAL;
1177 }
1178
1179 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1180 case SND_SOC_DAIFMT_NB_NF:
1181 break;
1182 case SND_SOC_DAIFMT_NB_IF:
1183 reg14val |= M98088_DAI_WCI;
1184 break;
1185 case SND_SOC_DAIFMT_IB_NF:
1186 reg14val |= M98088_DAI_BCI;
1187 break;
1188 case SND_SOC_DAIFMT_IB_IF:
1189 reg14val |= M98088_DAI_BCI|M98088_DAI_WCI;
1190 break;
1191 default:
1192 return -EINVAL;
1193 }
1194
1195 snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT,
1196 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
1197 M98088_DAI_WCI, reg14val);
1198
1199 reg15val = M98088_DAI_BSEL64;
1200 if (max98088->digmic)
1201 reg15val |= M98088_DAI_OSR64;
1202 snd_soc_component_write(component, M98088_REG_15_DAI1_CLOCK, reg15val);
1203 }
1204
1205 return 0;
1206 }
1207
1208 static int max98088_dai2_set_fmt(struct snd_soc_dai *codec_dai,
1209 unsigned int fmt)
1210 {
1211 struct snd_soc_component *component = codec_dai->component;
1212 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1213 struct max98088_cdata *cdata;
1214 u8 reg1Cval = 0;
1215
1216 cdata = &max98088->dai[1];
1217
1218 if (fmt != cdata->fmt) {
1219 cdata->fmt = fmt;
1220
1221 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1222 case SND_SOC_DAIFMT_CBS_CFS:
1223 /* Slave mode PLL */
1224 snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI,
1225 0x80);
1226 snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO,
1227 0x00);
1228 break;
1229 case SND_SOC_DAIFMT_CBM_CFM:
1230 /* Set to master mode */
1231 reg1Cval |= M98088_DAI_MAS;
1232 break;
1233 case SND_SOC_DAIFMT_CBS_CFM:
1234 case SND_SOC_DAIFMT_CBM_CFS:
1235 default:
1236 dev_err(component->dev, "Clock mode unsupported");
1237 return -EINVAL;
1238 }
1239
1240 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1241 case SND_SOC_DAIFMT_I2S:
1242 reg1Cval |= M98088_DAI_DLY;
1243 break;
1244 case SND_SOC_DAIFMT_LEFT_J:
1245 break;
1246 default:
1247 return -EINVAL;
1248 }
1249
1250 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1251 case SND_SOC_DAIFMT_NB_NF:
1252 break;
1253 case SND_SOC_DAIFMT_NB_IF:
1254 reg1Cval |= M98088_DAI_WCI;
1255 break;
1256 case SND_SOC_DAIFMT_IB_NF:
1257 reg1Cval |= M98088_DAI_BCI;
1258 break;
1259 case SND_SOC_DAIFMT_IB_IF:
1260 reg1Cval |= M98088_DAI_BCI|M98088_DAI_WCI;
1261 break;
1262 default:
1263 return -EINVAL;
1264 }
1265
1266 snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT,
1267 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
1268 M98088_DAI_WCI, reg1Cval);
1269
1270 snd_soc_component_write(component, M98088_REG_1D_DAI2_CLOCK,
1271 M98088_DAI_BSEL64);
1272 }
1273
1274 return 0;
1275 }
1276
1277 static int max98088_dai1_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1278 {
1279 struct snd_soc_component *component = codec_dai->component;
1280 int reg;
1281
1282 if (mute)
1283 reg = M98088_DAI_MUTE;
1284 else
1285 reg = 0;
1286
1287 snd_soc_component_update_bits(component, M98088_REG_2F_LVL_DAI1_PLAY,
1288 M98088_DAI_MUTE_MASK, reg);
1289 return 0;
1290 }
1291
1292 static int max98088_dai2_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1293 {
1294 struct snd_soc_component *component = codec_dai->component;
1295 int reg;
1296
1297 if (mute)
1298 reg = M98088_DAI_MUTE;
1299 else
1300 reg = 0;
1301
1302 snd_soc_component_update_bits(component, M98088_REG_31_LVL_DAI2_PLAY,
1303 M98088_DAI_MUTE_MASK, reg);
1304 return 0;
1305 }
1306
1307 static int max98088_set_bias_level(struct snd_soc_component *component,
1308 enum snd_soc_bias_level level)
1309 {
1310 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1311
1312 switch (level) {
1313 case SND_SOC_BIAS_ON:
1314 break;
1315
1316 case SND_SOC_BIAS_PREPARE:
1317 /*
1318 * SND_SOC_BIAS_PREPARE is called while preparing for a
1319 * transition to ON or away from ON. If current bias_level
1320 * is SND_SOC_BIAS_ON, then it is preparing for a transition
1321 * away from ON. Disable the clock in that case, otherwise
1322 * enable it.
1323 */
1324 if (!IS_ERR(max98088->mclk)) {
1325 if (snd_soc_component_get_bias_level(component) ==
1326 SND_SOC_BIAS_ON)
1327 clk_disable_unprepare(max98088->mclk);
1328 else
1329 clk_prepare_enable(max98088->mclk);
1330 }
1331 break;
1332
1333 case SND_SOC_BIAS_STANDBY:
1334 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
1335 regcache_sync(max98088->regmap);
1336
1337 snd_soc_component_update_bits(component, M98088_REG_4C_PWR_EN_IN,
1338 M98088_MBEN, M98088_MBEN);
1339 break;
1340
1341 case SND_SOC_BIAS_OFF:
1342 snd_soc_component_update_bits(component, M98088_REG_4C_PWR_EN_IN,
1343 M98088_MBEN, 0);
1344 regcache_mark_dirty(max98088->regmap);
1345 break;
1346 }
1347 return 0;
1348 }
1349
1350 #define MAX98088_RATES SNDRV_PCM_RATE_8000_96000
1351 #define MAX98088_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1352
1353 static const struct snd_soc_dai_ops max98088_dai1_ops = {
1354 .set_sysclk = max98088_dai_set_sysclk,
1355 .set_fmt = max98088_dai1_set_fmt,
1356 .hw_params = max98088_dai1_hw_params,
1357 .digital_mute = max98088_dai1_digital_mute,
1358 };
1359
1360 static const struct snd_soc_dai_ops max98088_dai2_ops = {
1361 .set_sysclk = max98088_dai_set_sysclk,
1362 .set_fmt = max98088_dai2_set_fmt,
1363 .hw_params = max98088_dai2_hw_params,
1364 .digital_mute = max98088_dai2_digital_mute,
1365 };
1366
1367 static struct snd_soc_dai_driver max98088_dai[] = {
1368 {
1369 .name = "HiFi",
1370 .playback = {
1371 .stream_name = "HiFi Playback",
1372 .channels_min = 1,
1373 .channels_max = 2,
1374 .rates = MAX98088_RATES,
1375 .formats = MAX98088_FORMATS,
1376 },
1377 .capture = {
1378 .stream_name = "HiFi Capture",
1379 .channels_min = 1,
1380 .channels_max = 2,
1381 .rates = MAX98088_RATES,
1382 .formats = MAX98088_FORMATS,
1383 },
1384 .ops = &max98088_dai1_ops,
1385 },
1386 {
1387 .name = "Aux",
1388 .playback = {
1389 .stream_name = "Aux Playback",
1390 .channels_min = 1,
1391 .channels_max = 2,
1392 .rates = MAX98088_RATES,
1393 .formats = MAX98088_FORMATS,
1394 },
1395 .ops = &max98088_dai2_ops,
1396 }
1397 };
1398
1399 static const char *eq_mode_name[] = {"EQ1 Mode", "EQ2 Mode"};
1400
1401 static int max98088_get_channel(struct snd_soc_component *component, const char *name)
1402 {
1403 int ret;
1404
1405 ret = match_string(eq_mode_name, ARRAY_SIZE(eq_mode_name), name);
1406 if (ret < 0)
1407 dev_err(component->dev, "Bad EQ channel name '%s'\n", name);
1408 return ret;
1409 }
1410
1411 static void max98088_setup_eq1(struct snd_soc_component *component)
1412 {
1413 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1414 struct max98088_pdata *pdata = max98088->pdata;
1415 struct max98088_eq_cfg *coef_set;
1416 int best, best_val, save, i, sel, fs;
1417 struct max98088_cdata *cdata;
1418
1419 cdata = &max98088->dai[0];
1420
1421 if (!pdata || !max98088->eq_textcnt)
1422 return;
1423
1424 /* Find the selected configuration with nearest sample rate */
1425 fs = cdata->rate;
1426 sel = cdata->eq_sel;
1427
1428 best = 0;
1429 best_val = INT_MAX;
1430 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1431 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
1432 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1433 best = i;
1434 best_val = abs(pdata->eq_cfg[i].rate - fs);
1435 }
1436 }
1437
1438 dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
1439 pdata->eq_cfg[best].name,
1440 pdata->eq_cfg[best].rate, fs);
1441
1442 /* Disable EQ while configuring, and save current on/off state */
1443 save = snd_soc_component_read32(component, M98088_REG_49_CFG_LEVEL);
1444 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0);
1445
1446 coef_set = &pdata->eq_cfg[sel];
1447
1448 m98088_eq_band(component, 0, 0, coef_set->band1);
1449 m98088_eq_band(component, 0, 1, coef_set->band2);
1450 m98088_eq_band(component, 0, 2, coef_set->band3);
1451 m98088_eq_band(component, 0, 3, coef_set->band4);
1452 m98088_eq_band(component, 0, 4, coef_set->band5);
1453
1454 /* Restore the original on/off state */
1455 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, save);
1456 }
1457
1458 static void max98088_setup_eq2(struct snd_soc_component *component)
1459 {
1460 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1461 struct max98088_pdata *pdata = max98088->pdata;
1462 struct max98088_eq_cfg *coef_set;
1463 int best, best_val, save, i, sel, fs;
1464 struct max98088_cdata *cdata;
1465
1466 cdata = &max98088->dai[1];
1467
1468 if (!pdata || !max98088->eq_textcnt)
1469 return;
1470
1471 /* Find the selected configuration with nearest sample rate */
1472 fs = cdata->rate;
1473
1474 sel = cdata->eq_sel;
1475 best = 0;
1476 best_val = INT_MAX;
1477 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1478 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
1479 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1480 best = i;
1481 best_val = abs(pdata->eq_cfg[i].rate - fs);
1482 }
1483 }
1484
1485 dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
1486 pdata->eq_cfg[best].name,
1487 pdata->eq_cfg[best].rate, fs);
1488
1489 /* Disable EQ while configuring, and save current on/off state */
1490 save = snd_soc_component_read32(component, M98088_REG_49_CFG_LEVEL);
1491 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0);
1492
1493 coef_set = &pdata->eq_cfg[sel];
1494
1495 m98088_eq_band(component, 1, 0, coef_set->band1);
1496 m98088_eq_band(component, 1, 1, coef_set->band2);
1497 m98088_eq_band(component, 1, 2, coef_set->band3);
1498 m98088_eq_band(component, 1, 3, coef_set->band4);
1499 m98088_eq_band(component, 1, 4, coef_set->band5);
1500
1501 /* Restore the original on/off state */
1502 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN,
1503 save);
1504 }
1505
1506 static int max98088_put_eq_enum(struct snd_kcontrol *kcontrol,
1507 struct snd_ctl_elem_value *ucontrol)
1508 {
1509 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1510 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1511 struct max98088_pdata *pdata = max98088->pdata;
1512 int channel = max98088_get_channel(component, kcontrol->id.name);
1513 struct max98088_cdata *cdata;
1514 int sel = ucontrol->value.enumerated.item[0];
1515
1516 if (channel < 0)
1517 return channel;
1518
1519 cdata = &max98088->dai[channel];
1520
1521 if (sel >= pdata->eq_cfgcnt)
1522 return -EINVAL;
1523
1524 cdata->eq_sel = sel;
1525
1526 switch (channel) {
1527 case 0:
1528 max98088_setup_eq1(component);
1529 break;
1530 case 1:
1531 max98088_setup_eq2(component);
1532 break;
1533 }
1534
1535 return 0;
1536 }
1537
1538 static int max98088_get_eq_enum(struct snd_kcontrol *kcontrol,
1539 struct snd_ctl_elem_value *ucontrol)
1540 {
1541 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1542 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1543 int channel = max98088_get_channel(component, kcontrol->id.name);
1544 struct max98088_cdata *cdata;
1545
1546 if (channel < 0)
1547 return channel;
1548
1549 cdata = &max98088->dai[channel];
1550 ucontrol->value.enumerated.item[0] = cdata->eq_sel;
1551 return 0;
1552 }
1553
1554 static void max98088_handle_eq_pdata(struct snd_soc_component *component)
1555 {
1556 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1557 struct max98088_pdata *pdata = max98088->pdata;
1558 struct max98088_eq_cfg *cfg;
1559 unsigned int cfgcnt;
1560 int i, j;
1561 const char **t;
1562 int ret;
1563 struct snd_kcontrol_new controls[] = {
1564 SOC_ENUM_EXT((char *)eq_mode_name[0],
1565 max98088->eq_enum,
1566 max98088_get_eq_enum,
1567 max98088_put_eq_enum),
1568 SOC_ENUM_EXT((char *)eq_mode_name[1],
1569 max98088->eq_enum,
1570 max98088_get_eq_enum,
1571 max98088_put_eq_enum),
1572 };
1573 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(eq_mode_name));
1574
1575 cfg = pdata->eq_cfg;
1576 cfgcnt = pdata->eq_cfgcnt;
1577
1578 /* Setup an array of texts for the equalizer enum.
1579 * This is based on Mark Brown's equalizer driver code.
1580 */
1581 max98088->eq_textcnt = 0;
1582 max98088->eq_texts = NULL;
1583 for (i = 0; i < cfgcnt; i++) {
1584 for (j = 0; j < max98088->eq_textcnt; j++) {
1585 if (strcmp(cfg[i].name, max98088->eq_texts[j]) == 0)
1586 break;
1587 }
1588
1589 if (j != max98088->eq_textcnt)
1590 continue;
1591
1592 /* Expand the array */
1593 t = krealloc(max98088->eq_texts,
1594 sizeof(char *) * (max98088->eq_textcnt + 1),
1595 GFP_KERNEL);
1596 if (t == NULL)
1597 continue;
1598
1599 /* Store the new entry */
1600 t[max98088->eq_textcnt] = cfg[i].name;
1601 max98088->eq_textcnt++;
1602 max98088->eq_texts = t;
1603 }
1604
1605 /* Now point the soc_enum to .texts array items */
1606 max98088->eq_enum.texts = max98088->eq_texts;
1607 max98088->eq_enum.items = max98088->eq_textcnt;
1608
1609 ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls));
1610 if (ret != 0)
1611 dev_err(component->dev, "Failed to add EQ control: %d\n", ret);
1612 }
1613
1614 static void max98088_handle_pdata(struct snd_soc_component *component)
1615 {
1616 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1617 struct max98088_pdata *pdata = max98088->pdata;
1618 u8 regval = 0;
1619
1620 if (!pdata) {
1621 dev_dbg(component->dev, "No platform data\n");
1622 return;
1623 }
1624
1625 /* Configure mic for analog/digital mic mode */
1626 if (pdata->digmic_left_mode)
1627 regval |= M98088_DIGMIC_L;
1628
1629 if (pdata->digmic_right_mode)
1630 regval |= M98088_DIGMIC_R;
1631
1632 max98088->digmic = (regval ? 1 : 0);
1633
1634 snd_soc_component_write(component, M98088_REG_48_CFG_MIC, regval);
1635
1636 /* Configure receiver output */
1637 regval = ((pdata->receiver_mode) ? M98088_REC_LINEMODE : 0);
1638 snd_soc_component_update_bits(component, M98088_REG_2A_MIC_REC_CNTL,
1639 M98088_REC_LINEMODE_MASK, regval);
1640
1641 /* Configure equalizers */
1642 if (pdata->eq_cfgcnt)
1643 max98088_handle_eq_pdata(component);
1644 }
1645
1646 static int max98088_probe(struct snd_soc_component *component)
1647 {
1648 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1649 struct max98088_cdata *cdata;
1650 int ret = 0;
1651
1652 regcache_mark_dirty(max98088->regmap);
1653
1654 /* initialize private data */
1655
1656 max98088->sysclk = (unsigned)-1;
1657 max98088->eq_textcnt = 0;
1658
1659 cdata = &max98088->dai[0];
1660 cdata->rate = (unsigned)-1;
1661 cdata->fmt = (unsigned)-1;
1662 cdata->eq_sel = 0;
1663
1664 cdata = &max98088->dai[1];
1665 cdata->rate = (unsigned)-1;
1666 cdata->fmt = (unsigned)-1;
1667 cdata->eq_sel = 0;
1668
1669 max98088->ina_state = 0;
1670 max98088->inb_state = 0;
1671 max98088->ex_mode = 0;
1672 max98088->digmic = 0;
1673 max98088->mic1pre = 0;
1674 max98088->mic2pre = 0;
1675
1676 ret = snd_soc_component_read32(component, M98088_REG_FF_REV_ID);
1677 if (ret < 0) {
1678 dev_err(component->dev, "Failed to read device revision: %d\n",
1679 ret);
1680 goto err_access;
1681 }
1682 dev_info(component->dev, "revision %c\n", ret - 0x40 + 'A');
1683
1684 snd_soc_component_write(component, M98088_REG_51_PWR_SYS, M98088_PWRSV);
1685
1686 snd_soc_component_write(component, M98088_REG_0F_IRQ_ENABLE, 0x00);
1687
1688 snd_soc_component_write(component, M98088_REG_22_MIX_DAC,
1689 M98088_DAI1L_TO_DACL|M98088_DAI2L_TO_DACL|
1690 M98088_DAI1R_TO_DACR|M98088_DAI2R_TO_DACR);
1691
1692 snd_soc_component_write(component, M98088_REG_4E_BIAS_CNTL, 0xF0);
1693 snd_soc_component_write(component, M98088_REG_50_DAC_BIAS2, 0x0F);
1694
1695 snd_soc_component_write(component, M98088_REG_16_DAI1_IOCFG,
1696 M98088_S1NORMAL|M98088_SDATA);
1697
1698 snd_soc_component_write(component, M98088_REG_1E_DAI2_IOCFG,
1699 M98088_S2NORMAL|M98088_SDATA);
1700
1701 max98088_handle_pdata(component);
1702
1703 err_access:
1704 return ret;
1705 }
1706
1707 static void max98088_remove(struct snd_soc_component *component)
1708 {
1709 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1710
1711 kfree(max98088->eq_texts);
1712 }
1713
1714 static const struct snd_soc_component_driver soc_component_dev_max98088 = {
1715 .probe = max98088_probe,
1716 .remove = max98088_remove,
1717 .set_bias_level = max98088_set_bias_level,
1718 .controls = max98088_snd_controls,
1719 .num_controls = ARRAY_SIZE(max98088_snd_controls),
1720 .dapm_widgets = max98088_dapm_widgets,
1721 .num_dapm_widgets = ARRAY_SIZE(max98088_dapm_widgets),
1722 .dapm_routes = max98088_audio_map,
1723 .num_dapm_routes = ARRAY_SIZE(max98088_audio_map),
1724 .suspend_bias_off = 1,
1725 .idle_bias_on = 1,
1726 .use_pmdown_time = 1,
1727 .endianness = 1,
1728 .non_legacy_dai_naming = 1,
1729 };
1730
1731 static int max98088_i2c_probe(struct i2c_client *i2c,
1732 const struct i2c_device_id *id)
1733 {
1734 struct max98088_priv *max98088;
1735 int ret;
1736
1737 max98088 = devm_kzalloc(&i2c->dev, sizeof(struct max98088_priv),
1738 GFP_KERNEL);
1739 if (max98088 == NULL)
1740 return -ENOMEM;
1741
1742 max98088->regmap = devm_regmap_init_i2c(i2c, &max98088_regmap);
1743 if (IS_ERR(max98088->regmap))
1744 return PTR_ERR(max98088->regmap);
1745
1746 max98088->mclk = devm_clk_get(&i2c->dev, "mclk");
1747 if (IS_ERR(max98088->mclk))
1748 if (PTR_ERR(max98088->mclk) == -EPROBE_DEFER)
1749 return PTR_ERR(max98088->mclk);
1750
1751 max98088->devtype = id->driver_data;
1752
1753 i2c_set_clientdata(i2c, max98088);
1754 max98088->pdata = i2c->dev.platform_data;
1755
1756 ret = devm_snd_soc_register_component(&i2c->dev,
1757 &soc_component_dev_max98088, &max98088_dai[0], 2);
1758 return ret;
1759 }
1760
1761 static const struct i2c_device_id max98088_i2c_id[] = {
1762 { "max98088", MAX98088 },
1763 { "max98089", MAX98089 },
1764 { }
1765 };
1766 MODULE_DEVICE_TABLE(i2c, max98088_i2c_id);
1767
1768 #if defined(CONFIG_OF)
1769 static const struct of_device_id max98088_of_match[] = {
1770 { .compatible = "maxim,max98088" },
1771 { .compatible = "maxim,max98089" },
1772 { }
1773 };
1774 MODULE_DEVICE_TABLE(of, max98088_of_match);
1775 #endif
1776
1777 static struct i2c_driver max98088_i2c_driver = {
1778 .driver = {
1779 .name = "max98088",
1780 .of_match_table = of_match_ptr(max98088_of_match),
1781 },
1782 .probe = max98088_i2c_probe,
1783 .id_table = max98088_i2c_id,
1784 };
1785
1786 module_i2c_driver(max98088_i2c_driver);
1787
1788 MODULE_DESCRIPTION("ALSA SoC MAX98088 driver");
1789 MODULE_AUTHOR("Peter Hsiang, Jesse Marroquin");
1790 MODULE_LICENSE("GPL");
Linux with added FPC-III support