sound/soc/codecs/nau8540.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * NAU85L40 ALSA SoC audio driver
   4  *
   5  * Copyright 2016 Nuvoton Technology Corp.
   6  * Author: John Hsu <KCHSU0@nuvoton.com>
   7  */
   8
   9 #ifndef __NAU8540_H__
  10 #define __NAU8540_H__
  11
  12 #define NAU8540_REG_SW_RESET                    0x00
  13 #define NAU8540_REG_POWER_MANAGEMENT    0x01
  14 #define NAU8540_REG_CLOCK_CTRL          0x02
  15 #define NAU8540_REG_CLOCK_SRC                   0x03
  16 #define NAU8540_REG_FLL1                        0x04
  17 #define NAU8540_REG_FLL2                        0x05
  18 #define NAU8540_REG_FLL3                        0x06
  19 #define NAU8540_REG_FLL4                        0x07
  20 #define NAU8540_REG_FLL5                        0x08
  21 #define NAU8540_REG_FLL6                        0x09
  22 #define NAU8540_REG_FLL_VCO_RSV         0x0A
  23 #define NAU8540_REG_PCM_CTRL0                   0x10
  24 #define NAU8540_REG_PCM_CTRL1                   0x11
  25 #define NAU8540_REG_PCM_CTRL2                   0x12
  26 #define NAU8540_REG_PCM_CTRL3                   0x13
  27 #define NAU8540_REG_PCM_CTRL4                   0x14
  28 #define NAU8540_REG_ALC_CONTROL_1               0x20
  29 #define NAU8540_REG_ALC_CONTROL_2               0x21
  30 #define NAU8540_REG_ALC_CONTROL_3               0x22
  31 #define NAU8540_REG_ALC_CONTROL_4               0x23
  32 #define NAU8540_REG_ALC_CONTROL_5               0x24
  33 #define NAU8540_REG_ALC_GAIN_CH12               0x2D
  34 #define NAU8540_REG_ALC_GAIN_CH34               0x2E
  35 #define NAU8540_REG_ALC_STATUS          0x2F
  36 #define NAU8540_REG_NOTCH_FIL1_CH1              0x30
  37 #define NAU8540_REG_NOTCH_FIL2_CH1              0x31
  38 #define NAU8540_REG_NOTCH_FIL1_CH2              0x32
  39 #define NAU8540_REG_NOTCH_FIL2_CH2              0x33
  40 #define NAU8540_REG_NOTCH_FIL1_CH3              0x34
  41 #define NAU8540_REG_NOTCH_FIL2_CH3              0x35
  42 #define NAU8540_REG_NOTCH_FIL1_CH4              0x36
  43 #define NAU8540_REG_NOTCH_FIL2_CH4              0x37
  44 #define NAU8540_REG_HPF_FILTER_CH12             0x38
  45 #define NAU8540_REG_HPF_FILTER_CH34             0x39
  46 #define NAU8540_REG_ADC_SAMPLE_RATE             0x3A
  47 #define NAU8540_REG_DIGITAL_GAIN_CH1            0x40
  48 #define NAU8540_REG_DIGITAL_GAIN_CH2            0x41
  49 #define NAU8540_REG_DIGITAL_GAIN_CH3            0x42
  50 #define NAU8540_REG_DIGITAL_GAIN_CH4            0x43
  51 #define NAU8540_REG_DIGITAL_MUX         0x44
  52 #define NAU8540_REG_P2P_CH1                     0x48
  53 #define NAU8540_REG_P2P_CH2                     0x49
  54 #define NAU8540_REG_P2P_CH3                     0x4A
  55 #define NAU8540_REG_P2P_CH4                     0x4B
  56 #define NAU8540_REG_PEAK_CH1                    0x4C
  57 #define NAU8540_REG_PEAK_CH2                    0x4D
  58 #define NAU8540_REG_PEAK_CH3                    0x4E
  59 #define NAU8540_REG_PEAK_CH4                    0x4F
  60 #define NAU8540_REG_GPIO_CTRL                   0x50
  61 #define NAU8540_REG_MISC_CTRL                   0x51
  62 #define NAU8540_REG_I2C_CTRL                    0x52
  63 #define NAU8540_REG_I2C_DEVICE_ID               0x58
  64 #define NAU8540_REG_RST                 0x5A
  65 #define NAU8540_REG_VMID_CTRL                   0x60
  66 #define NAU8540_REG_MUTE                        0x61
  67 #define NAU8540_REG_ANALOG_ADC1         0x64
  68 #define NAU8540_REG_ANALOG_ADC2         0x65
  69 #define NAU8540_REG_ANALOG_PWR          0x66
  70 #define NAU8540_REG_MIC_BIAS                    0x67
  71 #define NAU8540_REG_REFERENCE                   0x68
  72 #define NAU8540_REG_FEPGA1                      0x69
  73 #define NAU8540_REG_FEPGA2                      0x6A
  74 #define NAU8540_REG_FEPGA3                      0x6B
  75 #define NAU8540_REG_FEPGA4                      0x6C
  76 #define NAU8540_REG_PWR                 0x6D
  77 #define NAU8540_REG_MAX                 NAU8540_REG_PWR
  78
  79
  80 /* POWER_MANAGEMENT (0x01) */
  81 #define NAU8540_ADC4_EN         (0x1 << 3)
  82 #define NAU8540_ADC3_EN         (0x1 << 2)
  83 #define NAU8540_ADC2_EN         (0x1 << 1)
  84 #define NAU8540_ADC1_EN         0x1
  85
  86 /* CLOCK_CTRL (0x02) */
  87 #define NAU8540_CLK_ADC_EN              (0x1 << 15)
  88 #define NAU8540_CLK_I2S_EN              (0x1 << 1)
  89
  90 /* CLOCK_SRC (0x03) */
  91 #define NAU8540_CLK_SRC_SFT             15
  92 #define NAU8540_CLK_SRC_MASK            (1 << NAU8540_CLK_SRC_SFT)
  93 #define NAU8540_CLK_SRC_VCO             (1 << NAU8540_CLK_SRC_SFT)
  94 #define NAU8540_CLK_SRC_MCLK            (0 << NAU8540_CLK_SRC_SFT)
  95 #define NAU8540_CLK_ADC_SRC_SFT 6
  96 #define NAU8540_CLK_ADC_SRC_MASK        (0x3 << NAU8540_CLK_ADC_SRC_SFT)
  97 #define NAU8540_CLK_MCLK_SRC_MASK       0xf
  98
  99 /* FLL1 (0x04) */
 100 #define NAU8540_ICTRL_LATCH_SFT 10
 101 #define NAU8540_ICTRL_LATCH_MASK        (0x7 << NAU8540_ICTRL_LATCH_SFT)
 102 #define NAU8540_FLL_RATIO_MASK  0x7f
 103
 104 /* FLL3 (0x06) */
 105 #define NAU8540_GAIN_ERR_SFT            12
 106 #define NAU8540_GAIN_ERR_MASK           (0xf << NAU8540_GAIN_ERR_SFT)
 107 #define NAU8540_FLL_CLK_SRC_SFT 10
 108 #define NAU8540_FLL_CLK_SRC_MASK        (0x3 << NAU8540_FLL_CLK_SRC_SFT)
 109 #define NAU8540_FLL_CLK_SRC_MCLK        (0 << NAU8540_FLL_CLK_SRC_SFT)
 110 #define NAU8540_FLL_CLK_SRC_BLK (0x2 << NAU8540_FLL_CLK_SRC_SFT)
 111 #define NAU8540_FLL_CLK_SRC_FS          (0x3 << NAU8540_FLL_CLK_SRC_SFT)
 112 #define NAU8540_FLL_INTEGER_MASK        0x3ff
 113
 114 /* FLL4 (0x07) */
 115 #define NAU8540_FLL_REF_DIV_SFT 10
 116 #define NAU8540_FLL_REF_DIV_MASK        (0x3 << NAU8540_FLL_REF_DIV_SFT)
 117
 118 /* FLL5 (0x08) */
 119 #define NAU8540_FLL_PDB_DAC_EN  (0x1 << 15)
 120 #define NAU8540_FLL_LOOP_FTR_EN (0x1 << 14)
 121 #define NAU8540_FLL_CLK_SW_MASK (0x1 << 13)
 122 #define NAU8540_FLL_CLK_SW_N2           (0x1 << 13)
 123 #define NAU8540_FLL_CLK_SW_REF  (0x0 << 13)
 124 #define NAU8540_FLL_FTR_SW_MASK (0x1 << 12)
 125 #define NAU8540_FLL_FTR_SW_ACCU (0x1 << 12)
 126 #define NAU8540_FLL_FTR_SW_FILTER       (0x0 << 12)
 127
 128 /* FLL6 (0x9) */
 129 #define NAU8540_DCO_EN                  (0x1 << 15)
 130 #define NAU8540_SDM_EN                  (0x1 << 14)
 131 #define NAU8540_CUTOFF500               (0x1 << 13)
 132
 133 /* PCM_CTRL0 (0x10) */
 134 #define NAU8540_I2S_BP_SFT              7
 135 #define NAU8540_I2S_BP_INV              (0x1 << NAU8540_I2S_BP_SFT)
 136 #define NAU8540_I2S_PCMB_SFT            6
 137 #define NAU8540_I2S_PCMB_EN             (0x1 << NAU8540_I2S_PCMB_SFT)
 138 #define NAU8540_I2S_DL_SFT              2
 139 #define NAU8540_I2S_DL_MASK             (0x3 << NAU8540_I2S_DL_SFT)
 140 #define NAU8540_I2S_DL_16               (0 << NAU8540_I2S_DL_SFT)
 141 #define NAU8540_I2S_DL_20               (0x1 << NAU8540_I2S_DL_SFT)
 142 #define NAU8540_I2S_DL_24               (0x2 << NAU8540_I2S_DL_SFT)
 143 #define NAU8540_I2S_DL_32               (0x3 << NAU8540_I2S_DL_SFT)
 144 #define NAU8540_I2S_DF_MASK             0x3
 145 #define NAU8540_I2S_DF_RIGTH            0
 146 #define NAU8540_I2S_DF_LEFT             0x1
 147 #define NAU8540_I2S_DF_I2S              0x2
 148 #define NAU8540_I2S_DF_PCM_AB           0x3
 149
 150 /* PCM_CTRL1 (0x11) */
 151 #define NAU8540_I2S_DO12_TRI            (0x1 << 15)
 152 #define NAU8540_I2S_LRC_DIV_SFT 12
 153 #define NAU8540_I2S_LRC_DIV_MASK        (0x3 << NAU8540_I2S_LRC_DIV_SFT)
 154 #define NAU8540_I2S_DO12_OE             (0x1 << 4)
 155 #define NAU8540_I2S_MS_SFT              3
 156 #define NAU8540_I2S_MS_MASK             (0x1 << NAU8540_I2S_MS_SFT)
 157 #define NAU8540_I2S_MS_MASTER           (0x1 << NAU8540_I2S_MS_SFT)
 158 #define NAU8540_I2S_MS_SLAVE            (0x0 << NAU8540_I2S_MS_SFT)
 159 #define NAU8540_I2S_BLK_DIV_MASK        0x7
 160
 161 /* PCM_CTRL1 (0x12) */
 162 #define NAU8540_I2S_DO34_TRI            (0x1 << 15)
 163 #define NAU8540_I2S_DO34_OE             (0x1 << 11)
 164 #define NAU8540_I2S_TSLOT_L_MASK        0x3ff
 165
 166 /* PCM_CTRL4 (0x14) */
 167 #define NAU8540_TDM_MODE                (0x1 << 15)
 168 #define NAU8540_TDM_OFFSET_EN           (0x1 << 14)
 169 #define NAU8540_TDM_TX_MASK             0xf
 170
 171 /* ADC_SAMPLE_RATE (0x3A) */
 172 #define NAU8540_CH_SYNC         (0x1 << 14)
 173 #define NAU8540_ADC_OSR_MASK            0x3
 174 #define NAU8540_ADC_OSR_256             0x3
 175 #define NAU8540_ADC_OSR_128             0x2
 176 #define NAU8540_ADC_OSR_64              0x1
 177 #define NAU8540_ADC_OSR_32              0x0
 178
 179 /* VMID_CTRL (0x60) */
 180 #define NAU8540_VMID_EN         (1 << 6)
 181 #define NAU8540_VMID_SEL_SFT            4
 182 #define NAU8540_VMID_SEL_MASK           (0x3 << NAU8540_VMID_SEL_SFT)
 183
 184 /* MIC_BIAS (0x67) */
 185 #define NAU8540_PU_PRE                  (0x1 << 8)
 186
 187 /* REFERENCE (0x68) */
 188 #define NAU8540_PRECHARGE_DIS           (0x1 << 13)
 189 #define NAU8540_GLOBAL_BIAS_EN  (0x1 << 12)
 190
 191 /* FEPGA1 (0x69) */
 192 #define NAU8540_FEPGA1_MODCH2_SHT_SFT   7
 193 #define NAU8540_FEPGA1_MODCH2_SHT       (0x1 << NAU8540_FEPGA1_MODCH2_SHT_SFT)
 194 #define NAU8540_FEPGA1_MODCH1_SHT_SFT   3
 195 #define NAU8540_FEPGA1_MODCH1_SHT       (0x1 << NAU8540_FEPGA1_MODCH1_SHT_SFT)
 196
 197 /* FEPGA2 (0x6A) */
 198 #define NAU8540_FEPGA2_MODCH4_SHT_SFT   7
 199 #define NAU8540_FEPGA2_MODCH4_SHT       (0x1 << NAU8540_FEPGA2_MODCH4_SHT_SFT)
 200 #define NAU8540_FEPGA2_MODCH3_SHT_SFT   3
 201 #define NAU8540_FEPGA2_MODCH3_SHT       (0x1 << NAU8540_FEPGA2_MODCH3_SHT_SFT)
 202
 203
 204 /* System Clock Source */
 205 enum {
 206         NAU8540_CLK_DIS,
 207         NAU8540_CLK_MCLK,
 208         NAU8540_CLK_INTERNAL,
 209         NAU8540_CLK_FLL_MCLK,
 210         NAU8540_CLK_FLL_BLK,
 211         NAU8540_CLK_FLL_FS,
 212 };
 213
 214 struct nau8540 {
 215         struct device *dev;
 216         struct regmap *regmap;
 217 };
 218
 219 struct nau8540_fll {
 220         int mclk_src;
 221         int ratio;
 222         int fll_frac;
 223         int fll_int;
 224         int clk_ref_div;
 225 };
 226
 227 struct nau8540_fll_attr {
 228         unsigned int param;
 229         unsigned int val;
 230 };
 231
 232 /* over sampling rate */
 233 struct nau8540_osr_attr {
 234         unsigned int osr;
 235         unsigned int clk_src;
 236 };
 237
 238
 239 #endif  /* __NAU8540_H__ */