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ARM: dts: omap5: Add bus_dma_limit for L3 bus
[linux/fpc-iii.git] / sound / soc / codecs / wm8400.c
blobe25c09b8a6938a3fc2211efbeec813d7481aace8
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * wm8400.c -- WM8400 ALSA Soc Audio driver
4 *
5 * Copyright 2008-11 Wolfson Microelectronics PLC.
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 */
8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/pm.h>
16 #include <linux/platform_device.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/mfd/wm8400-audio.h>
19 #include <linux/mfd/wm8400-private.h>
20 #include <linux/mfd/core.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/soc.h>
25 #include <sound/initval.h>
26 #include <sound/tlv.h>
27
28 #include "wm8400.h"
29
30 static struct regulator_bulk_data power[] = {
31 {
32 .supply = "I2S1VDD",
33 },
34 {
35 .supply = "I2S2VDD",
36 },
37 {
38 .supply = "DCVDD",
39 },
40 {
41 .supply = "AVDD",
42 },
43 {
44 .supply = "FLLVDD",
45 },
46 {
47 .supply = "HPVDD",
48 },
49 {
50 .supply = "SPKVDD",
51 },
52 };
53
54 /* codec private data */
55 struct wm8400_priv {
56 struct wm8400 *wm8400;
57 u16 fake_register;
58 unsigned int sysclk;
59 unsigned int pcmclk;
60 int fll_in, fll_out;
61 };
62
63 static void wm8400_component_reset(struct snd_soc_component *component)
64 {
65 struct wm8400_priv *wm8400 = snd_soc_component_get_drvdata(component);
66
67 wm8400_reset_codec_reg_cache(wm8400->wm8400);
68 }
69
70 static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0);
71
72 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
73
74 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -2100, 0, 0);
75
76 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
77
78 static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0);
79
80 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
81
82 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
83
84 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
85
86 static int wm8400_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
87 struct snd_ctl_elem_value *ucontrol)
88 {
89 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
90 struct soc_mixer_control *mc =
91 (struct soc_mixer_control *)kcontrol->private_value;
92 int reg = mc->reg;
93 int ret;
94 u16 val;
95
96 ret = snd_soc_put_volsw(kcontrol, ucontrol);
97 if (ret < 0)
98 return ret;
99
100 /* now hit the volume update bits (always bit 8) */
101 val = snd_soc_component_read32(component, reg);
102 return snd_soc_component_write(component, reg, val | 0x0100);
103 }
104
105 #define WM8400_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \
106 SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \
107 snd_soc_get_volsw, wm8400_outpga_put_volsw_vu, tlv_array)
108
109
110 static const char *wm8400_digital_sidetone[] =
111 {"None", "Left ADC", "Right ADC", "Reserved"};
112
113 static SOC_ENUM_SINGLE_DECL(wm8400_left_digital_sidetone_enum,
114 WM8400_DIGITAL_SIDE_TONE,
115 WM8400_ADC_TO_DACL_SHIFT,
116 wm8400_digital_sidetone);
117
118 static SOC_ENUM_SINGLE_DECL(wm8400_right_digital_sidetone_enum,
119 WM8400_DIGITAL_SIDE_TONE,
120 WM8400_ADC_TO_DACR_SHIFT,
121 wm8400_digital_sidetone);
122
123 static const char *wm8400_adcmode[] =
124 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
125
126 static SOC_ENUM_SINGLE_DECL(wm8400_right_adcmode_enum,
127 WM8400_ADC_CTRL,
128 WM8400_ADC_HPF_CUT_SHIFT,
129 wm8400_adcmode);
130
131 static const struct snd_kcontrol_new wm8400_snd_controls[] = {
132 /* INMIXL */
133 SOC_SINGLE("LIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L12MNBST_SHIFT,
134 1, 0),
135 SOC_SINGLE("LIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L34MNBST_SHIFT,
136 1, 0),
137 /* INMIXR */
138 SOC_SINGLE("RIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R12MNBST_SHIFT,
139 1, 0),
140 SOC_SINGLE("RIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R34MNBST_SHIFT,
141 1, 0),
142
143 /* LOMIX */
144 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER3,
145 WM8400_LLI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
146 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
147 WM8400_LR12LOVOL_SHIFT, 7, 0, out_mix_tlv),
148 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
149 WM8400_LL12LOVOL_SHIFT, 7, 0, out_mix_tlv),
150 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER5,
151 WM8400_LRI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
152 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
153 WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
154 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
155 WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
156
157 /* ROMIX */
158 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER4,
159 WM8400_RRI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
160 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
161 WM8400_RL12ROVOL_SHIFT, 7, 0, out_mix_tlv),
162 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
163 WM8400_RR12ROVOL_SHIFT, 7, 0, out_mix_tlv),
164 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER6,
165 WM8400_RLI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
166 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
167 WM8400_RLBROVOL_SHIFT, 7, 0, out_mix_tlv),
168 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
169 WM8400_RRBROVOL_SHIFT, 7, 0, out_mix_tlv),
170
171 /* LOUT */
172 WM8400_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8400_LEFT_OUTPUT_VOLUME,
173 WM8400_LOUTVOL_SHIFT, WM8400_LOUTVOL_MASK, 0, out_pga_tlv),
174 SOC_SINGLE("LOUT ZC", WM8400_LEFT_OUTPUT_VOLUME, WM8400_LOZC_SHIFT, 1, 0),
175
176 /* ROUT */
177 WM8400_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8400_RIGHT_OUTPUT_VOLUME,
178 WM8400_ROUTVOL_SHIFT, WM8400_ROUTVOL_MASK, 0, out_pga_tlv),
179 SOC_SINGLE("ROUT ZC", WM8400_RIGHT_OUTPUT_VOLUME, WM8400_ROZC_SHIFT, 1, 0),
180
181 /* LOPGA */
182 WM8400_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8400_LEFT_OPGA_VOLUME,
183 WM8400_LOPGAVOL_SHIFT, WM8400_LOPGAVOL_MASK, 0, out_pga_tlv),
184 SOC_SINGLE("LOPGA ZC Switch", WM8400_LEFT_OPGA_VOLUME,
185 WM8400_LOPGAZC_SHIFT, 1, 0),
186
187 /* ROPGA */
188 WM8400_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8400_RIGHT_OPGA_VOLUME,
189 WM8400_ROPGAVOL_SHIFT, WM8400_ROPGAVOL_MASK, 0, out_pga_tlv),
190 SOC_SINGLE("ROPGA ZC Switch", WM8400_RIGHT_OPGA_VOLUME,
191 WM8400_ROPGAZC_SHIFT, 1, 0),
192
193 SOC_SINGLE("LON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
194 WM8400_LONMUTE_SHIFT, 1, 0),
195 SOC_SINGLE("LOP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
196 WM8400_LOPMUTE_SHIFT, 1, 0),
197 SOC_SINGLE("LOP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
198 WM8400_LOATTN_SHIFT, 1, 0),
199 SOC_SINGLE("RON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
200 WM8400_RONMUTE_SHIFT, 1, 0),
201 SOC_SINGLE("ROP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
202 WM8400_ROPMUTE_SHIFT, 1, 0),
203 SOC_SINGLE("ROP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
204 WM8400_ROATTN_SHIFT, 1, 0),
205
206 SOC_SINGLE("OUT3 Mute Switch", WM8400_OUT3_4_VOLUME,
207 WM8400_OUT3MUTE_SHIFT, 1, 0),
208 SOC_SINGLE("OUT3 Attenuation Switch", WM8400_OUT3_4_VOLUME,
209 WM8400_OUT3ATTN_SHIFT, 1, 0),
210
211 SOC_SINGLE("OUT4 Mute Switch", WM8400_OUT3_4_VOLUME,
212 WM8400_OUT4MUTE_SHIFT, 1, 0),
213 SOC_SINGLE("OUT4 Attenuation Switch", WM8400_OUT3_4_VOLUME,
214 WM8400_OUT4ATTN_SHIFT, 1, 0),
215
216 SOC_SINGLE("Speaker Mode Switch", WM8400_CLASSD1,
217 WM8400_CDMODE_SHIFT, 1, 0),
218
219 SOC_SINGLE("Speaker Output Attenuation Volume", WM8400_SPEAKER_VOLUME,
220 WM8400_SPKATTN_SHIFT, WM8400_SPKATTN_MASK, 0),
221 SOC_SINGLE("Speaker DC Boost Volume", WM8400_CLASSD3,
222 WM8400_DCGAIN_SHIFT, 6, 0),
223 SOC_SINGLE("Speaker AC Boost Volume", WM8400_CLASSD3,
224 WM8400_ACGAIN_SHIFT, 6, 0),
225
226 WM8400_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
227 WM8400_LEFT_DAC_DIGITAL_VOLUME, WM8400_DACL_VOL_SHIFT,
228 127, 0, out_dac_tlv),
229
230 WM8400_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
231 WM8400_RIGHT_DAC_DIGITAL_VOLUME, WM8400_DACR_VOL_SHIFT,
232 127, 0, out_dac_tlv),
233
234 SOC_ENUM("Left Digital Sidetone", wm8400_left_digital_sidetone_enum),
235 SOC_ENUM("Right Digital Sidetone", wm8400_right_digital_sidetone_enum),
236
237 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
238 WM8400_ADCL_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
239 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
240 WM8400_ADCR_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
241
242 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8400_ADC_CTRL,
243 WM8400_ADC_HPF_ENA_SHIFT, 1, 0),
244
245 SOC_ENUM("ADC HPF Mode", wm8400_right_adcmode_enum),
246
247 WM8400_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
248 WM8400_LEFT_ADC_DIGITAL_VOLUME,
249 WM8400_ADCL_VOL_SHIFT,
250 WM8400_ADCL_VOL_MASK,
251 0,
252 in_adc_tlv),
253
254 WM8400_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
255 WM8400_RIGHT_ADC_DIGITAL_VOLUME,
256 WM8400_ADCR_VOL_SHIFT,
257 WM8400_ADCR_VOL_MASK,
258 0,
259 in_adc_tlv),
260
261 WM8400_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
262 WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
263 WM8400_LIN12VOL_SHIFT,
264 WM8400_LIN12VOL_MASK,
265 0,
266 in_pga_tlv),
267
268 SOC_SINGLE("LIN12 ZC Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
269 WM8400_LI12ZC_SHIFT, 1, 0),
270
271 SOC_SINGLE("LIN12 Mute Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
272 WM8400_LI12MUTE_SHIFT, 1, 0),
273
274 WM8400_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
275 WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
276 WM8400_LIN34VOL_SHIFT,
277 WM8400_LIN34VOL_MASK,
278 0,
279 in_pga_tlv),
280
281 SOC_SINGLE("LIN34 ZC Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
282 WM8400_LI34ZC_SHIFT, 1, 0),
283
284 SOC_SINGLE("LIN34 Mute Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
285 WM8400_LI34MUTE_SHIFT, 1, 0),
286
287 WM8400_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
288 WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
289 WM8400_RIN12VOL_SHIFT,
290 WM8400_RIN12VOL_MASK,
291 0,
292 in_pga_tlv),
293
294 SOC_SINGLE("RIN12 ZC Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
295 WM8400_RI12ZC_SHIFT, 1, 0),
296
297 SOC_SINGLE("RIN12 Mute Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
298 WM8400_RI12MUTE_SHIFT, 1, 0),
299
300 WM8400_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
301 WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
302 WM8400_RIN34VOL_SHIFT,
303 WM8400_RIN34VOL_MASK,
304 0,
305 in_pga_tlv),
306
307 SOC_SINGLE("RIN34 ZC Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
308 WM8400_RI34ZC_SHIFT, 1, 0),
309
310 SOC_SINGLE("RIN34 Mute Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
311 WM8400_RI34MUTE_SHIFT, 1, 0),
312
313 };
314
315 /*
316 * _DAPM_ Controls
317 */
318
319 static int outmixer_event (struct snd_soc_dapm_widget *w,
320 struct snd_kcontrol * kcontrol, int event)
321 {
322 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
323 struct soc_mixer_control *mc =
324 (struct soc_mixer_control *)kcontrol->private_value;
325 u32 reg_shift = mc->shift;
326 int ret = 0;
327 u16 reg;
328
329 switch (reg_shift) {
330 case WM8400_SPEAKER_MIXER | (WM8400_LDSPK << 8) :
331 reg = snd_soc_component_read32(component, WM8400_OUTPUT_MIXER1);
332 if (reg & WM8400_LDLO) {
333 printk(KERN_WARNING
334 "Cannot set as Output Mixer 1 LDLO Set\n");
335 ret = -1;
336 }
337 break;
338 case WM8400_SPEAKER_MIXER | (WM8400_RDSPK << 8):
339 reg = snd_soc_component_read32(component, WM8400_OUTPUT_MIXER2);
340 if (reg & WM8400_RDRO) {
341 printk(KERN_WARNING
342 "Cannot set as Output Mixer 2 RDRO Set\n");
343 ret = -1;
344 }
345 break;
346 case WM8400_OUTPUT_MIXER1 | (WM8400_LDLO << 8):
347 reg = snd_soc_component_read32(component, WM8400_SPEAKER_MIXER);
348 if (reg & WM8400_LDSPK) {
349 printk(KERN_WARNING
350 "Cannot set as Speaker Mixer LDSPK Set\n");
351 ret = -1;
352 }
353 break;
354 case WM8400_OUTPUT_MIXER2 | (WM8400_RDRO << 8):
355 reg = snd_soc_component_read32(component, WM8400_SPEAKER_MIXER);
356 if (reg & WM8400_RDSPK) {
357 printk(KERN_WARNING
358 "Cannot set as Speaker Mixer RDSPK Set\n");
359 ret = -1;
360 }
361 break;
362 }
363
364 return ret;
365 }
366
367 /* INMIX dB values */
368 static const DECLARE_TLV_DB_SCALE(in_mix_tlv, -1200, 600, 0);
369
370 /* Left In PGA Connections */
371 static const struct snd_kcontrol_new wm8400_dapm_lin12_pga_controls[] = {
372 SOC_DAPM_SINGLE("LIN1 Switch", WM8400_INPUT_MIXER2, WM8400_LMN1_SHIFT, 1, 0),
373 SOC_DAPM_SINGLE("LIN2 Switch", WM8400_INPUT_MIXER2, WM8400_LMP2_SHIFT, 1, 0),
374 };
375
376 static const struct snd_kcontrol_new wm8400_dapm_lin34_pga_controls[] = {
377 SOC_DAPM_SINGLE("LIN3 Switch", WM8400_INPUT_MIXER2, WM8400_LMN3_SHIFT, 1, 0),
378 SOC_DAPM_SINGLE("LIN4 Switch", WM8400_INPUT_MIXER2, WM8400_LMP4_SHIFT, 1, 0),
379 };
380
381 /* Right In PGA Connections */
382 static const struct snd_kcontrol_new wm8400_dapm_rin12_pga_controls[] = {
383 SOC_DAPM_SINGLE("RIN1 Switch", WM8400_INPUT_MIXER2, WM8400_RMN1_SHIFT, 1, 0),
384 SOC_DAPM_SINGLE("RIN2 Switch", WM8400_INPUT_MIXER2, WM8400_RMP2_SHIFT, 1, 0),
385 };
386
387 static const struct snd_kcontrol_new wm8400_dapm_rin34_pga_controls[] = {
388 SOC_DAPM_SINGLE("RIN3 Switch", WM8400_INPUT_MIXER2, WM8400_RMN3_SHIFT, 1, 0),
389 SOC_DAPM_SINGLE("RIN4 Switch", WM8400_INPUT_MIXER2, WM8400_RMP4_SHIFT, 1, 0),
390 };
391
392 /* INMIXL */
393 static const struct snd_kcontrol_new wm8400_dapm_inmixl_controls[] = {
394 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8400_INPUT_MIXER3,
395 WM8400_LDBVOL_SHIFT, WM8400_LDBVOL_MASK, 0, in_mix_tlv),
396 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8400_INPUT_MIXER5, WM8400_LI2BVOL_SHIFT,
397 7, 0, in_mix_tlv),
398 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
399 1, 0),
400 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
401 1, 0),
402 };
403
404 /* INMIXR */
405 static const struct snd_kcontrol_new wm8400_dapm_inmixr_controls[] = {
406 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8400_INPUT_MIXER4,
407 WM8400_RDBVOL_SHIFT, WM8400_RDBVOL_MASK, 0, in_mix_tlv),
408 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8400_INPUT_MIXER6, WM8400_RI2BVOL_SHIFT,
409 7, 0, in_mix_tlv),
410 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
411 1, 0),
412 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
413 1, 0),
414 };
415
416 /* AINLMUX */
417 static const char *wm8400_ainlmux[] =
418 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
419
420 static SOC_ENUM_SINGLE_DECL(wm8400_ainlmux_enum,
421 WM8400_INPUT_MIXER1,
422 WM8400_AINLMODE_SHIFT,
423 wm8400_ainlmux);
424
425 static const struct snd_kcontrol_new wm8400_dapm_ainlmux_controls =
426 SOC_DAPM_ENUM("Route", wm8400_ainlmux_enum);
427
428 /* DIFFINL */
429
430 /* AINRMUX */
431 static const char *wm8400_ainrmux[] =
432 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
433
434 static SOC_ENUM_SINGLE_DECL(wm8400_ainrmux_enum,
435 WM8400_INPUT_MIXER1,
436 WM8400_AINRMODE_SHIFT,
437 wm8400_ainrmux);
438
439 static const struct snd_kcontrol_new wm8400_dapm_ainrmux_controls =
440 SOC_DAPM_ENUM("Route", wm8400_ainrmux_enum);
441
442 /* RXVOICE */
443 static const struct snd_kcontrol_new wm8400_dapm_rxvoice_controls[] = {
444 SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8400_INPUT_MIXER5, WM8400_LR4BVOL_SHIFT,
445 WM8400_LR4BVOL_MASK, 0, in_mix_tlv),
446 SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8400_INPUT_MIXER6, WM8400_RL4BVOL_SHIFT,
447 WM8400_RL4BVOL_MASK, 0, in_mix_tlv),
448 };
449
450 /* LOMIX */
451 static const struct snd_kcontrol_new wm8400_dapm_lomix_controls[] = {
452 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
453 WM8400_LRBLO_SHIFT, 1, 0),
454 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
455 WM8400_LLBLO_SHIFT, 1, 0),
456 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
457 WM8400_LRI3LO_SHIFT, 1, 0),
458 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
459 WM8400_LLI3LO_SHIFT, 1, 0),
460 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
461 WM8400_LR12LO_SHIFT, 1, 0),
462 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
463 WM8400_LL12LO_SHIFT, 1, 0),
464 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8400_OUTPUT_MIXER1,
465 WM8400_LDLO_SHIFT, 1, 0),
466 };
467
468 /* ROMIX */
469 static const struct snd_kcontrol_new wm8400_dapm_romix_controls[] = {
470 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
471 WM8400_RLBRO_SHIFT, 1, 0),
472 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
473 WM8400_RRBRO_SHIFT, 1, 0),
474 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
475 WM8400_RLI3RO_SHIFT, 1, 0),
476 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
477 WM8400_RRI3RO_SHIFT, 1, 0),
478 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
479 WM8400_RL12RO_SHIFT, 1, 0),
480 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
481 WM8400_RR12RO_SHIFT, 1, 0),
482 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8400_OUTPUT_MIXER2,
483 WM8400_RDRO_SHIFT, 1, 0),
484 };
485
486 /* LONMIX */
487 static const struct snd_kcontrol_new wm8400_dapm_lonmix_controls[] = {
488 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
489 WM8400_LLOPGALON_SHIFT, 1, 0),
490 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER1,
491 WM8400_LROPGALON_SHIFT, 1, 0),
492 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8400_LINE_MIXER1,
493 WM8400_LOPLON_SHIFT, 1, 0),
494 };
495
496 /* LOPMIX */
497 static const struct snd_kcontrol_new wm8400_dapm_lopmix_controls[] = {
498 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER1,
499 WM8400_LR12LOP_SHIFT, 1, 0),
500 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER1,
501 WM8400_LL12LOP_SHIFT, 1, 0),
502 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
503 WM8400_LLOPGALOP_SHIFT, 1, 0),
504 };
505
506 /* RONMIX */
507 static const struct snd_kcontrol_new wm8400_dapm_ronmix_controls[] = {
508 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
509 WM8400_RROPGARON_SHIFT, 1, 0),
510 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER2,
511 WM8400_RLOPGARON_SHIFT, 1, 0),
512 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8400_LINE_MIXER2,
513 WM8400_ROPRON_SHIFT, 1, 0),
514 };
515
516 /* ROPMIX */
517 static const struct snd_kcontrol_new wm8400_dapm_ropmix_controls[] = {
518 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER2,
519 WM8400_RL12ROP_SHIFT, 1, 0),
520 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER2,
521 WM8400_RR12ROP_SHIFT, 1, 0),
522 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
523 WM8400_RROPGAROP_SHIFT, 1, 0),
524 };
525
526 /* OUT3MIX */
527 static const struct snd_kcontrol_new wm8400_dapm_out3mix_controls[] = {
528 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
529 WM8400_LI4O3_SHIFT, 1, 0),
530 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8400_OUT3_4_MIXER,
531 WM8400_LPGAO3_SHIFT, 1, 0),
532 };
533
534 /* OUT4MIX */
535 static const struct snd_kcontrol_new wm8400_dapm_out4mix_controls[] = {
536 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8400_OUT3_4_MIXER,
537 WM8400_RPGAO4_SHIFT, 1, 0),
538 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
539 WM8400_RI4O4_SHIFT, 1, 0),
540 };
541
542 /* SPKMIX */
543 static const struct snd_kcontrol_new wm8400_dapm_spkmix_controls[] = {
544 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
545 WM8400_LI2SPK_SHIFT, 1, 0),
546 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8400_SPEAKER_MIXER,
547 WM8400_LB2SPK_SHIFT, 1, 0),
548 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8400_SPEAKER_MIXER,
549 WM8400_LOPGASPK_SHIFT, 1, 0),
550 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8400_SPEAKER_MIXER,
551 WM8400_LDSPK_SHIFT, 1, 0),
552 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8400_SPEAKER_MIXER,
553 WM8400_RDSPK_SHIFT, 1, 0),
554 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8400_SPEAKER_MIXER,
555 WM8400_ROPGASPK_SHIFT, 1, 0),
556 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8400_SPEAKER_MIXER,
557 WM8400_RL12ROP_SHIFT, 1, 0),
558 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
559 WM8400_RI2SPK_SHIFT, 1, 0),
560 };
561
562 static const struct snd_soc_dapm_widget wm8400_dapm_widgets[] = {
563 /* Input Side */
564 /* Input Lines */
565 SND_SOC_DAPM_INPUT("LIN1"),
566 SND_SOC_DAPM_INPUT("LIN2"),
567 SND_SOC_DAPM_INPUT("LIN3"),
568 SND_SOC_DAPM_INPUT("LIN4/RXN"),
569 SND_SOC_DAPM_INPUT("RIN3"),
570 SND_SOC_DAPM_INPUT("RIN4/RXP"),
571 SND_SOC_DAPM_INPUT("RIN1"),
572 SND_SOC_DAPM_INPUT("RIN2"),
573 SND_SOC_DAPM_INPUT("Internal ADC Source"),
574
575 /* DACs */
576 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8400_POWER_MANAGEMENT_2,
577 WM8400_ADCL_ENA_SHIFT, 0),
578 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8400_POWER_MANAGEMENT_2,
579 WM8400_ADCR_ENA_SHIFT, 0),
580
581 /* Input PGAs */
582 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8400_POWER_MANAGEMENT_2,
583 WM8400_LIN12_ENA_SHIFT,
584 0, &wm8400_dapm_lin12_pga_controls[0],
585 ARRAY_SIZE(wm8400_dapm_lin12_pga_controls)),
586 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8400_POWER_MANAGEMENT_2,
587 WM8400_LIN34_ENA_SHIFT,
588 0, &wm8400_dapm_lin34_pga_controls[0],
589 ARRAY_SIZE(wm8400_dapm_lin34_pga_controls)),
590 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8400_POWER_MANAGEMENT_2,
591 WM8400_RIN12_ENA_SHIFT,
592 0, &wm8400_dapm_rin12_pga_controls[0],
593 ARRAY_SIZE(wm8400_dapm_rin12_pga_controls)),
594 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8400_POWER_MANAGEMENT_2,
595 WM8400_RIN34_ENA_SHIFT,
596 0, &wm8400_dapm_rin34_pga_controls[0],
597 ARRAY_SIZE(wm8400_dapm_rin34_pga_controls)),
598
599 SND_SOC_DAPM_SUPPLY("INL", WM8400_POWER_MANAGEMENT_2, WM8400_AINL_ENA_SHIFT,
600 0, NULL, 0),
601 SND_SOC_DAPM_SUPPLY("INR", WM8400_POWER_MANAGEMENT_2, WM8400_AINR_ENA_SHIFT,
602 0, NULL, 0),
603
604 /* INMIXL */
605 SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0,
606 &wm8400_dapm_inmixl_controls[0],
607 ARRAY_SIZE(wm8400_dapm_inmixl_controls)),
608
609 /* AINLMUX */
610 SND_SOC_DAPM_MUX("AILNMUX", SND_SOC_NOPM, 0, 0, &wm8400_dapm_ainlmux_controls),
611
612 /* INMIXR */
613 SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0,
614 &wm8400_dapm_inmixr_controls[0],
615 ARRAY_SIZE(wm8400_dapm_inmixr_controls)),
616
617 /* AINRMUX */
618 SND_SOC_DAPM_MUX("AIRNMUX", SND_SOC_NOPM, 0, 0, &wm8400_dapm_ainrmux_controls),
619
620 /* Output Side */
621 /* DACs */
622 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8400_POWER_MANAGEMENT_3,
623 WM8400_DACL_ENA_SHIFT, 0),
624 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8400_POWER_MANAGEMENT_3,
625 WM8400_DACR_ENA_SHIFT, 0),
626
627 /* LOMIX */
628 SND_SOC_DAPM_MIXER_E("LOMIX", WM8400_POWER_MANAGEMENT_3,
629 WM8400_LOMIX_ENA_SHIFT,
630 0, &wm8400_dapm_lomix_controls[0],
631 ARRAY_SIZE(wm8400_dapm_lomix_controls),
632 outmixer_event, SND_SOC_DAPM_PRE_REG),
633
634 /* LONMIX */
635 SND_SOC_DAPM_MIXER("LONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LON_ENA_SHIFT,
636 0, &wm8400_dapm_lonmix_controls[0],
637 ARRAY_SIZE(wm8400_dapm_lonmix_controls)),
638
639 /* LOPMIX */
640 SND_SOC_DAPM_MIXER("LOPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LOP_ENA_SHIFT,
641 0, &wm8400_dapm_lopmix_controls[0],
642 ARRAY_SIZE(wm8400_dapm_lopmix_controls)),
643
644 /* OUT3MIX */
645 SND_SOC_DAPM_MIXER("OUT3MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT3_ENA_SHIFT,
646 0, &wm8400_dapm_out3mix_controls[0],
647 ARRAY_SIZE(wm8400_dapm_out3mix_controls)),
648
649 /* SPKMIX */
650 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8400_POWER_MANAGEMENT_1, WM8400_SPK_ENA_SHIFT,
651 0, &wm8400_dapm_spkmix_controls[0],
652 ARRAY_SIZE(wm8400_dapm_spkmix_controls), outmixer_event,
653 SND_SOC_DAPM_PRE_REG),
654
655 /* OUT4MIX */
656 SND_SOC_DAPM_MIXER("OUT4MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT4_ENA_SHIFT,
657 0, &wm8400_dapm_out4mix_controls[0],
658 ARRAY_SIZE(wm8400_dapm_out4mix_controls)),
659
660 /* ROPMIX */
661 SND_SOC_DAPM_MIXER("ROPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_ROP_ENA_SHIFT,
662 0, &wm8400_dapm_ropmix_controls[0],
663 ARRAY_SIZE(wm8400_dapm_ropmix_controls)),
664
665 /* RONMIX */
666 SND_SOC_DAPM_MIXER("RONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_RON_ENA_SHIFT,
667 0, &wm8400_dapm_ronmix_controls[0],
668 ARRAY_SIZE(wm8400_dapm_ronmix_controls)),
669
670 /* ROMIX */
671 SND_SOC_DAPM_MIXER_E("ROMIX", WM8400_POWER_MANAGEMENT_3,
672 WM8400_ROMIX_ENA_SHIFT,
673 0, &wm8400_dapm_romix_controls[0],
674 ARRAY_SIZE(wm8400_dapm_romix_controls),
675 outmixer_event, SND_SOC_DAPM_PRE_REG),
676
677 /* LOUT PGA */
678 SND_SOC_DAPM_PGA("LOUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_LOUT_ENA_SHIFT,
679 0, NULL, 0),
680
681 /* ROUT PGA */
682 SND_SOC_DAPM_PGA("ROUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_ROUT_ENA_SHIFT,
683 0, NULL, 0),
684
685 /* LOPGA */
686 SND_SOC_DAPM_PGA("LOPGA", WM8400_POWER_MANAGEMENT_3, WM8400_LOPGA_ENA_SHIFT, 0,
687 NULL, 0),
688
689 /* ROPGA */
690 SND_SOC_DAPM_PGA("ROPGA", WM8400_POWER_MANAGEMENT_3, WM8400_ROPGA_ENA_SHIFT, 0,
691 NULL, 0),
692
693 /* MICBIAS */
694 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8400_POWER_MANAGEMENT_1,
695 WM8400_MIC1BIAS_ENA_SHIFT, 0, NULL, 0),
696
697 SND_SOC_DAPM_OUTPUT("LON"),
698 SND_SOC_DAPM_OUTPUT("LOP"),
699 SND_SOC_DAPM_OUTPUT("OUT3"),
700 SND_SOC_DAPM_OUTPUT("LOUT"),
701 SND_SOC_DAPM_OUTPUT("SPKN"),
702 SND_SOC_DAPM_OUTPUT("SPKP"),
703 SND_SOC_DAPM_OUTPUT("ROUT"),
704 SND_SOC_DAPM_OUTPUT("OUT4"),
705 SND_SOC_DAPM_OUTPUT("ROP"),
706 SND_SOC_DAPM_OUTPUT("RON"),
707
708 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
709 };
710
711 static const struct snd_soc_dapm_route wm8400_dapm_routes[] = {
712 /* Make DACs turn on when playing even if not mixed into any outputs */
713 {"Internal DAC Sink", NULL, "Left DAC"},
714 {"Internal DAC Sink", NULL, "Right DAC"},
715
716 /* Make ADCs turn on when recording
717 * even if not mixed from any inputs */
718 {"Left ADC", NULL, "Internal ADC Source"},
719 {"Right ADC", NULL, "Internal ADC Source"},
720
721 /* Input Side */
722 /* LIN12 PGA */
723 {"LIN12 PGA", "LIN1 Switch", "LIN1"},
724 {"LIN12 PGA", "LIN2 Switch", "LIN2"},
725 /* LIN34 PGA */
726 {"LIN34 PGA", "LIN3 Switch", "LIN3"},
727 {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
728 /* INMIXL */
729 {"INMIXL", NULL, "INL"},
730 {"INMIXL", "Record Left Volume", "LOMIX"},
731 {"INMIXL", "LIN2 Volume", "LIN2"},
732 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
733 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
734 /* AILNMUX */
735 {"AILNMUX", NULL, "INL"},
736 {"AILNMUX", "INMIXL Mix", "INMIXL"},
737 {"AILNMUX", "DIFFINL Mix", "LIN12 PGA"},
738 {"AILNMUX", "DIFFINL Mix", "LIN34 PGA"},
739 {"AILNMUX", "RXVOICE Mix", "LIN4/RXN"},
740 {"AILNMUX", "RXVOICE Mix", "RIN4/RXP"},
741 /* ADC */
742 {"Left ADC", NULL, "AILNMUX"},
743
744 /* RIN12 PGA */
745 {"RIN12 PGA", "RIN1 Switch", "RIN1"},
746 {"RIN12 PGA", "RIN2 Switch", "RIN2"},
747 /* RIN34 PGA */
748 {"RIN34 PGA", "RIN3 Switch", "RIN3"},
749 {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
750 /* INMIXR */
751 {"INMIXR", NULL, "INR"},
752 {"INMIXR", "Record Right Volume", "ROMIX"},
753 {"INMIXR", "RIN2 Volume", "RIN2"},
754 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
755 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
756 /* AIRNMUX */
757 {"AIRNMUX", NULL, "INR"},
758 {"AIRNMUX", "INMIXR Mix", "INMIXR"},
759 {"AIRNMUX", "DIFFINR Mix", "RIN12 PGA"},
760 {"AIRNMUX", "DIFFINR Mix", "RIN34 PGA"},
761 {"AIRNMUX", "RXVOICE Mix", "LIN4/RXN"},
762 {"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"},
763 /* ADC */
764 {"Right ADC", NULL, "AIRNMUX"},
765
766 /* LOMIX */
767 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
768 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
769 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
770 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
771 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AIRNMUX"},
772 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AILNMUX"},
773 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
774
775 /* ROMIX */
776 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
777 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
778 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
779 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
780 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AIRNMUX"},
781 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AILNMUX"},
782 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
783
784 /* SPKMIX */
785 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
786 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
787 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AILNMUX"},
788 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AIRNMUX"},
789 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
790 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
791 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
792 {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"},
793
794 /* LONMIX */
795 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
796 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
797 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
798
799 /* LOPMIX */
800 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
801 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
802 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
803
804 /* OUT3MIX */
805 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
806 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
807
808 /* OUT4MIX */
809 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
810 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
811
812 /* RONMIX */
813 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
814 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
815 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
816
817 /* ROPMIX */
818 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
819 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
820 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
821
822 /* Out Mixer PGAs */
823 {"LOPGA", NULL, "LOMIX"},
824 {"ROPGA", NULL, "ROMIX"},
825
826 {"LOUT PGA", NULL, "LOMIX"},
827 {"ROUT PGA", NULL, "ROMIX"},
828
829 /* Output Pins */
830 {"LON", NULL, "LONMIX"},
831 {"LOP", NULL, "LOPMIX"},
832 {"OUT3", NULL, "OUT3MIX"},
833 {"LOUT", NULL, "LOUT PGA"},
834 {"SPKN", NULL, "SPKMIX"},
835 {"ROUT", NULL, "ROUT PGA"},
836 {"OUT4", NULL, "OUT4MIX"},
837 {"ROP", NULL, "ROPMIX"},
838 {"RON", NULL, "RONMIX"},
839 };
840
841 /*
842 * Clock after FLL and dividers
843 */
844 static int wm8400_set_dai_sysclk(struct snd_soc_dai *codec_dai,
845 int clk_id, unsigned int freq, int dir)
846 {
847 struct snd_soc_component *component = codec_dai->component;
848 struct wm8400_priv *wm8400 = snd_soc_component_get_drvdata(component);
849
850 wm8400->sysclk = freq;
851 return 0;
852 }
853
854 struct fll_factors {
855 u16 n;
856 u16 k;
857 u16 outdiv;
858 u16 fratio;
859 u16 freq_ref;
860 };
861
862 #define FIXED_FLL_SIZE ((1 << 16) * 10)
863
864 static int fll_factors(struct wm8400_priv *wm8400, struct fll_factors *factors,
865 unsigned int Fref, unsigned int Fout)
866 {
867 u64 Kpart;
868 unsigned int K, Nmod, target;
869
870 factors->outdiv = 2;
871 while (Fout * factors->outdiv < 90000000 ||
872 Fout * factors->outdiv > 100000000) {
873 factors->outdiv *= 2;
874 if (factors->outdiv > 32) {
875 dev_err(wm8400->wm8400->dev,
876 "Unsupported FLL output frequency %uHz\n",
877 Fout);
878 return -EINVAL;
879 }
880 }
881 target = Fout * factors->outdiv;
882 factors->outdiv = factors->outdiv >> 2;
883
884 if (Fref < 48000)
885 factors->freq_ref = 1;
886 else
887 factors->freq_ref = 0;
888
889 if (Fref < 1000000)
890 factors->fratio = 9;
891 else
892 factors->fratio = 0;
893
894 /* Ensure we have a fractional part */
895 do {
896 if (Fref < 1000000)
897 factors->fratio--;
898 else
899 factors->fratio++;
900
901 if (factors->fratio < 1 || factors->fratio > 8) {
902 dev_err(wm8400->wm8400->dev,
903 "Unable to calculate FRATIO\n");
904 return -EINVAL;
905 }
906
907 factors->n = target / (Fref * factors->fratio);
908 Nmod = target % (Fref * factors->fratio);
909 } while (Nmod == 0);
910
911 /* Calculate fractional part - scale up so we can round. */
912 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
913
914 do_div(Kpart, (Fref * factors->fratio));
915
916 K = Kpart & 0xFFFFFFFF;
917
918 if ((K % 10) >= 5)
919 K += 5;
920
921 /* Move down to proper range now rounding is done */
922 factors->k = K / 10;
923
924 dev_dbg(wm8400->wm8400->dev,
925 "FLL: Fref=%u Fout=%u N=%x K=%x, FRATIO=%x OUTDIV=%x\n",
926 Fref, Fout,
927 factors->n, factors->k, factors->fratio, factors->outdiv);
928
929 return 0;
930 }
931
932 static int wm8400_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
933 int source, unsigned int freq_in,
934 unsigned int freq_out)
935 {
936 struct snd_soc_component *component = codec_dai->component;
937 struct wm8400_priv *wm8400 = snd_soc_component_get_drvdata(component);
938 struct fll_factors factors;
939 int ret;
940 u16 reg;
941
942 if (freq_in == wm8400->fll_in && freq_out == wm8400->fll_out)
943 return 0;
944
945 if (freq_out) {
946 ret = fll_factors(wm8400, &factors, freq_in, freq_out);
947 if (ret != 0)
948 return ret;
949 } else {
950 /* Bodge GCC 4.4.0 uninitialised variable warning - it
951 * doesn't seem capable of working out that we exit if
952 * freq_out is 0 before any of the uses. */
953 memset(&factors, 0, sizeof(factors));
954 }
955
956 wm8400->fll_out = freq_out;
957 wm8400->fll_in = freq_in;
958
959 /* We *must* disable the FLL before any changes */
960 reg = snd_soc_component_read32(component, WM8400_POWER_MANAGEMENT_2);
961 reg &= ~WM8400_FLL_ENA;
962 snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_2, reg);
963
964 reg = snd_soc_component_read32(component, WM8400_FLL_CONTROL_1);
965 reg &= ~WM8400_FLL_OSC_ENA;
966 snd_soc_component_write(component, WM8400_FLL_CONTROL_1, reg);
967
968 if (!freq_out)
969 return 0;
970
971 reg &= ~(WM8400_FLL_REF_FREQ | WM8400_FLL_FRATIO_MASK);
972 reg |= WM8400_FLL_FRAC | factors.fratio;
973 reg |= factors.freq_ref << WM8400_FLL_REF_FREQ_SHIFT;
974 snd_soc_component_write(component, WM8400_FLL_CONTROL_1, reg);
975
976 snd_soc_component_write(component, WM8400_FLL_CONTROL_2, factors.k);
977 snd_soc_component_write(component, WM8400_FLL_CONTROL_3, factors.n);
978
979 reg = snd_soc_component_read32(component, WM8400_FLL_CONTROL_4);
980 reg &= ~WM8400_FLL_OUTDIV_MASK;
981 reg |= factors.outdiv;
982 snd_soc_component_write(component, WM8400_FLL_CONTROL_4, reg);
983
984 return 0;
985 }
986
987 /*
988 * Sets ADC and Voice DAC format.
989 */
990 static int wm8400_set_dai_fmt(struct snd_soc_dai *codec_dai,
991 unsigned int fmt)
992 {
993 struct snd_soc_component *component = codec_dai->component;
994 u16 audio1, audio3;
995
996 audio1 = snd_soc_component_read32(component, WM8400_AUDIO_INTERFACE_1);
997 audio3 = snd_soc_component_read32(component, WM8400_AUDIO_INTERFACE_3);
998
999 /* set master/slave audio interface */
1000 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1001 case SND_SOC_DAIFMT_CBS_CFS:
1002 audio3 &= ~WM8400_AIF_MSTR1;
1003 break;
1004 case SND_SOC_DAIFMT_CBM_CFM:
1005 audio3 |= WM8400_AIF_MSTR1;
1006 break;
1007 default:
1008 return -EINVAL;
1009 }
1010
1011 audio1 &= ~WM8400_AIF_FMT_MASK;
1012
1013 /* interface format */
1014 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1015 case SND_SOC_DAIFMT_I2S:
1016 audio1 |= WM8400_AIF_FMT_I2S;
1017 audio1 &= ~WM8400_AIF_LRCLK_INV;
1018 break;
1019 case SND_SOC_DAIFMT_RIGHT_J:
1020 audio1 |= WM8400_AIF_FMT_RIGHTJ;
1021 audio1 &= ~WM8400_AIF_LRCLK_INV;
1022 break;
1023 case SND_SOC_DAIFMT_LEFT_J:
1024 audio1 |= WM8400_AIF_FMT_LEFTJ;
1025 audio1 &= ~WM8400_AIF_LRCLK_INV;
1026 break;
1027 case SND_SOC_DAIFMT_DSP_A:
1028 audio1 |= WM8400_AIF_FMT_DSP;
1029 audio1 &= ~WM8400_AIF_LRCLK_INV;
1030 break;
1031 case SND_SOC_DAIFMT_DSP_B:
1032 audio1 |= WM8400_AIF_FMT_DSP | WM8400_AIF_LRCLK_INV;
1033 break;
1034 default:
1035 return -EINVAL;
1036 }
1037
1038 snd_soc_component_write(component, WM8400_AUDIO_INTERFACE_1, audio1);
1039 snd_soc_component_write(component, WM8400_AUDIO_INTERFACE_3, audio3);
1040 return 0;
1041 }
1042
1043 static int wm8400_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1044 int div_id, int div)
1045 {
1046 struct snd_soc_component *component = codec_dai->component;
1047 u16 reg;
1048
1049 switch (div_id) {
1050 case WM8400_MCLK_DIV:
1051 reg = snd_soc_component_read32(component, WM8400_CLOCKING_2) &
1052 ~WM8400_MCLK_DIV_MASK;
1053 snd_soc_component_write(component, WM8400_CLOCKING_2, reg | div);
1054 break;
1055 case WM8400_DACCLK_DIV:
1056 reg = snd_soc_component_read32(component, WM8400_CLOCKING_2) &
1057 ~WM8400_DAC_CLKDIV_MASK;
1058 snd_soc_component_write(component, WM8400_CLOCKING_2, reg | div);
1059 break;
1060 case WM8400_ADCCLK_DIV:
1061 reg = snd_soc_component_read32(component, WM8400_CLOCKING_2) &
1062 ~WM8400_ADC_CLKDIV_MASK;
1063 snd_soc_component_write(component, WM8400_CLOCKING_2, reg | div);
1064 break;
1065 case WM8400_BCLK_DIV:
1066 reg = snd_soc_component_read32(component, WM8400_CLOCKING_1) &
1067 ~WM8400_BCLK_DIV_MASK;
1068 snd_soc_component_write(component, WM8400_CLOCKING_1, reg | div);
1069 break;
1070 default:
1071 return -EINVAL;
1072 }
1073
1074 return 0;
1075 }
1076
1077 /*
1078 * Set PCM DAI bit size and sample rate.
1079 */
1080 static int wm8400_hw_params(struct snd_pcm_substream *substream,
1081 struct snd_pcm_hw_params *params,
1082 struct snd_soc_dai *dai)
1083 {
1084 struct snd_soc_component *component = dai->component;
1085 u16 audio1 = snd_soc_component_read32(component, WM8400_AUDIO_INTERFACE_1);
1086
1087 audio1 &= ~WM8400_AIF_WL_MASK;
1088 /* bit size */
1089 switch (params_width(params)) {
1090 case 16:
1091 break;
1092 case 20:
1093 audio1 |= WM8400_AIF_WL_20BITS;
1094 break;
1095 case 24:
1096 audio1 |= WM8400_AIF_WL_24BITS;
1097 break;
1098 case 32:
1099 audio1 |= WM8400_AIF_WL_32BITS;
1100 break;
1101 }
1102
1103 snd_soc_component_write(component, WM8400_AUDIO_INTERFACE_1, audio1);
1104 return 0;
1105 }
1106
1107 static int wm8400_mute(struct snd_soc_dai *dai, int mute)
1108 {
1109 struct snd_soc_component *component = dai->component;
1110 u16 val = snd_soc_component_read32(component, WM8400_DAC_CTRL) & ~WM8400_DAC_MUTE;
1111
1112 if (mute)
1113 snd_soc_component_write(component, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
1114 else
1115 snd_soc_component_write(component, WM8400_DAC_CTRL, val);
1116
1117 return 0;
1118 }
1119
1120 /* TODO: set bias for best performance at standby */
1121 static int wm8400_set_bias_level(struct snd_soc_component *component,
1122 enum snd_soc_bias_level level)
1123 {
1124 struct wm8400_priv *wm8400 = snd_soc_component_get_drvdata(component);
1125 u16 val;
1126 int ret;
1127
1128 switch (level) {
1129 case SND_SOC_BIAS_ON:
1130 break;
1131
1132 case SND_SOC_BIAS_PREPARE:
1133 /* VMID=2*50k */
1134 val = snd_soc_component_read32(component, WM8400_POWER_MANAGEMENT_1) &
1135 ~WM8400_VMID_MODE_MASK;
1136 snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val | 0x2);
1137 break;
1138
1139 case SND_SOC_BIAS_STANDBY:
1140 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1141 ret = regulator_bulk_enable(ARRAY_SIZE(power),
1142 &power[0]);
1143 if (ret != 0) {
1144 dev_err(wm8400->wm8400->dev,
1145 "Failed to enable regulators: %d\n",
1146 ret);
1147 return ret;
1148 }
1149
1150 snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1,
1151 WM8400_CODEC_ENA | WM8400_SYSCLK_ENA);
1152
1153 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1154 snd_soc_component_write(component, WM8400_ANTIPOP2, WM8400_SOFTST |
1155 WM8400_BUFDCOPEN | WM8400_POBCTRL);
1156
1157 msleep(50);
1158
1159 /* Enable VREF & VMID at 2x50k */
1160 val = snd_soc_component_read32(component, WM8400_POWER_MANAGEMENT_1);
1161 val |= 0x2 | WM8400_VREF_ENA;
1162 snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val);
1163
1164 /* Enable BUFIOEN */
1165 snd_soc_component_write(component, WM8400_ANTIPOP2, WM8400_SOFTST |
1166 WM8400_BUFDCOPEN | WM8400_POBCTRL |
1167 WM8400_BUFIOEN);
1168
1169 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1170 snd_soc_component_write(component, WM8400_ANTIPOP2, WM8400_BUFIOEN);
1171 }
1172
1173 /* VMID=2*300k */
1174 val = snd_soc_component_read32(component, WM8400_POWER_MANAGEMENT_1) &
1175 ~WM8400_VMID_MODE_MASK;
1176 snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val | 0x4);
1177 break;
1178
1179 case SND_SOC_BIAS_OFF:
1180 /* Enable POBCTRL and SOFT_ST */
1181 snd_soc_component_write(component, WM8400_ANTIPOP2, WM8400_SOFTST |
1182 WM8400_POBCTRL | WM8400_BUFIOEN);
1183
1184 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1185 snd_soc_component_write(component, WM8400_ANTIPOP2, WM8400_SOFTST |
1186 WM8400_BUFDCOPEN | WM8400_POBCTRL |
1187 WM8400_BUFIOEN);
1188
1189 /* mute DAC */
1190 val = snd_soc_component_read32(component, WM8400_DAC_CTRL);
1191 snd_soc_component_write(component, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
1192
1193 /* Enable any disabled outputs */
1194 val = snd_soc_component_read32(component, WM8400_POWER_MANAGEMENT_1);
1195 val |= WM8400_SPK_ENA | WM8400_OUT3_ENA |
1196 WM8400_OUT4_ENA | WM8400_LOUT_ENA |
1197 WM8400_ROUT_ENA;
1198 snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val);
1199
1200 /* Disable VMID */
1201 val &= ~WM8400_VMID_MODE_MASK;
1202 snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val);
1203
1204 msleep(300);
1205
1206 /* Enable all output discharge bits */
1207 snd_soc_component_write(component, WM8400_ANTIPOP1, WM8400_DIS_LLINE |
1208 WM8400_DIS_RLINE | WM8400_DIS_OUT3 |
1209 WM8400_DIS_OUT4 | WM8400_DIS_LOUT |
1210 WM8400_DIS_ROUT);
1211
1212 /* Disable VREF */
1213 val &= ~WM8400_VREF_ENA;
1214 snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, val);
1215
1216 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1217 snd_soc_component_write(component, WM8400_ANTIPOP2, 0x0);
1218
1219 ret = regulator_bulk_disable(ARRAY_SIZE(power),
1220 &power[0]);
1221 if (ret != 0)
1222 return ret;
1223
1224 break;
1225 }
1226
1227 return 0;
1228 }
1229
1230 #define WM8400_RATES SNDRV_PCM_RATE_8000_96000
1231
1232 #define WM8400_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1233 SNDRV_PCM_FMTBIT_S24_LE)
1234
1235 static const struct snd_soc_dai_ops wm8400_dai_ops = {
1236 .hw_params = wm8400_hw_params,
1237 .digital_mute = wm8400_mute,
1238 .set_fmt = wm8400_set_dai_fmt,
1239 .set_clkdiv = wm8400_set_dai_clkdiv,
1240 .set_sysclk = wm8400_set_dai_sysclk,
1241 .set_pll = wm8400_set_dai_pll,
1242 };
1243
1244 /*
1245 * The WM8400 supports 2 different and mutually exclusive DAI
1246 * configurations.
1247 *
1248 * 1. ADC/DAC on Primary Interface
1249 * 2. ADC on Primary Interface/DAC on secondary
1250 */
1251 static struct snd_soc_dai_driver wm8400_dai = {
1252 /* ADC/DAC on primary */
1253 .name = "wm8400-hifi",
1254 .playback = {
1255 .stream_name = "Playback",
1256 .channels_min = 1,
1257 .channels_max = 2,
1258 .rates = WM8400_RATES,
1259 .formats = WM8400_FORMATS,
1260 },
1261 .capture = {
1262 .stream_name = "Capture",
1263 .channels_min = 1,
1264 .channels_max = 2,
1265 .rates = WM8400_RATES,
1266 .formats = WM8400_FORMATS,
1267 },
1268 .ops = &wm8400_dai_ops,
1269 };
1270
1271 static int wm8400_component_probe(struct snd_soc_component *component)
1272 {
1273 struct wm8400 *wm8400 = dev_get_platdata(component->dev);
1274 struct wm8400_priv *priv;
1275 int ret;
1276 u16 reg;
1277
1278 priv = devm_kzalloc(component->dev, sizeof(struct wm8400_priv),
1279 GFP_KERNEL);
1280 if (priv == NULL)
1281 return -ENOMEM;
1282
1283 snd_soc_component_init_regmap(component, wm8400->regmap);
1284 snd_soc_component_set_drvdata(component, priv);
1285 priv->wm8400 = wm8400;
1286
1287 ret = devm_regulator_bulk_get(wm8400->dev,
1288 ARRAY_SIZE(power), &power[0]);
1289 if (ret != 0) {
1290 dev_err(component->dev, "Failed to get regulators: %d\n", ret);
1291 return ret;
1292 }
1293
1294 wm8400_component_reset(component);
1295
1296 reg = snd_soc_component_read32(component, WM8400_POWER_MANAGEMENT_1);
1297 snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1, reg | WM8400_CODEC_ENA);
1298
1299 /* Latch volume update bits */
1300 reg = snd_soc_component_read32(component, WM8400_LEFT_LINE_INPUT_1_2_VOLUME);
1301 snd_soc_component_write(component, WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
1302 reg & WM8400_IPVU);
1303 reg = snd_soc_component_read32(component, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME);
1304 snd_soc_component_write(component, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
1305 reg & WM8400_IPVU);
1306
1307 snd_soc_component_write(component, WM8400_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1308 snd_soc_component_write(component, WM8400_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
1309
1310 return 0;
1311 }
1312
1313 static void wm8400_component_remove(struct snd_soc_component *component)
1314 {
1315 u16 reg;
1316
1317 reg = snd_soc_component_read32(component, WM8400_POWER_MANAGEMENT_1);
1318 snd_soc_component_write(component, WM8400_POWER_MANAGEMENT_1,
1319 reg & (~WM8400_CODEC_ENA));
1320 }
1321
1322 static const struct snd_soc_component_driver soc_component_dev_wm8400 = {
1323 .probe = wm8400_component_probe,
1324 .remove = wm8400_component_remove,
1325 .set_bias_level = wm8400_set_bias_level,
1326 .controls = wm8400_snd_controls,
1327 .num_controls = ARRAY_SIZE(wm8400_snd_controls),
1328 .dapm_widgets = wm8400_dapm_widgets,
1329 .num_dapm_widgets = ARRAY_SIZE(wm8400_dapm_widgets),
1330 .dapm_routes = wm8400_dapm_routes,
1331 .num_dapm_routes = ARRAY_SIZE(wm8400_dapm_routes),
1332 .suspend_bias_off = 1,
1333 .idle_bias_on = 1,
1334 .use_pmdown_time = 1,
1335 .endianness = 1,
1336 .non_legacy_dai_naming = 1,
1337 };
1338
1339 static int wm8400_probe(struct platform_device *pdev)
1340 {
1341 return devm_snd_soc_register_component(&pdev->dev,
1342 &soc_component_dev_wm8400,
1343 &wm8400_dai, 1);
1344 }
1345
1346 static struct platform_driver wm8400_codec_driver = {
1347 .driver = {
1348 .name = "wm8400-codec",
1349 },
1350 .probe = wm8400_probe,
1351 };
1352
1353 module_platform_driver(wm8400_codec_driver);
1354
1355 MODULE_DESCRIPTION("ASoC WM8400 driver");
1356 MODULE_AUTHOR("Mark Brown");
1357 MODULE_LICENSE("GPL");
1358 MODULE_ALIAS("platform:wm8400-codec");
Linux with added FPC-III support