2 * Copyright (C) 2012 Altera Corporation
3 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
5 * Modified from mach-picoxcell/time.c
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/dw_apb_timer.h>
21 #include <linux/of_address.h>
22 #include <linux/of_irq.h>
23 #include <linux/clk.h>
24 #include <linux/sched_clock.h>
26 static void __init
timer_get_base_and_rate(struct device_node
*np
,
27 void __iomem
**base
, u32
*rate
)
29 struct clk
*timer_clk
;
32 *base
= of_iomap(np
, 0);
35 panic("Unable to map regs for %s", np
->name
);
38 * Not all implementations use a periphal clock, so don't panic
41 pclk
= of_clk_get_by_name(np
, "pclk");
43 if (clk_prepare_enable(pclk
))
44 pr_warn("pclk for %s is present, but could not be activated\n",
47 timer_clk
= of_clk_get_by_name(np
, "timer");
48 if (IS_ERR(timer_clk
))
51 if (!clk_prepare_enable(timer_clk
)) {
52 *rate
= clk_get_rate(timer_clk
);
57 if (of_property_read_u32(np
, "clock-freq", rate
) &&
58 of_property_read_u32(np
, "clock-frequency", rate
))
59 panic("No clock nor clock-frequency property for %s", np
->name
);
62 static void __init
add_clockevent(struct device_node
*event_timer
)
65 struct dw_apb_clock_event_device
*ced
;
68 irq
= irq_of_parse_and_map(event_timer
, 0);
70 panic("No IRQ for clock event timer");
72 timer_get_base_and_rate(event_timer
, &iobase
, &rate
);
74 ced
= dw_apb_clockevent_init(0, event_timer
->name
, 300, iobase
, irq
,
77 panic("Unable to initialise clockevent device");
79 dw_apb_clockevent_register(ced
);
82 static void __iomem
*sched_io_base
;
83 static u32 sched_rate
;
85 static void __init
add_clocksource(struct device_node
*source_timer
)
88 struct dw_apb_clocksource
*cs
;
91 timer_get_base_and_rate(source_timer
, &iobase
, &rate
);
93 cs
= dw_apb_clocksource_init(300, source_timer
->name
, iobase
, rate
);
95 panic("Unable to initialise clocksource device");
97 dw_apb_clocksource_start(cs
);
98 dw_apb_clocksource_register(cs
);
101 * Fallback to use the clocksource as sched_clock if no separate
102 * timer is found. sched_io_base then points to the current_value
103 * register of the clocksource timer.
105 sched_io_base
= iobase
+ 0x04;
109 static u64 notrace
read_sched_clock(void)
111 return ~__raw_readl(sched_io_base
);
114 static const struct of_device_id sptimer_ids
[] __initconst
= {
115 { .compatible
= "picochip,pc3x2-rtc" },
119 static void __init
init_sched_clock(void)
121 struct device_node
*sched_timer
;
123 sched_timer
= of_find_matching_node(NULL
, sptimer_ids
);
125 timer_get_base_and_rate(sched_timer
, &sched_io_base
,
127 of_node_put(sched_timer
);
130 sched_clock_register(read_sched_clock
, 32, sched_rate
);
133 static int num_called
;
134 static void __init
dw_apb_timer_init(struct device_node
*timer
)
136 switch (num_called
) {
138 pr_debug("%s: found clockevent timer\n", __func__
);
139 add_clockevent(timer
);
142 pr_debug("%s: found clocksource timer\n", __func__
);
143 add_clocksource(timer
);
152 CLOCKSOURCE_OF_DECLARE(pc3x2_timer
, "picochip,pc3x2-timer", dw_apb_timer_init
);
153 CLOCKSOURCE_OF_DECLARE(apb_timer_osc
, "snps,dw-apb-timer-osc", dw_apb_timer_init
);
154 CLOCKSOURCE_OF_DECLARE(apb_timer_sp
, "snps,dw-apb-timer-sp", dw_apb_timer_init
);
155 CLOCKSOURCE_OF_DECLARE(apb_timer
, "snps,dw-apb-timer", dw_apb_timer_init
);