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crypto: keywrap - memzero the correct memory
[linux/fpc-iii.git] / drivers / thermal / samsung / exynos_tmu.c
blobfa61eff88496e541334043f5457f1f989dd7e480
1 /*
2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
3 *
4 * Copyright (C) 2014 Samsung Electronics
5 * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
6 * Lukasz Majewski <l.majewski@samsung.com>
7 *
8 * Copyright (C) 2011 Samsung Electronics
9 * Donggeun Kim <dg77.kim@samsung.com>
10 * Amit Daniel Kachhap <amit.kachhap@linaro.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
28 #include <linux/clk.h>
29 #include <linux/io.h>
30 #include <linux/interrupt.h>
31 #include <linux/module.h>
32 #include <linux/of.h>
33 #include <linux/of_address.h>
34 #include <linux/of_irq.h>
35 #include <linux/platform_device.h>
36 #include <linux/regulator/consumer.h>
37
38 #include "exynos_tmu.h"
39 #include "../thermal_core.h"
40
41 /* Exynos generic registers */
42 #define EXYNOS_TMU_REG_TRIMINFO 0x0
43 #define EXYNOS_TMU_REG_CONTROL 0x20
44 #define EXYNOS_TMU_REG_STATUS 0x28
45 #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
46 #define EXYNOS_TMU_REG_INTEN 0x70
47 #define EXYNOS_TMU_REG_INTSTAT 0x74
48 #define EXYNOS_TMU_REG_INTCLEAR 0x78
49
50 #define EXYNOS_TMU_TEMP_MASK 0xff
51 #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
52 #define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f
53 #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf
54 #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8
55 #define EXYNOS_TMU_CORE_EN_SHIFT 0
56
57 /* Exynos3250 specific registers */
58 #define EXYNOS_TMU_TRIMINFO_CON1 0x10
59
60 /* Exynos4210 specific registers */
61 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
62 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
63
64 /* Exynos5250, Exynos4412, Exynos3250 specific registers */
65 #define EXYNOS_TMU_TRIMINFO_CON2 0x14
66 #define EXYNOS_THD_TEMP_RISE 0x50
67 #define EXYNOS_THD_TEMP_FALL 0x54
68 #define EXYNOS_EMUL_CON 0x80
69
70 #define EXYNOS_TRIMINFO_RELOAD_ENABLE 1
71 #define EXYNOS_TRIMINFO_25_SHIFT 0
72 #define EXYNOS_TRIMINFO_85_SHIFT 8
73 #define EXYNOS_TMU_TRIP_MODE_SHIFT 13
74 #define EXYNOS_TMU_TRIP_MODE_MASK 0x7
75 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12
76
77 #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0
78 #define EXYNOS_TMU_INTEN_RISE1_SHIFT 4
79 #define EXYNOS_TMU_INTEN_RISE2_SHIFT 8
80 #define EXYNOS_TMU_INTEN_RISE3_SHIFT 12
81 #define EXYNOS_TMU_INTEN_FALL0_SHIFT 16
82
83 #define EXYNOS_EMUL_TIME 0x57F0
84 #define EXYNOS_EMUL_TIME_MASK 0xffff
85 #define EXYNOS_EMUL_TIME_SHIFT 16
86 #define EXYNOS_EMUL_DATA_SHIFT 8
87 #define EXYNOS_EMUL_DATA_MASK 0xFF
88 #define EXYNOS_EMUL_ENABLE 0x1
89
90 /* Exynos5260 specific */
91 #define EXYNOS5260_TMU_REG_INTEN 0xC0
92 #define EXYNOS5260_TMU_REG_INTSTAT 0xC4
93 #define EXYNOS5260_TMU_REG_INTCLEAR 0xC8
94 #define EXYNOS5260_EMUL_CON 0x100
95
96 /* Exynos4412 specific */
97 #define EXYNOS4412_MUX_ADDR_VALUE 6
98 #define EXYNOS4412_MUX_ADDR_SHIFT 20
99
100 /* Exynos5433 specific registers */
101 #define EXYNOS5433_TMU_REG_CONTROL1 0x024
102 #define EXYNOS5433_TMU_SAMPLING_INTERVAL 0x02c
103 #define EXYNOS5433_TMU_COUNTER_VALUE0 0x030
104 #define EXYNOS5433_TMU_COUNTER_VALUE1 0x034
105 #define EXYNOS5433_TMU_REG_CURRENT_TEMP1 0x044
106 #define EXYNOS5433_THD_TEMP_RISE3_0 0x050
107 #define EXYNOS5433_THD_TEMP_RISE7_4 0x054
108 #define EXYNOS5433_THD_TEMP_FALL3_0 0x060
109 #define EXYNOS5433_THD_TEMP_FALL7_4 0x064
110 #define EXYNOS5433_TMU_REG_INTEN 0x0c0
111 #define EXYNOS5433_TMU_REG_INTPEND 0x0c8
112 #define EXYNOS5433_TMU_EMUL_CON 0x110
113 #define EXYNOS5433_TMU_PD_DET_EN 0x130
114
115 #define EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT 16
116 #define EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT 23
117 #define EXYNOS5433_TRIMINFO_SENSOR_ID_MASK \
118 (0xf << EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT)
119 #define EXYNOS5433_TRIMINFO_CALIB_SEL_MASK BIT(23)
120
121 #define EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING 0
122 #define EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING 1
123
124 #define EXYNOS5433_PD_DET_EN 1
125
126 /*exynos5440 specific registers*/
127 #define EXYNOS5440_TMU_S0_7_TRIM 0x000
128 #define EXYNOS5440_TMU_S0_7_CTRL 0x020
129 #define EXYNOS5440_TMU_S0_7_DEBUG 0x040
130 #define EXYNOS5440_TMU_S0_7_TEMP 0x0f0
131 #define EXYNOS5440_TMU_S0_7_TH0 0x110
132 #define EXYNOS5440_TMU_S0_7_TH1 0x130
133 #define EXYNOS5440_TMU_S0_7_TH2 0x150
134 #define EXYNOS5440_TMU_S0_7_IRQEN 0x210
135 #define EXYNOS5440_TMU_S0_7_IRQ 0x230
136 /* exynos5440 common registers */
137 #define EXYNOS5440_TMU_IRQ_STATUS 0x000
138 #define EXYNOS5440_TMU_PMIN 0x004
139
140 #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0
141 #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1
142 #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2
143 #define EXYNOS5440_TMU_INTEN_RISE3_SHIFT 3
144 #define EXYNOS5440_TMU_INTEN_FALL0_SHIFT 4
145 #define EXYNOS5440_TMU_TH_RISE4_SHIFT 24
146 #define EXYNOS5440_EFUSE_SWAP_OFFSET 8
147
148 /* Exynos7 specific registers */
149 #define EXYNOS7_THD_TEMP_RISE7_6 0x50
150 #define EXYNOS7_THD_TEMP_FALL7_6 0x60
151 #define EXYNOS7_TMU_REG_INTEN 0x110
152 #define EXYNOS7_TMU_REG_INTPEND 0x118
153 #define EXYNOS7_TMU_REG_EMUL_CON 0x160
154
155 #define EXYNOS7_TMU_TEMP_MASK 0x1ff
156 #define EXYNOS7_PD_DET_EN_SHIFT 23
157 #define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0
158 #define EXYNOS7_TMU_INTEN_RISE1_SHIFT 1
159 #define EXYNOS7_TMU_INTEN_RISE2_SHIFT 2
160 #define EXYNOS7_TMU_INTEN_RISE3_SHIFT 3
161 #define EXYNOS7_TMU_INTEN_RISE4_SHIFT 4
162 #define EXYNOS7_TMU_INTEN_RISE5_SHIFT 5
163 #define EXYNOS7_TMU_INTEN_RISE6_SHIFT 6
164 #define EXYNOS7_TMU_INTEN_RISE7_SHIFT 7
165 #define EXYNOS7_EMUL_DATA_SHIFT 7
166 #define EXYNOS7_EMUL_DATA_MASK 0x1ff
167
168 #define MCELSIUS 1000
169 /**
170 * struct exynos_tmu_data : A structure to hold the private data of the TMU
171 driver
172 * @id: identifier of the one instance of the TMU controller.
173 * @pdata: pointer to the tmu platform/configuration data
174 * @base: base address of the single instance of the TMU controller.
175 * @base_second: base address of the common registers of the TMU controller.
176 * @irq: irq number of the TMU controller.
177 * @soc: id of the SOC type.
178 * @irq_work: pointer to the irq work structure.
179 * @lock: lock to implement synchronization.
180 * @clk: pointer to the clock structure.
181 * @clk_sec: pointer to the clock structure for accessing the base_second.
182 * @sclk: pointer to the clock structure for accessing the tmu special clk.
183 * @temp_error1: fused value of the first point trim.
184 * @temp_error2: fused value of the second point trim.
185 * @regulator: pointer to the TMU regulator structure.
186 * @reg_conf: pointer to structure to register with core thermal.
187 * @tmu_initialize: SoC specific TMU initialization method
188 * @tmu_control: SoC specific TMU control method
189 * @tmu_read: SoC specific TMU temperature read method
190 * @tmu_set_emulation: SoC specific TMU emulation setting method
191 * @tmu_clear_irqs: SoC specific TMU interrupts clearing method
192 */
193 struct exynos_tmu_data {
194 int id;
195 struct exynos_tmu_platform_data *pdata;
196 void __iomem *base;
197 void __iomem *base_second;
198 int irq;
199 enum soc_type soc;
200 struct work_struct irq_work;
201 struct mutex lock;
202 struct clk *clk, *clk_sec, *sclk;
203 u16 temp_error1, temp_error2;
204 struct regulator *regulator;
205 struct thermal_zone_device *tzd;
206
207 int (*tmu_initialize)(struct platform_device *pdev);
208 void (*tmu_control)(struct platform_device *pdev, bool on);
209 int (*tmu_read)(struct exynos_tmu_data *data);
210 void (*tmu_set_emulation)(struct exynos_tmu_data *data, int temp);
211 void (*tmu_clear_irqs)(struct exynos_tmu_data *data);
212 };
213
214 static void exynos_report_trigger(struct exynos_tmu_data *p)
215 {
216 char data[10], *envp[] = { data, NULL };
217 struct thermal_zone_device *tz = p->tzd;
218 int temp;
219 unsigned int i;
220
221 if (!tz) {
222 pr_err("No thermal zone device defined\n");
223 return;
224 }
225
226 thermal_zone_device_update(tz);
227
228 mutex_lock(&tz->lock);
229 /* Find the level for which trip happened */
230 for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
231 tz->ops->get_trip_temp(tz, i, &temp);
232 if (tz->last_temperature < temp)
233 break;
234 }
235
236 snprintf(data, sizeof(data), "%u", i);
237 kobject_uevent_env(&tz->device.kobj, KOBJ_CHANGE, envp);
238 mutex_unlock(&tz->lock);
239 }
240
241 /*
242 * TMU treats temperature as a mapped temperature code.
243 * The temperature is converted differently depending on the calibration type.
244 */
245 static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
246 {
247 struct exynos_tmu_platform_data *pdata = data->pdata;
248 int temp_code;
249
250 switch (pdata->cal_type) {
251 case TYPE_TWO_POINT_TRIMMING:
252 temp_code = (temp - pdata->first_point_trim) *
253 (data->temp_error2 - data->temp_error1) /
254 (pdata->second_point_trim - pdata->first_point_trim) +
255 data->temp_error1;
256 break;
257 case TYPE_ONE_POINT_TRIMMING:
258 temp_code = temp + data->temp_error1 - pdata->first_point_trim;
259 break;
260 default:
261 temp_code = temp + pdata->default_temp_offset;
262 break;
263 }
264
265 return temp_code;
266 }
267
268 /*
269 * Calculate a temperature value from a temperature code.
270 * The unit of the temperature is degree Celsius.
271 */
272 static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code)
273 {
274 struct exynos_tmu_platform_data *pdata = data->pdata;
275 int temp;
276
277 switch (pdata->cal_type) {
278 case TYPE_TWO_POINT_TRIMMING:
279 temp = (temp_code - data->temp_error1) *
280 (pdata->second_point_trim - pdata->first_point_trim) /
281 (data->temp_error2 - data->temp_error1) +
282 pdata->first_point_trim;
283 break;
284 case TYPE_ONE_POINT_TRIMMING:
285 temp = temp_code - data->temp_error1 + pdata->first_point_trim;
286 break;
287 default:
288 temp = temp_code - pdata->default_temp_offset;
289 break;
290 }
291
292 return temp;
293 }
294
295 static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info)
296 {
297 struct exynos_tmu_platform_data *pdata = data->pdata;
298
299 data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
300 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
301 EXYNOS_TMU_TEMP_MASK);
302
303 if (!data->temp_error1 ||
304 (pdata->min_efuse_value > data->temp_error1) ||
305 (data->temp_error1 > pdata->max_efuse_value))
306 data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK;
307
308 if (!data->temp_error2)
309 data->temp_error2 =
310 (pdata->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
311 EXYNOS_TMU_TEMP_MASK;
312 }
313
314 static u32 get_th_reg(struct exynos_tmu_data *data, u32 threshold, bool falling)
315 {
316 struct thermal_zone_device *tz = data->tzd;
317 const struct thermal_trip * const trips =
318 of_thermal_get_trip_points(tz);
319 unsigned long temp;
320 int i;
321
322 if (!trips) {
323 pr_err("%s: Cannot get trip points from of-thermal.c!\n",
324 __func__);
325 return 0;
326 }
327
328 for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
329 if (trips[i].type == THERMAL_TRIP_CRITICAL)
330 continue;
331
332 temp = trips[i].temperature / MCELSIUS;
333 if (falling)
334 temp -= (trips[i].hysteresis / MCELSIUS);
335 else
336 threshold &= ~(0xff << 8 * i);
337
338 threshold |= temp_to_code(data, temp) << 8 * i;
339 }
340
341 return threshold;
342 }
343
344 static int exynos_tmu_initialize(struct platform_device *pdev)
345 {
346 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
347 int ret;
348
349 mutex_lock(&data->lock);
350 clk_enable(data->clk);
351 if (!IS_ERR(data->clk_sec))
352 clk_enable(data->clk_sec);
353 ret = data->tmu_initialize(pdev);
354 clk_disable(data->clk);
355 mutex_unlock(&data->lock);
356 if (!IS_ERR(data->clk_sec))
357 clk_disable(data->clk_sec);
358
359 return ret;
360 }
361
362 static u32 get_con_reg(struct exynos_tmu_data *data, u32 con)
363 {
364 struct exynos_tmu_platform_data *pdata = data->pdata;
365
366 if (data->soc == SOC_ARCH_EXYNOS4412 ||
367 data->soc == SOC_ARCH_EXYNOS3250)
368 con |= (EXYNOS4412_MUX_ADDR_VALUE << EXYNOS4412_MUX_ADDR_SHIFT);
369
370 con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT);
371 con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT;
372
373 con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
374 con |= (pdata->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
375
376 if (pdata->noise_cancel_mode) {
377 con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT);
378 con |= (pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT);
379 }
380
381 return con;
382 }
383
384 static void exynos_tmu_control(struct platform_device *pdev, bool on)
385 {
386 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
387
388 mutex_lock(&data->lock);
389 clk_enable(data->clk);
390 data->tmu_control(pdev, on);
391 clk_disable(data->clk);
392 mutex_unlock(&data->lock);
393 }
394
395 static int exynos4210_tmu_initialize(struct platform_device *pdev)
396 {
397 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
398 struct thermal_zone_device *tz = data->tzd;
399 const struct thermal_trip * const trips =
400 of_thermal_get_trip_points(tz);
401 int ret = 0, threshold_code, i;
402 unsigned long reference, temp;
403 unsigned int status;
404
405 if (!trips) {
406 pr_err("%s: Cannot get trip points from of-thermal.c!\n",
407 __func__);
408 ret = -ENODEV;
409 goto out;
410 }
411
412 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
413 if (!status) {
414 ret = -EBUSY;
415 goto out;
416 }
417
418 sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO));
419
420 /* Write temperature code for threshold */
421 reference = trips[0].temperature / MCELSIUS;
422 threshold_code = temp_to_code(data, reference);
423 if (threshold_code < 0) {
424 ret = threshold_code;
425 goto out;
426 }
427 writeb(threshold_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
428
429 for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
430 temp = trips[i].temperature / MCELSIUS;
431 writeb(temp - reference, data->base +
432 EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4);
433 }
434
435 data->tmu_clear_irqs(data);
436 out:
437 return ret;
438 }
439
440 static int exynos4412_tmu_initialize(struct platform_device *pdev)
441 {
442 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
443 const struct thermal_trip * const trips =
444 of_thermal_get_trip_points(data->tzd);
445 unsigned int status, trim_info, con, ctrl, rising_threshold;
446 int ret = 0, threshold_code, i;
447 unsigned long crit_temp = 0;
448
449 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
450 if (!status) {
451 ret = -EBUSY;
452 goto out;
453 }
454
455 if (data->soc == SOC_ARCH_EXYNOS3250 ||
456 data->soc == SOC_ARCH_EXYNOS4412 ||
457 data->soc == SOC_ARCH_EXYNOS5250) {
458 if (data->soc == SOC_ARCH_EXYNOS3250) {
459 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1);
460 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
461 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1);
462 }
463 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2);
464 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
465 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2);
466 }
467
468 /* On exynos5420 the triminfo register is in the shared space */
469 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
470 trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO);
471 else
472 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
473
474 sanitize_temp_error(data, trim_info);
475
476 /* Write temperature code for rising and falling threshold */
477 rising_threshold = readl(data->base + EXYNOS_THD_TEMP_RISE);
478 rising_threshold = get_th_reg(data, rising_threshold, false);
479 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
480 writel(get_th_reg(data, 0, true), data->base + EXYNOS_THD_TEMP_FALL);
481
482 data->tmu_clear_irqs(data);
483
484 /* if last threshold limit is also present */
485 for (i = 0; i < of_thermal_get_ntrips(data->tzd); i++) {
486 if (trips[i].type == THERMAL_TRIP_CRITICAL) {
487 crit_temp = trips[i].temperature;
488 break;
489 }
490 }
491
492 if (i == of_thermal_get_ntrips(data->tzd)) {
493 pr_err("%s: No CRITICAL trip point defined at of-thermal.c!\n",
494 __func__);
495 ret = -EINVAL;
496 goto out;
497 }
498
499 threshold_code = temp_to_code(data, crit_temp / MCELSIUS);
500 /* 1-4 level to be assigned in th0 reg */
501 rising_threshold &= ~(0xff << 8 * i);
502 rising_threshold |= threshold_code << 8 * i;
503 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
504 con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
505 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
506 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
507
508 out:
509 return ret;
510 }
511
512 static int exynos5433_tmu_initialize(struct platform_device *pdev)
513 {
514 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
515 struct exynos_tmu_platform_data *pdata = data->pdata;
516 struct thermal_zone_device *tz = data->tzd;
517 unsigned int status, trim_info;
518 unsigned int rising_threshold = 0, falling_threshold = 0;
519 int temp, temp_hist;
520 int ret = 0, threshold_code, i, sensor_id, cal_type;
521
522 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
523 if (!status) {
524 ret = -EBUSY;
525 goto out;
526 }
527
528 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
529 sanitize_temp_error(data, trim_info);
530
531 /* Read the temperature sensor id */
532 sensor_id = (trim_info & EXYNOS5433_TRIMINFO_SENSOR_ID_MASK)
533 >> EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT;
534 dev_info(&pdev->dev, "Temperature sensor ID: 0x%x\n", sensor_id);
535
536 /* Read the calibration mode */
537 writel(trim_info, data->base + EXYNOS_TMU_REG_TRIMINFO);
538 cal_type = (trim_info & EXYNOS5433_TRIMINFO_CALIB_SEL_MASK)
539 >> EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT;
540
541 switch (cal_type) {
542 case EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING:
543 pdata->cal_type = TYPE_ONE_POINT_TRIMMING;
544 break;
545 case EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING:
546 pdata->cal_type = TYPE_TWO_POINT_TRIMMING;
547 break;
548 default:
549 pdata->cal_type = TYPE_ONE_POINT_TRIMMING;
550 break;
551 }
552
553 dev_info(&pdev->dev, "Calibration type is %d-point calibration\n",
554 cal_type ? 2 : 1);
555
556 /* Write temperature code for rising and falling threshold */
557 for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
558 int rising_reg_offset, falling_reg_offset;
559 int j = 0;
560
561 switch (i) {
562 case 0:
563 case 1:
564 case 2:
565 case 3:
566 rising_reg_offset = EXYNOS5433_THD_TEMP_RISE3_0;
567 falling_reg_offset = EXYNOS5433_THD_TEMP_FALL3_0;
568 j = i;
569 break;
570 case 4:
571 case 5:
572 case 6:
573 case 7:
574 rising_reg_offset = EXYNOS5433_THD_TEMP_RISE7_4;
575 falling_reg_offset = EXYNOS5433_THD_TEMP_FALL7_4;
576 j = i - 4;
577 break;
578 default:
579 continue;
580 }
581
582 /* Write temperature code for rising threshold */
583 tz->ops->get_trip_temp(tz, i, &temp);
584 temp /= MCELSIUS;
585 threshold_code = temp_to_code(data, temp);
586
587 rising_threshold = readl(data->base + rising_reg_offset);
588 rising_threshold |= (threshold_code << j * 8);
589 writel(rising_threshold, data->base + rising_reg_offset);
590
591 /* Write temperature code for falling threshold */
592 tz->ops->get_trip_hyst(tz, i, &temp_hist);
593 temp_hist = temp - (temp_hist / MCELSIUS);
594 threshold_code = temp_to_code(data, temp_hist);
595
596 falling_threshold = readl(data->base + falling_reg_offset);
597 falling_threshold &= ~(0xff << j * 8);
598 falling_threshold |= (threshold_code << j * 8);
599 writel(falling_threshold, data->base + falling_reg_offset);
600 }
601
602 data->tmu_clear_irqs(data);
603 out:
604 return ret;
605 }
606
607 static int exynos5440_tmu_initialize(struct platform_device *pdev)
608 {
609 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
610 unsigned int trim_info = 0, con, rising_threshold;
611 int threshold_code;
612 int crit_temp = 0;
613
614 /*
615 * For exynos5440 soc triminfo value is swapped between TMU0 and
616 * TMU2, so the below logic is needed.
617 */
618 switch (data->id) {
619 case 0:
620 trim_info = readl(data->base + EXYNOS5440_EFUSE_SWAP_OFFSET +
621 EXYNOS5440_TMU_S0_7_TRIM);
622 break;
623 case 1:
624 trim_info = readl(data->base + EXYNOS5440_TMU_S0_7_TRIM);
625 break;
626 case 2:
627 trim_info = readl(data->base - EXYNOS5440_EFUSE_SWAP_OFFSET +
628 EXYNOS5440_TMU_S0_7_TRIM);
629 }
630 sanitize_temp_error(data, trim_info);
631
632 /* Write temperature code for rising and falling threshold */
633 rising_threshold = readl(data->base + EXYNOS5440_TMU_S0_7_TH0);
634 rising_threshold = get_th_reg(data, rising_threshold, false);
635 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH0);
636 writel(0, data->base + EXYNOS5440_TMU_S0_7_TH1);
637
638 data->tmu_clear_irqs(data);
639
640 /* if last threshold limit is also present */
641 if (!data->tzd->ops->get_crit_temp(data->tzd, &crit_temp)) {
642 threshold_code = temp_to_code(data, crit_temp / MCELSIUS);
643 /* 5th level to be assigned in th2 reg */
644 rising_threshold =
645 threshold_code << EXYNOS5440_TMU_TH_RISE4_SHIFT;
646 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH2);
647 con = readl(data->base + EXYNOS5440_TMU_S0_7_CTRL);
648 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
649 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
650 }
651 /* Clear the PMIN in the common TMU register */
652 if (!data->id)
653 writel(0, data->base_second + EXYNOS5440_TMU_PMIN);
654
655 return 0;
656 }
657
658 static int exynos7_tmu_initialize(struct platform_device *pdev)
659 {
660 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
661 struct thermal_zone_device *tz = data->tzd;
662 struct exynos_tmu_platform_data *pdata = data->pdata;
663 unsigned int status, trim_info;
664 unsigned int rising_threshold = 0, falling_threshold = 0;
665 int ret = 0, threshold_code, i;
666 int temp, temp_hist;
667 unsigned int reg_off, bit_off;
668
669 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
670 if (!status) {
671 ret = -EBUSY;
672 goto out;
673 }
674
675 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
676
677 data->temp_error1 = trim_info & EXYNOS7_TMU_TEMP_MASK;
678 if (!data->temp_error1 ||
679 (pdata->min_efuse_value > data->temp_error1) ||
680 (data->temp_error1 > pdata->max_efuse_value))
681 data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK;
682
683 /* Write temperature code for rising and falling threshold */
684 for (i = (of_thermal_get_ntrips(tz) - 1); i >= 0; i--) {
685 /*
686 * On exynos7 there are 4 rising and 4 falling threshold
687 * registers (0x50-0x5c and 0x60-0x6c respectively). Each
688 * register holds the value of two threshold levels (at bit
689 * offsets 0 and 16). Based on the fact that there are atmost
690 * eight possible trigger levels, calculate the register and
691 * bit offsets where the threshold levels are to be written.
692 *
693 * e.g. EXYNOS7_THD_TEMP_RISE7_6 (0x50)
694 * [24:16] - Threshold level 7
695 * [8:0] - Threshold level 6
696 * e.g. EXYNOS7_THD_TEMP_RISE5_4 (0x54)
697 * [24:16] - Threshold level 5
698 * [8:0] - Threshold level 4
699 *
700 * and similarly for falling thresholds.
701 *
702 * Based on the above, calculate the register and bit offsets
703 * for rising/falling threshold levels and populate them.
704 */
705 reg_off = ((7 - i) / 2) * 4;
706 bit_off = ((8 - i) % 2);
707
708 tz->ops->get_trip_temp(tz, i, &temp);
709 temp /= MCELSIUS;
710
711 tz->ops->get_trip_hyst(tz, i, &temp_hist);
712 temp_hist = temp - (temp_hist / MCELSIUS);
713
714 /* Set 9-bit temperature code for rising threshold levels */
715 threshold_code = temp_to_code(data, temp);
716 rising_threshold = readl(data->base +
717 EXYNOS7_THD_TEMP_RISE7_6 + reg_off);
718 rising_threshold &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off));
719 rising_threshold |= threshold_code << (16 * bit_off);
720 writel(rising_threshold,
721 data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off);
722
723 /* Set 9-bit temperature code for falling threshold levels */
724 threshold_code = temp_to_code(data, temp_hist);
725 falling_threshold &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off));
726 falling_threshold |= threshold_code << (16 * bit_off);
727 writel(falling_threshold,
728 data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off);
729 }
730
731 data->tmu_clear_irqs(data);
732 out:
733 return ret;
734 }
735
736 static void exynos4210_tmu_control(struct platform_device *pdev, bool on)
737 {
738 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
739 struct thermal_zone_device *tz = data->tzd;
740 unsigned int con, interrupt_en;
741
742 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
743
744 if (on) {
745 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
746 interrupt_en =
747 (of_thermal_is_trip_valid(tz, 3)
748 << EXYNOS_TMU_INTEN_RISE3_SHIFT) |
749 (of_thermal_is_trip_valid(tz, 2)
750 << EXYNOS_TMU_INTEN_RISE2_SHIFT) |
751 (of_thermal_is_trip_valid(tz, 1)
752 << EXYNOS_TMU_INTEN_RISE1_SHIFT) |
753 (of_thermal_is_trip_valid(tz, 0)
754 << EXYNOS_TMU_INTEN_RISE0_SHIFT);
755
756 if (data->soc != SOC_ARCH_EXYNOS4210)
757 interrupt_en |=
758 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
759 } else {
760 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
761 interrupt_en = 0; /* Disable all interrupts */
762 }
763 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
764 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
765 }
766
767 static void exynos5433_tmu_control(struct platform_device *pdev, bool on)
768 {
769 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
770 struct thermal_zone_device *tz = data->tzd;
771 unsigned int con, interrupt_en, pd_det_en;
772
773 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
774
775 if (on) {
776 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
777 interrupt_en =
778 (of_thermal_is_trip_valid(tz, 7)
779 << EXYNOS7_TMU_INTEN_RISE7_SHIFT) |
780 (of_thermal_is_trip_valid(tz, 6)
781 << EXYNOS7_TMU_INTEN_RISE6_SHIFT) |
782 (of_thermal_is_trip_valid(tz, 5)
783 << EXYNOS7_TMU_INTEN_RISE5_SHIFT) |
784 (of_thermal_is_trip_valid(tz, 4)
785 << EXYNOS7_TMU_INTEN_RISE4_SHIFT) |
786 (of_thermal_is_trip_valid(tz, 3)
787 << EXYNOS7_TMU_INTEN_RISE3_SHIFT) |
788 (of_thermal_is_trip_valid(tz, 2)
789 << EXYNOS7_TMU_INTEN_RISE2_SHIFT) |
790 (of_thermal_is_trip_valid(tz, 1)
791 << EXYNOS7_TMU_INTEN_RISE1_SHIFT) |
792 (of_thermal_is_trip_valid(tz, 0)
793 << EXYNOS7_TMU_INTEN_RISE0_SHIFT);
794
795 interrupt_en |=
796 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
797 } else {
798 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
799 interrupt_en = 0; /* Disable all interrupts */
800 }
801
802 pd_det_en = on ? EXYNOS5433_PD_DET_EN : 0;
803
804 writel(pd_det_en, data->base + EXYNOS5433_TMU_PD_DET_EN);
805 writel(interrupt_en, data->base + EXYNOS5433_TMU_REG_INTEN);
806 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
807 }
808
809 static void exynos5440_tmu_control(struct platform_device *pdev, bool on)
810 {
811 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
812 struct thermal_zone_device *tz = data->tzd;
813 unsigned int con, interrupt_en;
814
815 con = get_con_reg(data, readl(data->base + EXYNOS5440_TMU_S0_7_CTRL));
816
817 if (on) {
818 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
819 interrupt_en =
820 (of_thermal_is_trip_valid(tz, 3)
821 << EXYNOS5440_TMU_INTEN_RISE3_SHIFT) |
822 (of_thermal_is_trip_valid(tz, 2)
823 << EXYNOS5440_TMU_INTEN_RISE2_SHIFT) |
824 (of_thermal_is_trip_valid(tz, 1)
825 << EXYNOS5440_TMU_INTEN_RISE1_SHIFT) |
826 (of_thermal_is_trip_valid(tz, 0)
827 << EXYNOS5440_TMU_INTEN_RISE0_SHIFT);
828 interrupt_en |=
829 interrupt_en << EXYNOS5440_TMU_INTEN_FALL0_SHIFT;
830 } else {
831 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
832 interrupt_en = 0; /* Disable all interrupts */
833 }
834 writel(interrupt_en, data->base + EXYNOS5440_TMU_S0_7_IRQEN);
835 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
836 }
837
838 static void exynos7_tmu_control(struct platform_device *pdev, bool on)
839 {
840 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
841 struct thermal_zone_device *tz = data->tzd;
842 unsigned int con, interrupt_en;
843
844 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
845
846 if (on) {
847 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
848 con |= (1 << EXYNOS7_PD_DET_EN_SHIFT);
849 interrupt_en =
850 (of_thermal_is_trip_valid(tz, 7)
851 << EXYNOS7_TMU_INTEN_RISE7_SHIFT) |
852 (of_thermal_is_trip_valid(tz, 6)
853 << EXYNOS7_TMU_INTEN_RISE6_SHIFT) |
854 (of_thermal_is_trip_valid(tz, 5)
855 << EXYNOS7_TMU_INTEN_RISE5_SHIFT) |
856 (of_thermal_is_trip_valid(tz, 4)
857 << EXYNOS7_TMU_INTEN_RISE4_SHIFT) |
858 (of_thermal_is_trip_valid(tz, 3)
859 << EXYNOS7_TMU_INTEN_RISE3_SHIFT) |
860 (of_thermal_is_trip_valid(tz, 2)
861 << EXYNOS7_TMU_INTEN_RISE2_SHIFT) |
862 (of_thermal_is_trip_valid(tz, 1)
863 << EXYNOS7_TMU_INTEN_RISE1_SHIFT) |
864 (of_thermal_is_trip_valid(tz, 0)
865 << EXYNOS7_TMU_INTEN_RISE0_SHIFT);
866
867 interrupt_en |=
868 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
869 } else {
870 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
871 con &= ~(1 << EXYNOS7_PD_DET_EN_SHIFT);
872 interrupt_en = 0; /* Disable all interrupts */
873 }
874
875 writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN);
876 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
877 }
878
879 static int exynos_get_temp(void *p, int *temp)
880 {
881 struct exynos_tmu_data *data = p;
882
883 if (!data || !data->tmu_read)
884 return -EINVAL;
885
886 mutex_lock(&data->lock);
887 clk_enable(data->clk);
888
889 *temp = code_to_temp(data, data->tmu_read(data)) * MCELSIUS;
890
891 clk_disable(data->clk);
892 mutex_unlock(&data->lock);
893
894 return 0;
895 }
896
897 #ifdef CONFIG_THERMAL_EMULATION
898 static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val,
899 int temp)
900 {
901 if (temp) {
902 temp /= MCELSIUS;
903
904 if (data->soc != SOC_ARCH_EXYNOS5440) {
905 val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT);
906 val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT);
907 }
908 if (data->soc == SOC_ARCH_EXYNOS7) {
909 val &= ~(EXYNOS7_EMUL_DATA_MASK <<
910 EXYNOS7_EMUL_DATA_SHIFT);
911 val |= (temp_to_code(data, temp) <<
912 EXYNOS7_EMUL_DATA_SHIFT) |
913 EXYNOS_EMUL_ENABLE;
914 } else {
915 val &= ~(EXYNOS_EMUL_DATA_MASK <<
916 EXYNOS_EMUL_DATA_SHIFT);
917 val |= (temp_to_code(data, temp) <<
918 EXYNOS_EMUL_DATA_SHIFT) |
919 EXYNOS_EMUL_ENABLE;
920 }
921 } else {
922 val &= ~EXYNOS_EMUL_ENABLE;
923 }
924
925 return val;
926 }
927
928 static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data,
929 int temp)
930 {
931 unsigned int val;
932 u32 emul_con;
933
934 if (data->soc == SOC_ARCH_EXYNOS5260)
935 emul_con = EXYNOS5260_EMUL_CON;
936 else if (data->soc == SOC_ARCH_EXYNOS5433)
937 emul_con = EXYNOS5433_TMU_EMUL_CON;
938 else if (data->soc == SOC_ARCH_EXYNOS7)
939 emul_con = EXYNOS7_TMU_REG_EMUL_CON;
940 else
941 emul_con = EXYNOS_EMUL_CON;
942
943 val = readl(data->base + emul_con);
944 val = get_emul_con_reg(data, val, temp);
945 writel(val, data->base + emul_con);
946 }
947
948 static void exynos5440_tmu_set_emulation(struct exynos_tmu_data *data,
949 int temp)
950 {
951 unsigned int val;
952
953 val = readl(data->base + EXYNOS5440_TMU_S0_7_DEBUG);
954 val = get_emul_con_reg(data, val, temp);
955 writel(val, data->base + EXYNOS5440_TMU_S0_7_DEBUG);
956 }
957
958 static int exynos_tmu_set_emulation(void *drv_data, int temp)
959 {
960 struct exynos_tmu_data *data = drv_data;
961 int ret = -EINVAL;
962
963 if (data->soc == SOC_ARCH_EXYNOS4210)
964 goto out;
965
966 if (temp && temp < MCELSIUS)
967 goto out;
968
969 mutex_lock(&data->lock);
970 clk_enable(data->clk);
971 data->tmu_set_emulation(data, temp);
972 clk_disable(data->clk);
973 mutex_unlock(&data->lock);
974 return 0;
975 out:
976 return ret;
977 }
978 #else
979 #define exynos4412_tmu_set_emulation NULL
980 #define exynos5440_tmu_set_emulation NULL
981 static int exynos_tmu_set_emulation(void *drv_data, int temp)
982 { return -EINVAL; }
983 #endif /* CONFIG_THERMAL_EMULATION */
984
985 static int exynos4210_tmu_read(struct exynos_tmu_data *data)
986 {
987 int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
988
989 /* "temp_code" should range between 75 and 175 */
990 return (ret < 75 || ret > 175) ? -ENODATA : ret;
991 }
992
993 static int exynos4412_tmu_read(struct exynos_tmu_data *data)
994 {
995 return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
996 }
997
998 static int exynos5440_tmu_read(struct exynos_tmu_data *data)
999 {
1000 return readb(data->base + EXYNOS5440_TMU_S0_7_TEMP);
1001 }
1002
1003 static int exynos7_tmu_read(struct exynos_tmu_data *data)
1004 {
1005 return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) &
1006 EXYNOS7_TMU_TEMP_MASK;
1007 }
1008
1009 static void exynos_tmu_work(struct work_struct *work)
1010 {
1011 struct exynos_tmu_data *data = container_of(work,
1012 struct exynos_tmu_data, irq_work);
1013 unsigned int val_type;
1014
1015 if (!IS_ERR(data->clk_sec))
1016 clk_enable(data->clk_sec);
1017 /* Find which sensor generated this interrupt */
1018 if (data->soc == SOC_ARCH_EXYNOS5440) {
1019 val_type = readl(data->base_second + EXYNOS5440_TMU_IRQ_STATUS);
1020 if (!((val_type >> data->id) & 0x1))
1021 goto out;
1022 }
1023 if (!IS_ERR(data->clk_sec))
1024 clk_disable(data->clk_sec);
1025
1026 exynos_report_trigger(data);
1027 mutex_lock(&data->lock);
1028 clk_enable(data->clk);
1029
1030 /* TODO: take action based on particular interrupt */
1031 data->tmu_clear_irqs(data);
1032
1033 clk_disable(data->clk);
1034 mutex_unlock(&data->lock);
1035 out:
1036 enable_irq(data->irq);
1037 }
1038
1039 static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data)
1040 {
1041 unsigned int val_irq;
1042 u32 tmu_intstat, tmu_intclear;
1043
1044 if (data->soc == SOC_ARCH_EXYNOS5260) {
1045 tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT;
1046 tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR;
1047 } else if (data->soc == SOC_ARCH_EXYNOS7) {
1048 tmu_intstat = EXYNOS7_TMU_REG_INTPEND;
1049 tmu_intclear = EXYNOS7_TMU_REG_INTPEND;
1050 } else if (data->soc == SOC_ARCH_EXYNOS5433) {
1051 tmu_intstat = EXYNOS5433_TMU_REG_INTPEND;
1052 tmu_intclear = EXYNOS5433_TMU_REG_INTPEND;
1053 } else {
1054 tmu_intstat = EXYNOS_TMU_REG_INTSTAT;
1055 tmu_intclear = EXYNOS_TMU_REG_INTCLEAR;
1056 }
1057
1058 val_irq = readl(data->base + tmu_intstat);
1059 /*
1060 * Clear the interrupts. Please note that the documentation for
1061 * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly
1062 * states that INTCLEAR register has a different placing of bits
1063 * responsible for FALL IRQs than INTSTAT register. Exynos5420
1064 * and Exynos5440 documentation is correct (Exynos4210 doesn't
1065 * support FALL IRQs at all).
1066 */
1067 writel(val_irq, data->base + tmu_intclear);
1068 }
1069
1070 static void exynos5440_tmu_clear_irqs(struct exynos_tmu_data *data)
1071 {
1072 unsigned int val_irq;
1073
1074 val_irq = readl(data->base + EXYNOS5440_TMU_S0_7_IRQ);
1075 /* clear the interrupts */
1076 writel(val_irq, data->base + EXYNOS5440_TMU_S0_7_IRQ);
1077 }
1078
1079 static irqreturn_t exynos_tmu_irq(int irq, void *id)
1080 {
1081 struct exynos_tmu_data *data = id;
1082
1083 disable_irq_nosync(irq);
1084 schedule_work(&data->irq_work);
1085
1086 return IRQ_HANDLED;
1087 }
1088
1089 static const struct of_device_id exynos_tmu_match[] = {
1090 { .compatible = "samsung,exynos3250-tmu", },
1091 { .compatible = "samsung,exynos4210-tmu", },
1092 { .compatible = "samsung,exynos4412-tmu", },
1093 { .compatible = "samsung,exynos5250-tmu", },
1094 { .compatible = "samsung,exynos5260-tmu", },
1095 { .compatible = "samsung,exynos5420-tmu", },
1096 { .compatible = "samsung,exynos5420-tmu-ext-triminfo", },
1097 { .compatible = "samsung,exynos5433-tmu", },
1098 { .compatible = "samsung,exynos5440-tmu", },
1099 { .compatible = "samsung,exynos7-tmu", },
1100 { /* sentinel */ },
1101 };
1102 MODULE_DEVICE_TABLE(of, exynos_tmu_match);
1103
1104 static int exynos_of_get_soc_type(struct device_node *np)
1105 {
1106 if (of_device_is_compatible(np, "samsung,exynos3250-tmu"))
1107 return SOC_ARCH_EXYNOS3250;
1108 else if (of_device_is_compatible(np, "samsung,exynos4210-tmu"))
1109 return SOC_ARCH_EXYNOS4210;
1110 else if (of_device_is_compatible(np, "samsung,exynos4412-tmu"))
1111 return SOC_ARCH_EXYNOS4412;
1112 else if (of_device_is_compatible(np, "samsung,exynos5250-tmu"))
1113 return SOC_ARCH_EXYNOS5250;
1114 else if (of_device_is_compatible(np, "samsung,exynos5260-tmu"))
1115 return SOC_ARCH_EXYNOS5260;
1116 else if (of_device_is_compatible(np, "samsung,exynos5420-tmu"))
1117 return SOC_ARCH_EXYNOS5420;
1118 else if (of_device_is_compatible(np,
1119 "samsung,exynos5420-tmu-ext-triminfo"))
1120 return SOC_ARCH_EXYNOS5420_TRIMINFO;
1121 else if (of_device_is_compatible(np, "samsung,exynos5433-tmu"))
1122 return SOC_ARCH_EXYNOS5433;
1123 else if (of_device_is_compatible(np, "samsung,exynos5440-tmu"))
1124 return SOC_ARCH_EXYNOS5440;
1125 else if (of_device_is_compatible(np, "samsung,exynos7-tmu"))
1126 return SOC_ARCH_EXYNOS7;
1127
1128 return -EINVAL;
1129 }
1130
1131 static int exynos_of_sensor_conf(struct device_node *np,
1132 struct exynos_tmu_platform_data *pdata)
1133 {
1134 u32 value;
1135 int ret;
1136
1137 of_node_get(np);
1138
1139 ret = of_property_read_u32(np, "samsung,tmu_gain", &value);
1140 pdata->gain = (u8)value;
1141 of_property_read_u32(np, "samsung,tmu_reference_voltage", &value);
1142 pdata->reference_voltage = (u8)value;
1143 of_property_read_u32(np, "samsung,tmu_noise_cancel_mode", &value);
1144 pdata->noise_cancel_mode = (u8)value;
1145
1146 of_property_read_u32(np, "samsung,tmu_efuse_value",
1147 &pdata->efuse_value);
1148 of_property_read_u32(np, "samsung,tmu_min_efuse_value",
1149 &pdata->min_efuse_value);
1150 of_property_read_u32(np, "samsung,tmu_max_efuse_value",
1151 &pdata->max_efuse_value);
1152
1153 of_property_read_u32(np, "samsung,tmu_first_point_trim", &value);
1154 pdata->first_point_trim = (u8)value;
1155 of_property_read_u32(np, "samsung,tmu_second_point_trim", &value);
1156 pdata->second_point_trim = (u8)value;
1157 of_property_read_u32(np, "samsung,tmu_default_temp_offset", &value);
1158 pdata->default_temp_offset = (u8)value;
1159
1160 of_property_read_u32(np, "samsung,tmu_cal_type", &pdata->cal_type);
1161 of_property_read_u32(np, "samsung,tmu_cal_mode", &pdata->cal_mode);
1162
1163 of_node_put(np);
1164 return 0;
1165 }
1166
1167 static int exynos_map_dt_data(struct platform_device *pdev)
1168 {
1169 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
1170 struct exynos_tmu_platform_data *pdata;
1171 struct resource res;
1172
1173 if (!data || !pdev->dev.of_node)
1174 return -ENODEV;
1175
1176 data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl");
1177 if (data->id < 0)
1178 data->id = 0;
1179
1180 data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1181 if (data->irq <= 0) {
1182 dev_err(&pdev->dev, "failed to get IRQ\n");
1183 return -ENODEV;
1184 }
1185
1186 if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
1187 dev_err(&pdev->dev, "failed to get Resource 0\n");
1188 return -ENODEV;
1189 }
1190
1191 data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
1192 if (!data->base) {
1193 dev_err(&pdev->dev, "Failed to ioremap memory\n");
1194 return -EADDRNOTAVAIL;
1195 }
1196
1197 pdata = devm_kzalloc(&pdev->dev,
1198 sizeof(struct exynos_tmu_platform_data),
1199 GFP_KERNEL);
1200 if (!pdata)
1201 return -ENOMEM;
1202
1203 exynos_of_sensor_conf(pdev->dev.of_node, pdata);
1204 data->pdata = pdata;
1205 data->soc = exynos_of_get_soc_type(pdev->dev.of_node);
1206
1207 switch (data->soc) {
1208 case SOC_ARCH_EXYNOS4210:
1209 data->tmu_initialize = exynos4210_tmu_initialize;
1210 data->tmu_control = exynos4210_tmu_control;
1211 data->tmu_read = exynos4210_tmu_read;
1212 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1213 break;
1214 case SOC_ARCH_EXYNOS3250:
1215 case SOC_ARCH_EXYNOS4412:
1216 case SOC_ARCH_EXYNOS5250:
1217 case SOC_ARCH_EXYNOS5260:
1218 case SOC_ARCH_EXYNOS5420:
1219 case SOC_ARCH_EXYNOS5420_TRIMINFO:
1220 data->tmu_initialize = exynos4412_tmu_initialize;
1221 data->tmu_control = exynos4210_tmu_control;
1222 data->tmu_read = exynos4412_tmu_read;
1223 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
1224 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1225 break;
1226 case SOC_ARCH_EXYNOS5433:
1227 data->tmu_initialize = exynos5433_tmu_initialize;
1228 data->tmu_control = exynos5433_tmu_control;
1229 data->tmu_read = exynos4412_tmu_read;
1230 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
1231 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1232 break;
1233 case SOC_ARCH_EXYNOS5440:
1234 data->tmu_initialize = exynos5440_tmu_initialize;
1235 data->tmu_control = exynos5440_tmu_control;
1236 data->tmu_read = exynos5440_tmu_read;
1237 data->tmu_set_emulation = exynos5440_tmu_set_emulation;
1238 data->tmu_clear_irqs = exynos5440_tmu_clear_irqs;
1239 break;
1240 case SOC_ARCH_EXYNOS7:
1241 data->tmu_initialize = exynos7_tmu_initialize;
1242 data->tmu_control = exynos7_tmu_control;
1243 data->tmu_read = exynos7_tmu_read;
1244 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
1245 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1246 break;
1247 default:
1248 dev_err(&pdev->dev, "Platform not supported\n");
1249 return -EINVAL;
1250 }
1251
1252 /*
1253 * Check if the TMU shares some registers and then try to map the
1254 * memory of common registers.
1255 */
1256 if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO &&
1257 data->soc != SOC_ARCH_EXYNOS5440)
1258 return 0;
1259
1260 if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
1261 dev_err(&pdev->dev, "failed to get Resource 1\n");
1262 return -ENODEV;
1263 }
1264
1265 data->base_second = devm_ioremap(&pdev->dev, res.start,
1266 resource_size(&res));
1267 if (!data->base_second) {
1268 dev_err(&pdev->dev, "Failed to ioremap memory\n");
1269 return -ENOMEM;
1270 }
1271
1272 return 0;
1273 }
1274
1275 static struct thermal_zone_of_device_ops exynos_sensor_ops = {
1276 .get_temp = exynos_get_temp,
1277 .set_emul_temp = exynos_tmu_set_emulation,
1278 };
1279
1280 static int exynos_tmu_probe(struct platform_device *pdev)
1281 {
1282 struct exynos_tmu_data *data;
1283 int ret;
1284
1285 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
1286 GFP_KERNEL);
1287 if (!data)
1288 return -ENOMEM;
1289
1290 platform_set_drvdata(pdev, data);
1291 mutex_init(&data->lock);
1292
1293 /*
1294 * Try enabling the regulator if found
1295 * TODO: Add regulator as an SOC feature, so that regulator enable
1296 * is a compulsory call.
1297 */
1298 data->regulator = devm_regulator_get(&pdev->dev, "vtmu");
1299 if (!IS_ERR(data->regulator)) {
1300 ret = regulator_enable(data->regulator);
1301 if (ret) {
1302 dev_err(&pdev->dev, "failed to enable vtmu\n");
1303 return ret;
1304 }
1305 } else {
1306 dev_info(&pdev->dev, "Regulator node (vtmu) not found\n");
1307 }
1308
1309 ret = exynos_map_dt_data(pdev);
1310 if (ret)
1311 goto err_sensor;
1312
1313 INIT_WORK(&data->irq_work, exynos_tmu_work);
1314
1315 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
1316 if (IS_ERR(data->clk)) {
1317 dev_err(&pdev->dev, "Failed to get clock\n");
1318 ret = PTR_ERR(data->clk);
1319 goto err_sensor;
1320 }
1321
1322 data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
1323 if (IS_ERR(data->clk_sec)) {
1324 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
1325 dev_err(&pdev->dev, "Failed to get triminfo clock\n");
1326 ret = PTR_ERR(data->clk_sec);
1327 goto err_sensor;
1328 }
1329 } else {
1330 ret = clk_prepare(data->clk_sec);
1331 if (ret) {
1332 dev_err(&pdev->dev, "Failed to get clock\n");
1333 goto err_sensor;
1334 }
1335 }
1336
1337 ret = clk_prepare(data->clk);
1338 if (ret) {
1339 dev_err(&pdev->dev, "Failed to get clock\n");
1340 goto err_clk_sec;
1341 }
1342
1343 switch (data->soc) {
1344 case SOC_ARCH_EXYNOS5433:
1345 case SOC_ARCH_EXYNOS7:
1346 data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk");
1347 if (IS_ERR(data->sclk)) {
1348 dev_err(&pdev->dev, "Failed to get sclk\n");
1349 goto err_clk;
1350 } else {
1351 ret = clk_prepare_enable(data->sclk);
1352 if (ret) {
1353 dev_err(&pdev->dev, "Failed to enable sclk\n");
1354 goto err_clk;
1355 }
1356 }
1357 break;
1358 default:
1359 break;
1360 }
1361
1362 /*
1363 * data->tzd must be registered before calling exynos_tmu_initialize(),
1364 * requesting irq and calling exynos_tmu_control().
1365 */
1366 data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data,
1367 &exynos_sensor_ops);
1368 if (IS_ERR(data->tzd)) {
1369 ret = PTR_ERR(data->tzd);
1370 dev_err(&pdev->dev, "Failed to register sensor: %d\n", ret);
1371 goto err_sclk;
1372 }
1373
1374 ret = exynos_tmu_initialize(pdev);
1375 if (ret) {
1376 dev_err(&pdev->dev, "Failed to initialize TMU\n");
1377 goto err_thermal;
1378 }
1379
1380 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
1381 IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data);
1382 if (ret) {
1383 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
1384 goto err_thermal;
1385 }
1386
1387 exynos_tmu_control(pdev, true);
1388 return 0;
1389
1390 err_thermal:
1391 thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd);
1392 err_sclk:
1393 clk_disable_unprepare(data->sclk);
1394 err_clk:
1395 clk_unprepare(data->clk);
1396 err_clk_sec:
1397 if (!IS_ERR(data->clk_sec))
1398 clk_unprepare(data->clk_sec);
1399 err_sensor:
1400 if (!IS_ERR(data->regulator))
1401 regulator_disable(data->regulator);
1402
1403 return ret;
1404 }
1405
1406 static int exynos_tmu_remove(struct platform_device *pdev)
1407 {
1408 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
1409 struct thermal_zone_device *tzd = data->tzd;
1410
1411 thermal_zone_of_sensor_unregister(&pdev->dev, tzd);
1412 exynos_tmu_control(pdev, false);
1413
1414 clk_disable_unprepare(data->sclk);
1415 clk_unprepare(data->clk);
1416 if (!IS_ERR(data->clk_sec))
1417 clk_unprepare(data->clk_sec);
1418
1419 if (!IS_ERR(data->regulator))
1420 regulator_disable(data->regulator);
1421
1422 return 0;
1423 }
1424
1425 #ifdef CONFIG_PM_SLEEP
1426 static int exynos_tmu_suspend(struct device *dev)
1427 {
1428 exynos_tmu_control(to_platform_device(dev), false);
1429
1430 return 0;
1431 }
1432
1433 static int exynos_tmu_resume(struct device *dev)
1434 {
1435 struct platform_device *pdev = to_platform_device(dev);
1436
1437 exynos_tmu_initialize(pdev);
1438 exynos_tmu_control(pdev, true);
1439
1440 return 0;
1441 }
1442
1443 static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
1444 exynos_tmu_suspend, exynos_tmu_resume);
1445 #define EXYNOS_TMU_PM (&exynos_tmu_pm)
1446 #else
1447 #define EXYNOS_TMU_PM NULL
1448 #endif
1449
1450 static struct platform_driver exynos_tmu_driver = {
1451 .driver = {
1452 .name = "exynos-tmu",
1453 .pm = EXYNOS_TMU_PM,
1454 .of_match_table = exynos_tmu_match,
1455 },
1456 .probe = exynos_tmu_probe,
1457 .remove = exynos_tmu_remove,
1458 };
1459
1460 module_platform_driver(exynos_tmu_driver);
1461
1462 MODULE_DESCRIPTION("EXYNOS TMU Driver");
1463 MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
1464 MODULE_LICENSE("GPL");
1465 MODULE_ALIAS("platform:exynos-tmu");
Linux with added FPC-III support