arch/tile/include/asm/irq.h

   1 /*
   2  * Copyright 2010 Tilera Corporation. All Rights Reserved.
   3  *
   4  *   This program is free software; you can redistribute it and/or
   5  *   modify it under the terms of the GNU General Public License
   6  *   as published by the Free Software Foundation, version 2.
   7  *
   8  *   This program is distributed in the hope that it will be useful, but
   9  *   WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  11  *   NON INFRINGEMENT.  See the GNU General Public License for
  12  *   more details.
  13  */
  14
  15 #ifndef _ASM_TILE_IRQ_H
  16 #define _ASM_TILE_IRQ_H
  17
  18 #include <linux/hardirq.h>
  19
  20 /* The hypervisor interface provides 32 IRQs. */
  21 #define NR_IRQS                 32
  22
  23 /* IRQ numbers used for linux IPIs. */
  24 #define IRQ_RESCHEDULE  0
  25 /* Interrupts for dynamic allocation start at 1. Let the core allocate irq0 */
  26 #define NR_IRQS_LEGACY  1
  27
  28 #define irq_canonicalize(irq)   (irq)
  29
  30 void ack_bad_irq(unsigned int irq);
  31
  32 /*
  33  * Different ways of handling interrupts.  Tile interrupts are always
  34  * per-cpu; there is no global interrupt controller to implement
  35  * enable/disable.  Most onboard devices can send their interrupts to
  36  * many tiles at the same time, and Tile-specific drivers know how to
  37  * deal with this.
  38  *
  39  * However, generic devices (usually PCIE based, sometimes GPIO)
  40  * expect that interrupts will fire on a single core at a time and
  41  * that the irq can be enabled or disabled from any core at any time.
  42  * We implement this by directing such interrupts to a single core.
  43  *
  44  * One added wrinkle is that PCI interrupts can be either
  45  * hardware-cleared (legacy interrupts) or software cleared (MSI).
  46  * Other generic device systems (GPIO) are always software-cleared.
  47  *
  48  * The enums below are used by drivers for onboard devices, including
  49  * the internals of PCI root complex and GPIO.  They allow the driver
  50  * to tell the generic irq code what kind of interrupt is mapped to a
  51  * particular IRQ number.
  52  */
  53 enum {
  54         /* per-cpu interrupt; use enable/disable_percpu_irq() to mask */
  55         TILE_IRQ_PERCPU,
  56         /* global interrupt, hardware responsible for clearing. */
  57         TILE_IRQ_HW_CLEAR,
  58         /* global interrupt, software responsible for clearing. */
  59         TILE_IRQ_SW_CLEAR,
  60 };
  61
  62
  63 /*
  64  * Paravirtualized drivers should call this when they dynamically
  65  * allocate a new IRQ or discover an IRQ that was pre-allocated by the
  66  * hypervisor for use with their particular device.  This gives the
  67  * IRQ subsystem an opportunity to do interrupt-type-specific
  68  * initialization.
  69  *
  70  * ISSUE: We should modify this API so that registering anything
  71  * except percpu interrupts also requires providing callback methods
  72  * for enabling and disabling the interrupt.  This would allow the
  73  * generic IRQ code to proxy enable/disable_irq() calls back into the
  74  * PCI subsystem, which in turn could enable or disable the interrupt
  75  * at the PCI shim.
  76  */
  77 void tile_irq_activate(unsigned int irq, int tile_irq_type);
  78
  79 void setup_irq_regs(void);
  80
  81 #ifdef __tilegx__
  82 void arch_trigger_cpumask_backtrace(const struct cpumask *mask,
  83                                     bool exclude_self);
  84 #define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
  85 #endif
  86
  87 #endif /* _ASM_TILE_IRQ_H */