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Staging: strip: delete the driver
[linux/fpc-iii.git] / drivers / spi / omap2_mcspi.c
blobd8356af118a8c3ba121dff0eddfd616d9da53192
1 /*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrjölä <juha.yrjola@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/platform_device.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/io.h>
35 #include <linux/slab.h>
36
37 #include <linux/spi/spi.h>
38
39 #include <plat/dma.h>
40 #include <plat/clock.h>
41
42
43 #define OMAP2_MCSPI_MAX_FREQ 48000000
44
45 /* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */
46 #define OMAP2_MCSPI_MAX_CTRL 4
47
48 #define OMAP2_MCSPI_REVISION 0x00
49 #define OMAP2_MCSPI_SYSCONFIG 0x10
50 #define OMAP2_MCSPI_SYSSTATUS 0x14
51 #define OMAP2_MCSPI_IRQSTATUS 0x18
52 #define OMAP2_MCSPI_IRQENABLE 0x1c
53 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
54 #define OMAP2_MCSPI_SYST 0x24
55 #define OMAP2_MCSPI_MODULCTRL 0x28
56
57 /* per-channel banks, 0x14 bytes each, first is: */
58 #define OMAP2_MCSPI_CHCONF0 0x2c
59 #define OMAP2_MCSPI_CHSTAT0 0x30
60 #define OMAP2_MCSPI_CHCTRL0 0x34
61 #define OMAP2_MCSPI_TX0 0x38
62 #define OMAP2_MCSPI_RX0 0x3c
63
64 /* per-register bitmasks: */
65
66 #define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4)
67 #define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
68 #define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
69 #define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
70
71 #define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0)
72
73 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
74 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
75 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
76
77 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
78 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
79 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
80 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
81 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
82 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
83 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
84 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
85 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
86 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
87 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
88 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
89 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
90 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
91 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
92
93 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
94 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
95 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
96
97 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
98
99 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
100
101 /* We have 2 DMA channels per CS, one for RX and one for TX */
102 struct omap2_mcspi_dma {
103 int dma_tx_channel;
104 int dma_rx_channel;
105
106 int dma_tx_sync_dev;
107 int dma_rx_sync_dev;
108
109 struct completion dma_tx_completion;
110 struct completion dma_rx_completion;
111 };
112
113 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
114 * cache operations; better heuristics consider wordsize and bitrate.
115 */
116 #define DMA_MIN_BYTES 8
117
118
119 struct omap2_mcspi {
120 struct work_struct work;
121 /* lock protects queue and registers */
122 spinlock_t lock;
123 struct list_head msg_queue;
124 struct spi_master *master;
125 struct clk *ick;
126 struct clk *fck;
127 /* Virtual base address of the controller */
128 void __iomem *base;
129 unsigned long phys;
130 /* SPI1 has 4 channels, while SPI2 has 2 */
131 struct omap2_mcspi_dma *dma_channels;
132 };
133
134 struct omap2_mcspi_cs {
135 void __iomem *base;
136 unsigned long phys;
137 int word_len;
138 struct list_head node;
139 /* Context save and restore shadow register */
140 u32 chconf0;
141 };
142
143 /* used for context save and restore, structure members to be updated whenever
144 * corresponding registers are modified.
145 */
146 struct omap2_mcspi_regs {
147 u32 sysconfig;
148 u32 modulctrl;
149 u32 wakeupenable;
150 struct list_head cs;
151 };
152
153 static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL];
154
155 static struct workqueue_struct *omap2_mcspi_wq;
156
157 #define MOD_REG_BIT(val, mask, set) do { \
158 if (set) \
159 val |= mask; \
160 else \
161 val &= ~mask; \
162 } while (0)
163
164 static inline void mcspi_write_reg(struct spi_master *master,
165 int idx, u32 val)
166 {
167 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
168
169 __raw_writel(val, mcspi->base + idx);
170 }
171
172 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
173 {
174 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
175
176 return __raw_readl(mcspi->base + idx);
177 }
178
179 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
180 int idx, u32 val)
181 {
182 struct omap2_mcspi_cs *cs = spi->controller_state;
183
184 __raw_writel(val, cs->base + idx);
185 }
186
187 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
188 {
189 struct omap2_mcspi_cs *cs = spi->controller_state;
190
191 return __raw_readl(cs->base + idx);
192 }
193
194 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
195 {
196 struct omap2_mcspi_cs *cs = spi->controller_state;
197
198 return cs->chconf0;
199 }
200
201 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
202 {
203 struct omap2_mcspi_cs *cs = spi->controller_state;
204
205 cs->chconf0 = val;
206 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
207 }
208
209 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
210 int is_read, int enable)
211 {
212 u32 l, rw;
213
214 l = mcspi_cached_chconf0(spi);
215
216 if (is_read) /* 1 is read, 0 write */
217 rw = OMAP2_MCSPI_CHCONF_DMAR;
218 else
219 rw = OMAP2_MCSPI_CHCONF_DMAW;
220
221 MOD_REG_BIT(l, rw, enable);
222 mcspi_write_chconf0(spi, l);
223 }
224
225 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
226 {
227 u32 l;
228
229 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
230 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
231 }
232
233 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
234 {
235 u32 l;
236
237 l = mcspi_cached_chconf0(spi);
238 MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
239 mcspi_write_chconf0(spi, l);
240 }
241
242 static void omap2_mcspi_set_master_mode(struct spi_master *master)
243 {
244 u32 l;
245
246 /* setup when switching from (reset default) slave mode
247 * to single-channel master mode
248 */
249 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
250 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
251 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
252 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
253 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
254
255 omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
256 }
257
258 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
259 {
260 struct spi_master *spi_cntrl;
261 struct omap2_mcspi_cs *cs;
262 spi_cntrl = mcspi->master;
263
264 /* McSPI: context restore */
265 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
266 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
267
268 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
269 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig);
270
271 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
272 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
273
274 list_for_each_entry(cs, &omap2_mcspi_ctx[spi_cntrl->bus_num - 1].cs,
275 node)
276 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
277 }
278 static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
279 {
280 clk_disable(mcspi->ick);
281 clk_disable(mcspi->fck);
282 }
283
284 static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
285 {
286 if (clk_enable(mcspi->ick))
287 return -ENODEV;
288 if (clk_enable(mcspi->fck))
289 return -ENODEV;
290
291 omap2_mcspi_restore_ctx(mcspi);
292
293 return 0;
294 }
295
296 static unsigned
297 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
298 {
299 struct omap2_mcspi *mcspi;
300 struct omap2_mcspi_cs *cs = spi->controller_state;
301 struct omap2_mcspi_dma *mcspi_dma;
302 unsigned int count, c;
303 unsigned long base, tx_reg, rx_reg;
304 int word_len, data_type, element_count;
305 u8 * rx;
306 const u8 * tx;
307
308 mcspi = spi_master_get_devdata(spi->master);
309 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
310
311 count = xfer->len;
312 c = count;
313 word_len = cs->word_len;
314
315 base = cs->phys;
316 tx_reg = base + OMAP2_MCSPI_TX0;
317 rx_reg = base + OMAP2_MCSPI_RX0;
318 rx = xfer->rx_buf;
319 tx = xfer->tx_buf;
320
321 if (word_len <= 8) {
322 data_type = OMAP_DMA_DATA_TYPE_S8;
323 element_count = count;
324 } else if (word_len <= 16) {
325 data_type = OMAP_DMA_DATA_TYPE_S16;
326 element_count = count >> 1;
327 } else /* word_len <= 32 */ {
328 data_type = OMAP_DMA_DATA_TYPE_S32;
329 element_count = count >> 2;
330 }
331
332 if (tx != NULL) {
333 omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
334 data_type, element_count, 1,
335 OMAP_DMA_SYNC_ELEMENT,
336 mcspi_dma->dma_tx_sync_dev, 0);
337
338 omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
339 OMAP_DMA_AMODE_CONSTANT,
340 tx_reg, 0, 0);
341
342 omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
343 OMAP_DMA_AMODE_POST_INC,
344 xfer->tx_dma, 0, 0);
345 }
346
347 if (rx != NULL) {
348 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
349 data_type, element_count - 1, 1,
350 OMAP_DMA_SYNC_ELEMENT,
351 mcspi_dma->dma_rx_sync_dev, 1);
352
353 omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
354 OMAP_DMA_AMODE_CONSTANT,
355 rx_reg, 0, 0);
356
357 omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
358 OMAP_DMA_AMODE_POST_INC,
359 xfer->rx_dma, 0, 0);
360 }
361
362 if (tx != NULL) {
363 omap_start_dma(mcspi_dma->dma_tx_channel);
364 omap2_mcspi_set_dma_req(spi, 0, 1);
365 }
366
367 if (rx != NULL) {
368 omap_start_dma(mcspi_dma->dma_rx_channel);
369 omap2_mcspi_set_dma_req(spi, 1, 1);
370 }
371
372 if (tx != NULL) {
373 wait_for_completion(&mcspi_dma->dma_tx_completion);
374 dma_unmap_single(NULL, xfer->tx_dma, count, DMA_TO_DEVICE);
375 }
376
377 if (rx != NULL) {
378 wait_for_completion(&mcspi_dma->dma_rx_completion);
379 dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE);
380 omap2_mcspi_set_enable(spi, 0);
381 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
382 & OMAP2_MCSPI_CHSTAT_RXS)) {
383 u32 w;
384
385 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
386 if (word_len <= 8)
387 ((u8 *)xfer->rx_buf)[element_count - 1] = w;
388 else if (word_len <= 16)
389 ((u16 *)xfer->rx_buf)[element_count - 1] = w;
390 else /* word_len <= 32 */
391 ((u32 *)xfer->rx_buf)[element_count - 1] = w;
392 } else {
393 dev_err(&spi->dev, "DMA RX last word empty");
394 count -= (word_len <= 8) ? 1 :
395 (word_len <= 16) ? 2 :
396 /* word_len <= 32 */ 4;
397 }
398 omap2_mcspi_set_enable(spi, 1);
399 }
400 return count;
401 }
402
403 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
404 {
405 unsigned long timeout;
406
407 timeout = jiffies + msecs_to_jiffies(1000);
408 while (!(__raw_readl(reg) & bit)) {
409 if (time_after(jiffies, timeout))
410 return -1;
411 cpu_relax();
412 }
413 return 0;
414 }
415
416 static unsigned
417 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
418 {
419 struct omap2_mcspi *mcspi;
420 struct omap2_mcspi_cs *cs = spi->controller_state;
421 unsigned int count, c;
422 u32 l;
423 void __iomem *base = cs->base;
424 void __iomem *tx_reg;
425 void __iomem *rx_reg;
426 void __iomem *chstat_reg;
427 int word_len;
428
429 mcspi = spi_master_get_devdata(spi->master);
430 count = xfer->len;
431 c = count;
432 word_len = cs->word_len;
433
434 l = mcspi_cached_chconf0(spi);
435 l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
436
437 /* We store the pre-calculated register addresses on stack to speed
438 * up the transfer loop. */
439 tx_reg = base + OMAP2_MCSPI_TX0;
440 rx_reg = base + OMAP2_MCSPI_RX0;
441 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
442
443 if (word_len <= 8) {
444 u8 *rx;
445 const u8 *tx;
446
447 rx = xfer->rx_buf;
448 tx = xfer->tx_buf;
449
450 do {
451 c -= 1;
452 if (tx != NULL) {
453 if (mcspi_wait_for_reg_bit(chstat_reg,
454 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
455 dev_err(&spi->dev, "TXS timed out\n");
456 goto out;
457 }
458 #ifdef VERBOSE
459 dev_dbg(&spi->dev, "write-%d %02x\n",
460 word_len, *tx);
461 #endif
462 __raw_writel(*tx++, tx_reg);
463 }
464 if (rx != NULL) {
465 if (mcspi_wait_for_reg_bit(chstat_reg,
466 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
467 dev_err(&spi->dev, "RXS timed out\n");
468 goto out;
469 }
470 /* prevent last RX_ONLY read from triggering
471 * more word i/o: switch to rx+tx
472 */
473 if (c == 0 && tx == NULL)
474 mcspi_write_chconf0(spi, l);
475 *rx++ = __raw_readl(rx_reg);
476 #ifdef VERBOSE
477 dev_dbg(&spi->dev, "read-%d %02x\n",
478 word_len, *(rx - 1));
479 #endif
480 }
481 } while (c);
482 } else if (word_len <= 16) {
483 u16 *rx;
484 const u16 *tx;
485
486 rx = xfer->rx_buf;
487 tx = xfer->tx_buf;
488 do {
489 c -= 2;
490 if (tx != NULL) {
491 if (mcspi_wait_for_reg_bit(chstat_reg,
492 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
493 dev_err(&spi->dev, "TXS timed out\n");
494 goto out;
495 }
496 #ifdef VERBOSE
497 dev_dbg(&spi->dev, "write-%d %04x\n",
498 word_len, *tx);
499 #endif
500 __raw_writel(*tx++, tx_reg);
501 }
502 if (rx != NULL) {
503 if (mcspi_wait_for_reg_bit(chstat_reg,
504 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
505 dev_err(&spi->dev, "RXS timed out\n");
506 goto out;
507 }
508 /* prevent last RX_ONLY read from triggering
509 * more word i/o: switch to rx+tx
510 */
511 if (c == 0 && tx == NULL)
512 mcspi_write_chconf0(spi, l);
513 *rx++ = __raw_readl(rx_reg);
514 #ifdef VERBOSE
515 dev_dbg(&spi->dev, "read-%d %04x\n",
516 word_len, *(rx - 1));
517 #endif
518 }
519 } while (c);
520 } else if (word_len <= 32) {
521 u32 *rx;
522 const u32 *tx;
523
524 rx = xfer->rx_buf;
525 tx = xfer->tx_buf;
526 do {
527 c -= 4;
528 if (tx != NULL) {
529 if (mcspi_wait_for_reg_bit(chstat_reg,
530 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
531 dev_err(&spi->dev, "TXS timed out\n");
532 goto out;
533 }
534 #ifdef VERBOSE
535 dev_dbg(&spi->dev, "write-%d %04x\n",
536 word_len, *tx);
537 #endif
538 __raw_writel(*tx++, tx_reg);
539 }
540 if (rx != NULL) {
541 if (mcspi_wait_for_reg_bit(chstat_reg,
542 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
543 dev_err(&spi->dev, "RXS timed out\n");
544 goto out;
545 }
546 /* prevent last RX_ONLY read from triggering
547 * more word i/o: switch to rx+tx
548 */
549 if (c == 0 && tx == NULL)
550 mcspi_write_chconf0(spi, l);
551 *rx++ = __raw_readl(rx_reg);
552 #ifdef VERBOSE
553 dev_dbg(&spi->dev, "read-%d %04x\n",
554 word_len, *(rx - 1));
555 #endif
556 }
557 } while (c);
558 }
559
560 /* for TX_ONLY mode, be sure all words have shifted out */
561 if (xfer->rx_buf == NULL) {
562 if (mcspi_wait_for_reg_bit(chstat_reg,
563 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
564 dev_err(&spi->dev, "TXS timed out\n");
565 } else if (mcspi_wait_for_reg_bit(chstat_reg,
566 OMAP2_MCSPI_CHSTAT_EOT) < 0)
567 dev_err(&spi->dev, "EOT timed out\n");
568 }
569 out:
570 return count - c;
571 }
572
573 /* called only when no transfer is active to this device */
574 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
575 struct spi_transfer *t)
576 {
577 struct omap2_mcspi_cs *cs = spi->controller_state;
578 struct omap2_mcspi *mcspi;
579 struct spi_master *spi_cntrl;
580 u32 l = 0, div = 0;
581 u8 word_len = spi->bits_per_word;
582 u32 speed_hz = spi->max_speed_hz;
583
584 mcspi = spi_master_get_devdata(spi->master);
585 spi_cntrl = mcspi->master;
586
587 if (t != NULL && t->bits_per_word)
588 word_len = t->bits_per_word;
589
590 cs->word_len = word_len;
591
592 if (t && t->speed_hz)
593 speed_hz = t->speed_hz;
594
595 if (speed_hz) {
596 while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div))
597 > speed_hz)
598 div++;
599 } else
600 div = 15;
601
602 l = mcspi_cached_chconf0(spi);
603
604 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
605 * REVISIT: this controller could support SPI_3WIRE mode.
606 */
607 l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
608 l |= OMAP2_MCSPI_CHCONF_DPE0;
609
610 /* wordlength */
611 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
612 l |= (word_len - 1) << 7;
613
614 /* set chipselect polarity; manage with FORCE */
615 if (!(spi->mode & SPI_CS_HIGH))
616 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
617 else
618 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
619
620 /* set clock divisor */
621 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
622 l |= div << 2;
623
624 /* set SPI mode 0..3 */
625 if (spi->mode & SPI_CPOL)
626 l |= OMAP2_MCSPI_CHCONF_POL;
627 else
628 l &= ~OMAP2_MCSPI_CHCONF_POL;
629 if (spi->mode & SPI_CPHA)
630 l |= OMAP2_MCSPI_CHCONF_PHA;
631 else
632 l &= ~OMAP2_MCSPI_CHCONF_PHA;
633
634 mcspi_write_chconf0(spi, l);
635
636 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
637 OMAP2_MCSPI_MAX_FREQ / (1 << div),
638 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
639 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
640
641 return 0;
642 }
643
644 static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
645 {
646 struct spi_device *spi = data;
647 struct omap2_mcspi *mcspi;
648 struct omap2_mcspi_dma *mcspi_dma;
649
650 mcspi = spi_master_get_devdata(spi->master);
651 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
652
653 complete(&mcspi_dma->dma_rx_completion);
654
655 /* We must disable the DMA RX request */
656 omap2_mcspi_set_dma_req(spi, 1, 0);
657 }
658
659 static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
660 {
661 struct spi_device *spi = data;
662 struct omap2_mcspi *mcspi;
663 struct omap2_mcspi_dma *mcspi_dma;
664
665 mcspi = spi_master_get_devdata(spi->master);
666 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
667
668 complete(&mcspi_dma->dma_tx_completion);
669
670 /* We must disable the DMA TX request */
671 omap2_mcspi_set_dma_req(spi, 0, 0);
672 }
673
674 static int omap2_mcspi_request_dma(struct spi_device *spi)
675 {
676 struct spi_master *master = spi->master;
677 struct omap2_mcspi *mcspi;
678 struct omap2_mcspi_dma *mcspi_dma;
679
680 mcspi = spi_master_get_devdata(master);
681 mcspi_dma = mcspi->dma_channels + spi->chip_select;
682
683 if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
684 omap2_mcspi_dma_rx_callback, spi,
685 &mcspi_dma->dma_rx_channel)) {
686 dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
687 return -EAGAIN;
688 }
689
690 if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
691 omap2_mcspi_dma_tx_callback, spi,
692 &mcspi_dma->dma_tx_channel)) {
693 omap_free_dma(mcspi_dma->dma_rx_channel);
694 mcspi_dma->dma_rx_channel = -1;
695 dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
696 return -EAGAIN;
697 }
698
699 init_completion(&mcspi_dma->dma_rx_completion);
700 init_completion(&mcspi_dma->dma_tx_completion);
701
702 return 0;
703 }
704
705 static int omap2_mcspi_setup(struct spi_device *spi)
706 {
707 int ret;
708 struct omap2_mcspi *mcspi;
709 struct omap2_mcspi_dma *mcspi_dma;
710 struct omap2_mcspi_cs *cs = spi->controller_state;
711
712 if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
713 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
714 spi->bits_per_word);
715 return -EINVAL;
716 }
717
718 mcspi = spi_master_get_devdata(spi->master);
719 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
720
721 if (!cs) {
722 cs = kzalloc(sizeof *cs, GFP_KERNEL);
723 if (!cs)
724 return -ENOMEM;
725 cs->base = mcspi->base + spi->chip_select * 0x14;
726 cs->phys = mcspi->phys + spi->chip_select * 0x14;
727 cs->chconf0 = 0;
728 spi->controller_state = cs;
729 /* Link this to context save list */
730 list_add_tail(&cs->node,
731 &omap2_mcspi_ctx[mcspi->master->bus_num - 1].cs);
732 }
733
734 if (mcspi_dma->dma_rx_channel == -1
735 || mcspi_dma->dma_tx_channel == -1) {
736 ret = omap2_mcspi_request_dma(spi);
737 if (ret < 0)
738 return ret;
739 }
740
741 if (omap2_mcspi_enable_clocks(mcspi))
742 return -ENODEV;
743
744 ret = omap2_mcspi_setup_transfer(spi, NULL);
745 omap2_mcspi_disable_clocks(mcspi);
746
747 return ret;
748 }
749
750 static void omap2_mcspi_cleanup(struct spi_device *spi)
751 {
752 struct omap2_mcspi *mcspi;
753 struct omap2_mcspi_dma *mcspi_dma;
754 struct omap2_mcspi_cs *cs;
755
756 mcspi = spi_master_get_devdata(spi->master);
757 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
758
759 if (spi->controller_state) {
760 /* Unlink controller state from context save list */
761 cs = spi->controller_state;
762 list_del(&cs->node);
763
764 kfree(spi->controller_state);
765 }
766
767 if (mcspi_dma->dma_rx_channel != -1) {
768 omap_free_dma(mcspi_dma->dma_rx_channel);
769 mcspi_dma->dma_rx_channel = -1;
770 }
771 if (mcspi_dma->dma_tx_channel != -1) {
772 omap_free_dma(mcspi_dma->dma_tx_channel);
773 mcspi_dma->dma_tx_channel = -1;
774 }
775 }
776
777 static void omap2_mcspi_work(struct work_struct *work)
778 {
779 struct omap2_mcspi *mcspi;
780
781 mcspi = container_of(work, struct omap2_mcspi, work);
782 spin_lock_irq(&mcspi->lock);
783
784 if (omap2_mcspi_enable_clocks(mcspi))
785 goto out;
786
787 /* We only enable one channel at a time -- the one whose message is
788 * at the head of the queue -- although this controller would gladly
789 * arbitrate among multiple channels. This corresponds to "single
790 * channel" master mode. As a side effect, we need to manage the
791 * chipselect with the FORCE bit ... CS != channel enable.
792 */
793 while (!list_empty(&mcspi->msg_queue)) {
794 struct spi_message *m;
795 struct spi_device *spi;
796 struct spi_transfer *t = NULL;
797 int cs_active = 0;
798 struct omap2_mcspi_cs *cs;
799 int par_override = 0;
800 int status = 0;
801 u32 chconf;
802
803 m = container_of(mcspi->msg_queue.next, struct spi_message,
804 queue);
805
806 list_del_init(&m->queue);
807 spin_unlock_irq(&mcspi->lock);
808
809 spi = m->spi;
810 cs = spi->controller_state;
811
812 omap2_mcspi_set_enable(spi, 1);
813 list_for_each_entry(t, &m->transfers, transfer_list) {
814 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
815 status = -EINVAL;
816 break;
817 }
818 if (par_override || t->speed_hz || t->bits_per_word) {
819 par_override = 1;
820 status = omap2_mcspi_setup_transfer(spi, t);
821 if (status < 0)
822 break;
823 if (!t->speed_hz && !t->bits_per_word)
824 par_override = 0;
825 }
826
827 if (!cs_active) {
828 omap2_mcspi_force_cs(spi, 1);
829 cs_active = 1;
830 }
831
832 chconf = mcspi_cached_chconf0(spi);
833 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
834 if (t->tx_buf == NULL)
835 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
836 else if (t->rx_buf == NULL)
837 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
838 mcspi_write_chconf0(spi, chconf);
839
840 if (t->len) {
841 unsigned count;
842
843 /* RX_ONLY mode needs dummy data in TX reg */
844 if (t->tx_buf == NULL)
845 __raw_writel(0, cs->base
846 + OMAP2_MCSPI_TX0);
847
848 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
849 count = omap2_mcspi_txrx_dma(spi, t);
850 else
851 count = omap2_mcspi_txrx_pio(spi, t);
852 m->actual_length += count;
853
854 if (count != t->len) {
855 status = -EIO;
856 break;
857 }
858 }
859
860 if (t->delay_usecs)
861 udelay(t->delay_usecs);
862
863 /* ignore the "leave it on after last xfer" hint */
864 if (t->cs_change) {
865 omap2_mcspi_force_cs(spi, 0);
866 cs_active = 0;
867 }
868 }
869
870 /* Restore defaults if they were overriden */
871 if (par_override) {
872 par_override = 0;
873 status = omap2_mcspi_setup_transfer(spi, NULL);
874 }
875
876 if (cs_active)
877 omap2_mcspi_force_cs(spi, 0);
878
879 omap2_mcspi_set_enable(spi, 0);
880
881 m->status = status;
882 m->complete(m->context);
883
884 spin_lock_irq(&mcspi->lock);
885 }
886
887 omap2_mcspi_disable_clocks(mcspi);
888
889 out:
890 spin_unlock_irq(&mcspi->lock);
891 }
892
893 static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
894 {
895 struct omap2_mcspi *mcspi;
896 unsigned long flags;
897 struct spi_transfer *t;
898
899 m->actual_length = 0;
900 m->status = 0;
901
902 /* reject invalid messages and transfers */
903 if (list_empty(&m->transfers) || !m->complete)
904 return -EINVAL;
905 list_for_each_entry(t, &m->transfers, transfer_list) {
906 const void *tx_buf = t->tx_buf;
907 void *rx_buf = t->rx_buf;
908 unsigned len = t->len;
909
910 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
911 || (len && !(rx_buf || tx_buf))
912 || (t->bits_per_word &&
913 ( t->bits_per_word < 4
914 || t->bits_per_word > 32))) {
915 dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
916 t->speed_hz,
917 len,
918 tx_buf ? "tx" : "",
919 rx_buf ? "rx" : "",
920 t->bits_per_word);
921 return -EINVAL;
922 }
923 if (t->speed_hz && t->speed_hz < OMAP2_MCSPI_MAX_FREQ/(1<<16)) {
924 dev_dbg(&spi->dev, "%d Hz max exceeds %d\n",
925 t->speed_hz,
926 OMAP2_MCSPI_MAX_FREQ/(1<<16));
927 return -EINVAL;
928 }
929
930 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
931 continue;
932
933 /* Do DMA mapping "early" for better error reporting and
934 * dcache use. Note that if dma_unmap_single() ever starts
935 * to do real work on ARM, we'd need to clean up mappings
936 * for previous transfers on *ALL* exits of this loop...
937 */
938 if (tx_buf != NULL) {
939 t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf,
940 len, DMA_TO_DEVICE);
941 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
942 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
943 'T', len);
944 return -EINVAL;
945 }
946 }
947 if (rx_buf != NULL) {
948 t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len,
949 DMA_FROM_DEVICE);
950 if (dma_mapping_error(&spi->dev, t->rx_dma)) {
951 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
952 'R', len);
953 if (tx_buf != NULL)
954 dma_unmap_single(NULL, t->tx_dma,
955 len, DMA_TO_DEVICE);
956 return -EINVAL;
957 }
958 }
959 }
960
961 mcspi = spi_master_get_devdata(spi->master);
962
963 spin_lock_irqsave(&mcspi->lock, flags);
964 list_add_tail(&m->queue, &mcspi->msg_queue);
965 queue_work(omap2_mcspi_wq, &mcspi->work);
966 spin_unlock_irqrestore(&mcspi->lock, flags);
967
968 return 0;
969 }
970
971 static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
972 {
973 struct spi_master *master = mcspi->master;
974 u32 tmp;
975
976 if (omap2_mcspi_enable_clocks(mcspi))
977 return -1;
978
979 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
980 OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
981 do {
982 tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
983 } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
984
985 tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
986 OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
987 OMAP2_MCSPI_SYSCONFIG_SMARTIDLE;
988 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp);
989 omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp;
990
991 tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
992 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
993 omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp;
994
995 omap2_mcspi_set_master_mode(master);
996 omap2_mcspi_disable_clocks(mcspi);
997 return 0;
998 }
999
1000 static u8 __initdata spi1_rxdma_id [] = {
1001 OMAP24XX_DMA_SPI1_RX0,
1002 OMAP24XX_DMA_SPI1_RX1,
1003 OMAP24XX_DMA_SPI1_RX2,
1004 OMAP24XX_DMA_SPI1_RX3,
1005 };
1006
1007 static u8 __initdata spi1_txdma_id [] = {
1008 OMAP24XX_DMA_SPI1_TX0,
1009 OMAP24XX_DMA_SPI1_TX1,
1010 OMAP24XX_DMA_SPI1_TX2,
1011 OMAP24XX_DMA_SPI1_TX3,
1012 };
1013
1014 static u8 __initdata spi2_rxdma_id[] = {
1015 OMAP24XX_DMA_SPI2_RX0,
1016 OMAP24XX_DMA_SPI2_RX1,
1017 };
1018
1019 static u8 __initdata spi2_txdma_id[] = {
1020 OMAP24XX_DMA_SPI2_TX0,
1021 OMAP24XX_DMA_SPI2_TX1,
1022 };
1023
1024 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1025 || defined(CONFIG_ARCH_OMAP4)
1026 static u8 __initdata spi3_rxdma_id[] = {
1027 OMAP24XX_DMA_SPI3_RX0,
1028 OMAP24XX_DMA_SPI3_RX1,
1029 };
1030
1031 static u8 __initdata spi3_txdma_id[] = {
1032 OMAP24XX_DMA_SPI3_TX0,
1033 OMAP24XX_DMA_SPI3_TX1,
1034 };
1035 #endif
1036
1037 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1038 static u8 __initdata spi4_rxdma_id[] = {
1039 OMAP34XX_DMA_SPI4_RX0,
1040 };
1041
1042 static u8 __initdata spi4_txdma_id[] = {
1043 OMAP34XX_DMA_SPI4_TX0,
1044 };
1045 #endif
1046
1047 static int __init omap2_mcspi_probe(struct platform_device *pdev)
1048 {
1049 struct spi_master *master;
1050 struct omap2_mcspi *mcspi;
1051 struct resource *r;
1052 int status = 0, i;
1053 const u8 *rxdma_id, *txdma_id;
1054 unsigned num_chipselect;
1055
1056 switch (pdev->id) {
1057 case 1:
1058 rxdma_id = spi1_rxdma_id;
1059 txdma_id = spi1_txdma_id;
1060 num_chipselect = 4;
1061 break;
1062 case 2:
1063 rxdma_id = spi2_rxdma_id;
1064 txdma_id = spi2_txdma_id;
1065 num_chipselect = 2;
1066 break;
1067 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1068 || defined(CONFIG_ARCH_OMAP4)
1069 case 3:
1070 rxdma_id = spi3_rxdma_id;
1071 txdma_id = spi3_txdma_id;
1072 num_chipselect = 2;
1073 break;
1074 #endif
1075 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1076 case 4:
1077 rxdma_id = spi4_rxdma_id;
1078 txdma_id = spi4_txdma_id;
1079 num_chipselect = 1;
1080 break;
1081 #endif
1082 default:
1083 return -EINVAL;
1084 }
1085
1086 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1087 if (master == NULL) {
1088 dev_dbg(&pdev->dev, "master allocation failed\n");
1089 return -ENOMEM;
1090 }
1091
1092 /* the spi->mode bits understood by this driver: */
1093 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1094
1095 if (pdev->id != -1)
1096 master->bus_num = pdev->id;
1097
1098 master->setup = omap2_mcspi_setup;
1099 master->transfer = omap2_mcspi_transfer;
1100 master->cleanup = omap2_mcspi_cleanup;
1101 master->num_chipselect = num_chipselect;
1102
1103 dev_set_drvdata(&pdev->dev, master);
1104
1105 mcspi = spi_master_get_devdata(master);
1106 mcspi->master = master;
1107
1108 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1109 if (r == NULL) {
1110 status = -ENODEV;
1111 goto err1;
1112 }
1113 if (!request_mem_region(r->start, (r->end - r->start) + 1,
1114 dev_name(&pdev->dev))) {
1115 status = -EBUSY;
1116 goto err1;
1117 }
1118
1119 mcspi->phys = r->start;
1120 mcspi->base = ioremap(r->start, r->end - r->start + 1);
1121 if (!mcspi->base) {
1122 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1123 status = -ENOMEM;
1124 goto err1aa;
1125 }
1126
1127 INIT_WORK(&mcspi->work, omap2_mcspi_work);
1128
1129 spin_lock_init(&mcspi->lock);
1130 INIT_LIST_HEAD(&mcspi->msg_queue);
1131 INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
1132
1133 mcspi->ick = clk_get(&pdev->dev, "ick");
1134 if (IS_ERR(mcspi->ick)) {
1135 dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
1136 status = PTR_ERR(mcspi->ick);
1137 goto err1a;
1138 }
1139 mcspi->fck = clk_get(&pdev->dev, "fck");
1140 if (IS_ERR(mcspi->fck)) {
1141 dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
1142 status = PTR_ERR(mcspi->fck);
1143 goto err2;
1144 }
1145
1146 mcspi->dma_channels = kcalloc(master->num_chipselect,
1147 sizeof(struct omap2_mcspi_dma),
1148 GFP_KERNEL);
1149
1150 if (mcspi->dma_channels == NULL)
1151 goto err3;
1152
1153 for (i = 0; i < num_chipselect; i++) {
1154 mcspi->dma_channels[i].dma_rx_channel = -1;
1155 mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i];
1156 mcspi->dma_channels[i].dma_tx_channel = -1;
1157 mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i];
1158 }
1159
1160 if (omap2_mcspi_reset(mcspi) < 0)
1161 goto err4;
1162
1163 status = spi_register_master(master);
1164 if (status < 0)
1165 goto err4;
1166
1167 return status;
1168
1169 err4:
1170 kfree(mcspi->dma_channels);
1171 err3:
1172 clk_put(mcspi->fck);
1173 err2:
1174 clk_put(mcspi->ick);
1175 err1a:
1176 iounmap(mcspi->base);
1177 err1aa:
1178 release_mem_region(r->start, (r->end - r->start) + 1);
1179 err1:
1180 spi_master_put(master);
1181 return status;
1182 }
1183
1184 static int __exit omap2_mcspi_remove(struct platform_device *pdev)
1185 {
1186 struct spi_master *master;
1187 struct omap2_mcspi *mcspi;
1188 struct omap2_mcspi_dma *dma_channels;
1189 struct resource *r;
1190 void __iomem *base;
1191
1192 master = dev_get_drvdata(&pdev->dev);
1193 mcspi = spi_master_get_devdata(master);
1194 dma_channels = mcspi->dma_channels;
1195
1196 clk_put(mcspi->fck);
1197 clk_put(mcspi->ick);
1198
1199 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1200 release_mem_region(r->start, (r->end - r->start) + 1);
1201
1202 base = mcspi->base;
1203 spi_unregister_master(master);
1204 iounmap(base);
1205 kfree(dma_channels);
1206
1207 return 0;
1208 }
1209
1210 /* work with hotplug and coldplug */
1211 MODULE_ALIAS("platform:omap2_mcspi");
1212
1213 static struct platform_driver omap2_mcspi_driver = {
1214 .driver = {
1215 .name = "omap2_mcspi",
1216 .owner = THIS_MODULE,
1217 },
1218 .remove = __exit_p(omap2_mcspi_remove),
1219 };
1220
1221
1222 static int __init omap2_mcspi_init(void)
1223 {
1224 omap2_mcspi_wq = create_singlethread_workqueue(
1225 omap2_mcspi_driver.driver.name);
1226 if (omap2_mcspi_wq == NULL)
1227 return -1;
1228 return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe);
1229 }
1230 subsys_initcall(omap2_mcspi_init);
1231
1232 static void __exit omap2_mcspi_exit(void)
1233 {
1234 platform_driver_unregister(&omap2_mcspi_driver);
1235
1236 destroy_workqueue(omap2_mcspi_wq);
1237 }
1238 module_exit(omap2_mcspi_exit);
1239
1240 MODULE_LICENSE("GPL");
Linux with added FPC-III support