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Staging: strip: delete the driver
[linux/fpc-iii.git] / drivers / spi / spi_mpc8xxx.c
blob14d052316502cfcf7334cbb57cf5181e02c2c3be
1 /*
2 * MPC8xxx SPI controller driver.
3 *
4 * Maintainer: Kumar Gala
5 *
6 * Copyright (C) 2006 Polycom, Inc.
7 *
8 * CPM SPI and QE buffer descriptors mode support:
9 * Copyright (c) 2009 MontaVista Software, Inc.
10 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/bug.h>
22 #include <linux/errno.h>
23 #include <linux/err.h>
24 #include <linux/io.h>
25 #include <linux/completion.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28 #include <linux/irq.h>
29 #include <linux/device.h>
30 #include <linux/spi/spi.h>
31 #include <linux/spi/spi_bitbang.h>
32 #include <linux/platform_device.h>
33 #include <linux/fsl_devices.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/mm.h>
36 #include <linux/mutex.h>
37 #include <linux/of.h>
38 #include <linux/of_platform.h>
39 #include <linux/gpio.h>
40 #include <linux/of_gpio.h>
41 #include <linux/of_spi.h>
42 #include <linux/slab.h>
43
44 #include <sysdev/fsl_soc.h>
45 #include <asm/cpm.h>
46 #include <asm/qe.h>
47 #include <asm/irq.h>
48
49 /* CPM1 and CPM2 are mutually exclusive. */
50 #ifdef CONFIG_CPM1
51 #include <asm/cpm1.h>
52 #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_CH_SPI, 0)
53 #else
54 #include <asm/cpm2.h>
55 #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, 0, 0)
56 #endif
57
58 /* SPI Controller registers */
59 struct mpc8xxx_spi_reg {
60 u8 res1[0x20];
61 __be32 mode;
62 __be32 event;
63 __be32 mask;
64 __be32 command;
65 __be32 transmit;
66 __be32 receive;
67 };
68
69 /* SPI Parameter RAM */
70 struct spi_pram {
71 __be16 rbase; /* Rx Buffer descriptor base address */
72 __be16 tbase; /* Tx Buffer descriptor base address */
73 u8 rfcr; /* Rx function code */
74 u8 tfcr; /* Tx function code */
75 __be16 mrblr; /* Max receive buffer length */
76 __be32 rstate; /* Internal */
77 __be32 rdp; /* Internal */
78 __be16 rbptr; /* Internal */
79 __be16 rbc; /* Internal */
80 __be32 rxtmp; /* Internal */
81 __be32 tstate; /* Internal */
82 __be32 tdp; /* Internal */
83 __be16 tbptr; /* Internal */
84 __be16 tbc; /* Internal */
85 __be32 txtmp; /* Internal */
86 __be32 res; /* Tx temp. */
87 __be16 rpbase; /* Relocation pointer (CPM1 only) */
88 __be16 res1; /* Reserved */
89 };
90
91 /* SPI Controller mode register definitions */
92 #define SPMODE_LOOP (1 << 30)
93 #define SPMODE_CI_INACTIVEHIGH (1 << 29)
94 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
95 #define SPMODE_DIV16 (1 << 27)
96 #define SPMODE_REV (1 << 26)
97 #define SPMODE_MS (1 << 25)
98 #define SPMODE_ENABLE (1 << 24)
99 #define SPMODE_LEN(x) ((x) << 20)
100 #define SPMODE_PM(x) ((x) << 16)
101 #define SPMODE_OP (1 << 14)
102 #define SPMODE_CG(x) ((x) << 7)
103
104 /*
105 * Default for SPI Mode:
106 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
107 */
108 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
109 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
110
111 /* SPIE register values */
112 #define SPIE_NE 0x00000200 /* Not empty */
113 #define SPIE_NF 0x00000100 /* Not full */
114
115 /* SPIM register values */
116 #define SPIM_NE 0x00000200 /* Not empty */
117 #define SPIM_NF 0x00000100 /* Not full */
118
119 #define SPIE_TXB 0x00000200 /* Last char is written to tx fifo */
120 #define SPIE_RXB 0x00000100 /* Last char is written to rx buf */
121
122 /* SPCOM register values */
123 #define SPCOM_STR (1 << 23) /* Start transmit */
124
125 #define SPI_PRAM_SIZE 0x100
126 #define SPI_MRBLR ((unsigned int)PAGE_SIZE)
127
128 /* SPI Controller driver's private data. */
129 struct mpc8xxx_spi {
130 struct device *dev;
131 struct mpc8xxx_spi_reg __iomem *base;
132
133 /* rx & tx bufs from the spi_transfer */
134 const void *tx;
135 void *rx;
136
137 int subblock;
138 struct spi_pram __iomem *pram;
139 struct cpm_buf_desc __iomem *tx_bd;
140 struct cpm_buf_desc __iomem *rx_bd;
141
142 struct spi_transfer *xfer_in_progress;
143
144 /* dma addresses for CPM transfers */
145 dma_addr_t tx_dma;
146 dma_addr_t rx_dma;
147 bool map_tx_dma;
148 bool map_rx_dma;
149
150 dma_addr_t dma_dummy_tx;
151 dma_addr_t dma_dummy_rx;
152
153 /* functions to deal with different sized buffers */
154 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
155 u32(*get_tx) (struct mpc8xxx_spi *);
156
157 unsigned int count;
158 unsigned int irq;
159
160 unsigned nsecs; /* (clock cycle time)/2 */
161
162 u32 spibrg; /* SPIBRG input clock */
163 u32 rx_shift; /* RX data reg shift when in qe mode */
164 u32 tx_shift; /* TX data reg shift when in qe mode */
165
166 unsigned int flags;
167
168 struct workqueue_struct *workqueue;
169 struct work_struct work;
170
171 struct list_head queue;
172 spinlock_t lock;
173
174 struct completion done;
175 };
176
177 static void *mpc8xxx_dummy_rx;
178 static DEFINE_MUTEX(mpc8xxx_dummy_rx_lock);
179 static int mpc8xxx_dummy_rx_refcnt;
180
181 struct spi_mpc8xxx_cs {
182 /* functions to deal with different sized buffers */
183 void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
184 u32 (*get_tx) (struct mpc8xxx_spi *);
185 u32 rx_shift; /* RX data reg shift when in qe mode */
186 u32 tx_shift; /* TX data reg shift when in qe mode */
187 u32 hw_mode; /* Holds HW mode register settings */
188 };
189
190 static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
191 {
192 out_be32(reg, val);
193 }
194
195 static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
196 {
197 return in_be32(reg);
198 }
199
200 #define MPC83XX_SPI_RX_BUF(type) \
201 static \
202 void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
203 { \
204 type *rx = mpc8xxx_spi->rx; \
205 *rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \
206 mpc8xxx_spi->rx = rx; \
207 }
208
209 #define MPC83XX_SPI_TX_BUF(type) \
210 static \
211 u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
212 { \
213 u32 data; \
214 const type *tx = mpc8xxx_spi->tx; \
215 if (!tx) \
216 return 0; \
217 data = *tx++ << mpc8xxx_spi->tx_shift; \
218 mpc8xxx_spi->tx = tx; \
219 return data; \
220 }
221
222 MPC83XX_SPI_RX_BUF(u8)
223 MPC83XX_SPI_RX_BUF(u16)
224 MPC83XX_SPI_RX_BUF(u32)
225 MPC83XX_SPI_TX_BUF(u8)
226 MPC83XX_SPI_TX_BUF(u16)
227 MPC83XX_SPI_TX_BUF(u32)
228
229 static void mpc8xxx_spi_change_mode(struct spi_device *spi)
230 {
231 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
232 struct spi_mpc8xxx_cs *cs = spi->controller_state;
233 __be32 __iomem *mode = &mspi->base->mode;
234 unsigned long flags;
235
236 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
237 return;
238
239 /* Turn off IRQs locally to minimize time that SPI is disabled. */
240 local_irq_save(flags);
241
242 /* Turn off SPI unit prior changing mode */
243 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
244 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
245
246 /* When in CPM mode, we need to reinit tx and rx. */
247 if (mspi->flags & SPI_CPM_MODE) {
248 if (mspi->flags & SPI_QE) {
249 qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock,
250 QE_CR_PROTOCOL_UNSPECIFIED, 0);
251 } else {
252 cpm_command(CPM_SPI_CMD, CPM_CR_INIT_TRX);
253 if (mspi->flags & SPI_CPM1) {
254 out_be16(&mspi->pram->rbptr,
255 in_be16(&mspi->pram->rbase));
256 out_be16(&mspi->pram->tbptr,
257 in_be16(&mspi->pram->tbase));
258 }
259 }
260 }
261
262 local_irq_restore(flags);
263 }
264
265 static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value)
266 {
267 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
268 struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
269 bool pol = spi->mode & SPI_CS_HIGH;
270 struct spi_mpc8xxx_cs *cs = spi->controller_state;
271
272 if (value == BITBANG_CS_INACTIVE) {
273 if (pdata->cs_control)
274 pdata->cs_control(spi, !pol);
275 }
276
277 if (value == BITBANG_CS_ACTIVE) {
278 mpc8xxx_spi->rx_shift = cs->rx_shift;
279 mpc8xxx_spi->tx_shift = cs->tx_shift;
280 mpc8xxx_spi->get_rx = cs->get_rx;
281 mpc8xxx_spi->get_tx = cs->get_tx;
282
283 mpc8xxx_spi_change_mode(spi);
284
285 if (pdata->cs_control)
286 pdata->cs_control(spi, pol);
287 }
288 }
289
290 static
291 int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
292 {
293 struct mpc8xxx_spi *mpc8xxx_spi;
294 u8 bits_per_word, pm;
295 u32 hz;
296 struct spi_mpc8xxx_cs *cs = spi->controller_state;
297
298 mpc8xxx_spi = spi_master_get_devdata(spi->master);
299
300 if (t) {
301 bits_per_word = t->bits_per_word;
302 hz = t->speed_hz;
303 } else {
304 bits_per_word = 0;
305 hz = 0;
306 }
307
308 /* spi_transfer level calls that work per-word */
309 if (!bits_per_word)
310 bits_per_word = spi->bits_per_word;
311
312 /* Make sure its a bit width we support [4..16, 32] */
313 if ((bits_per_word < 4)
314 || ((bits_per_word > 16) && (bits_per_word != 32)))
315 return -EINVAL;
316
317 if (!hz)
318 hz = spi->max_speed_hz;
319
320 cs->rx_shift = 0;
321 cs->tx_shift = 0;
322 if (bits_per_word <= 8) {
323 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
324 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
325 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
326 cs->rx_shift = 16;
327 cs->tx_shift = 24;
328 }
329 } else if (bits_per_word <= 16) {
330 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
331 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
332 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
333 cs->rx_shift = 16;
334 cs->tx_shift = 16;
335 }
336 } else if (bits_per_word <= 32) {
337 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
338 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
339 } else
340 return -EINVAL;
341
342 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE &&
343 spi->mode & SPI_LSB_FIRST) {
344 cs->tx_shift = 0;
345 if (bits_per_word <= 8)
346 cs->rx_shift = 8;
347 else
348 cs->rx_shift = 0;
349 }
350
351 mpc8xxx_spi->rx_shift = cs->rx_shift;
352 mpc8xxx_spi->tx_shift = cs->tx_shift;
353 mpc8xxx_spi->get_rx = cs->get_rx;
354 mpc8xxx_spi->get_tx = cs->get_tx;
355
356 if (bits_per_word == 32)
357 bits_per_word = 0;
358 else
359 bits_per_word = bits_per_word - 1;
360
361 /* mask out bits we are going to set */
362 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
363 | SPMODE_PM(0xF));
364
365 cs->hw_mode |= SPMODE_LEN(bits_per_word);
366
367 if ((mpc8xxx_spi->spibrg / hz) > 64) {
368 cs->hw_mode |= SPMODE_DIV16;
369 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
370
371 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
372 "Will use %d Hz instead.\n", dev_name(&spi->dev),
373 hz, mpc8xxx_spi->spibrg / 1024);
374 if (pm > 16)
375 pm = 16;
376 } else
377 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
378 if (pm)
379 pm--;
380
381 cs->hw_mode |= SPMODE_PM(pm);
382
383 mpc8xxx_spi_change_mode(spi);
384 return 0;
385 }
386
387 static void mpc8xxx_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
388 {
389 struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd;
390 struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd;
391 unsigned int xfer_len = min(mspi->count, SPI_MRBLR);
392 unsigned int xfer_ofs;
393
394 xfer_ofs = mspi->xfer_in_progress->len - mspi->count;
395
396 out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma + xfer_ofs);
397 out_be16(&rx_bd->cbd_datlen, 0);
398 out_be16(&rx_bd->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT | BD_SC_WRAP);
399
400 out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma + xfer_ofs);
401 out_be16(&tx_bd->cbd_datlen, xfer_len);
402 out_be16(&tx_bd->cbd_sc, BD_SC_READY | BD_SC_INTRPT | BD_SC_WRAP |
403 BD_SC_LAST);
404
405 /* start transfer */
406 mpc8xxx_spi_write_reg(&mspi->base->command, SPCOM_STR);
407 }
408
409 static int mpc8xxx_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
410 struct spi_transfer *t, bool is_dma_mapped)
411 {
412 struct device *dev = mspi->dev;
413
414 if (is_dma_mapped) {
415 mspi->map_tx_dma = 0;
416 mspi->map_rx_dma = 0;
417 } else {
418 mspi->map_tx_dma = 1;
419 mspi->map_rx_dma = 1;
420 }
421
422 if (!t->tx_buf) {
423 mspi->tx_dma = mspi->dma_dummy_tx;
424 mspi->map_tx_dma = 0;
425 }
426
427 if (!t->rx_buf) {
428 mspi->rx_dma = mspi->dma_dummy_rx;
429 mspi->map_rx_dma = 0;
430 }
431
432 if (mspi->map_tx_dma) {
433 void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */
434
435 mspi->tx_dma = dma_map_single(dev, nonconst_tx, t->len,
436 DMA_TO_DEVICE);
437 if (dma_mapping_error(dev, mspi->tx_dma)) {
438 dev_err(dev, "unable to map tx dma\n");
439 return -ENOMEM;
440 }
441 } else {
442 mspi->tx_dma = t->tx_dma;
443 }
444
445 if (mspi->map_rx_dma) {
446 mspi->rx_dma = dma_map_single(dev, mspi->rx, t->len,
447 DMA_FROM_DEVICE);
448 if (dma_mapping_error(dev, mspi->rx_dma)) {
449 dev_err(dev, "unable to map rx dma\n");
450 goto err_rx_dma;
451 }
452 } else {
453 mspi->rx_dma = t->rx_dma;
454 }
455
456 /* enable rx ints */
457 mpc8xxx_spi_write_reg(&mspi->base->mask, SPIE_RXB);
458
459 mspi->xfer_in_progress = t;
460 mspi->count = t->len;
461
462 /* start CPM transfers */
463 mpc8xxx_spi_cpm_bufs_start(mspi);
464
465 return 0;
466
467 err_rx_dma:
468 if (mspi->map_tx_dma)
469 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
470 return -ENOMEM;
471 }
472
473 static void mpc8xxx_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
474 {
475 struct device *dev = mspi->dev;
476 struct spi_transfer *t = mspi->xfer_in_progress;
477
478 if (mspi->map_tx_dma)
479 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
480 if (mspi->map_tx_dma)
481 dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE);
482 mspi->xfer_in_progress = NULL;
483 }
484
485 static int mpc8xxx_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
486 struct spi_transfer *t, unsigned int len)
487 {
488 u32 word;
489
490 mspi->count = len;
491
492 /* enable rx ints */
493 mpc8xxx_spi_write_reg(&mspi->base->mask, SPIM_NE);
494
495 /* transmit word */
496 word = mspi->get_tx(mspi);
497 mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
498
499 return 0;
500 }
501
502 static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
503 bool is_dma_mapped)
504 {
505 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
506 unsigned int len = t->len;
507 u8 bits_per_word;
508 int ret;
509
510 bits_per_word = spi->bits_per_word;
511 if (t->bits_per_word)
512 bits_per_word = t->bits_per_word;
513
514 if (bits_per_word > 8) {
515 /* invalid length? */
516 if (len & 1)
517 return -EINVAL;
518 len /= 2;
519 }
520 if (bits_per_word > 16) {
521 /* invalid length? */
522 if (len & 1)
523 return -EINVAL;
524 len /= 2;
525 }
526
527 mpc8xxx_spi->tx = t->tx_buf;
528 mpc8xxx_spi->rx = t->rx_buf;
529
530 INIT_COMPLETION(mpc8xxx_spi->done);
531
532 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
533 ret = mpc8xxx_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
534 else
535 ret = mpc8xxx_spi_cpu_bufs(mpc8xxx_spi, t, len);
536 if (ret)
537 return ret;
538
539 wait_for_completion(&mpc8xxx_spi->done);
540
541 /* disable rx ints */
542 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
543
544 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
545 mpc8xxx_spi_cpm_bufs_complete(mpc8xxx_spi);
546
547 return mpc8xxx_spi->count;
548 }
549
550 static void mpc8xxx_spi_do_one_msg(struct spi_message *m)
551 {
552 struct spi_device *spi = m->spi;
553 struct spi_transfer *t;
554 unsigned int cs_change;
555 const int nsecs = 50;
556 int status;
557
558 cs_change = 1;
559 status = 0;
560 list_for_each_entry(t, &m->transfers, transfer_list) {
561 if (t->bits_per_word || t->speed_hz) {
562 /* Don't allow changes if CS is active */
563 status = -EINVAL;
564
565 if (cs_change)
566 status = mpc8xxx_spi_setup_transfer(spi, t);
567 if (status < 0)
568 break;
569 }
570
571 if (cs_change) {
572 mpc8xxx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
573 ndelay(nsecs);
574 }
575 cs_change = t->cs_change;
576 if (t->len)
577 status = mpc8xxx_spi_bufs(spi, t, m->is_dma_mapped);
578 if (status) {
579 status = -EMSGSIZE;
580 break;
581 }
582 m->actual_length += t->len;
583
584 if (t->delay_usecs)
585 udelay(t->delay_usecs);
586
587 if (cs_change) {
588 ndelay(nsecs);
589 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
590 ndelay(nsecs);
591 }
592 }
593
594 m->status = status;
595 m->complete(m->context);
596
597 if (status || !cs_change) {
598 ndelay(nsecs);
599 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
600 }
601
602 mpc8xxx_spi_setup_transfer(spi, NULL);
603 }
604
605 static void mpc8xxx_spi_work(struct work_struct *work)
606 {
607 struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
608 work);
609
610 spin_lock_irq(&mpc8xxx_spi->lock);
611 while (!list_empty(&mpc8xxx_spi->queue)) {
612 struct spi_message *m = container_of(mpc8xxx_spi->queue.next,
613 struct spi_message, queue);
614
615 list_del_init(&m->queue);
616 spin_unlock_irq(&mpc8xxx_spi->lock);
617
618 mpc8xxx_spi_do_one_msg(m);
619
620 spin_lock_irq(&mpc8xxx_spi->lock);
621 }
622 spin_unlock_irq(&mpc8xxx_spi->lock);
623 }
624
625 static int mpc8xxx_spi_setup(struct spi_device *spi)
626 {
627 struct mpc8xxx_spi *mpc8xxx_spi;
628 int retval;
629 u32 hw_mode;
630 struct spi_mpc8xxx_cs *cs = spi->controller_state;
631
632 if (!spi->max_speed_hz)
633 return -EINVAL;
634
635 if (!cs) {
636 cs = kzalloc(sizeof *cs, GFP_KERNEL);
637 if (!cs)
638 return -ENOMEM;
639 spi->controller_state = cs;
640 }
641 mpc8xxx_spi = spi_master_get_devdata(spi->master);
642
643 hw_mode = cs->hw_mode; /* Save orginal settings */
644 cs->hw_mode = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode);
645 /* mask out bits we are going to set */
646 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
647 | SPMODE_REV | SPMODE_LOOP);
648
649 if (spi->mode & SPI_CPHA)
650 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
651 if (spi->mode & SPI_CPOL)
652 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
653 if (!(spi->mode & SPI_LSB_FIRST))
654 cs->hw_mode |= SPMODE_REV;
655 if (spi->mode & SPI_LOOP)
656 cs->hw_mode |= SPMODE_LOOP;
657
658 retval = mpc8xxx_spi_setup_transfer(spi, NULL);
659 if (retval < 0) {
660 cs->hw_mode = hw_mode; /* Restore settings */
661 return retval;
662 }
663 return 0;
664 }
665
666 static void mpc8xxx_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
667 {
668 u16 len;
669
670 dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__,
671 in_be16(&mspi->rx_bd->cbd_datlen), mspi->count);
672
673 len = in_be16(&mspi->rx_bd->cbd_datlen);
674 if (len > mspi->count) {
675 WARN_ON(1);
676 len = mspi->count;
677 }
678
679 /* Clear the events */
680 mpc8xxx_spi_write_reg(&mspi->base->event, events);
681
682 mspi->count -= len;
683 if (mspi->count)
684 mpc8xxx_spi_cpm_bufs_start(mspi);
685 else
686 complete(&mspi->done);
687 }
688
689 static void mpc8xxx_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
690 {
691 /* We need handle RX first */
692 if (events & SPIE_NE) {
693 u32 rx_data = mpc8xxx_spi_read_reg(&mspi->base->receive);
694
695 if (mspi->rx)
696 mspi->get_rx(rx_data, mspi);
697 }
698
699 if ((events & SPIE_NF) == 0)
700 /* spin until TX is done */
701 while (((events =
702 mpc8xxx_spi_read_reg(&mspi->base->event)) &
703 SPIE_NF) == 0)
704 cpu_relax();
705
706 /* Clear the events */
707 mpc8xxx_spi_write_reg(&mspi->base->event, events);
708
709 mspi->count -= 1;
710 if (mspi->count) {
711 u32 word = mspi->get_tx(mspi);
712
713 mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
714 } else {
715 complete(&mspi->done);
716 }
717 }
718
719 static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data)
720 {
721 struct mpc8xxx_spi *mspi = context_data;
722 irqreturn_t ret = IRQ_NONE;
723 u32 events;
724
725 /* Get interrupt events(tx/rx) */
726 events = mpc8xxx_spi_read_reg(&mspi->base->event);
727 if (events)
728 ret = IRQ_HANDLED;
729
730 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
731
732 if (mspi->flags & SPI_CPM_MODE)
733 mpc8xxx_spi_cpm_irq(mspi, events);
734 else
735 mpc8xxx_spi_cpu_irq(mspi, events);
736
737 return ret;
738 }
739
740 static int mpc8xxx_spi_transfer(struct spi_device *spi,
741 struct spi_message *m)
742 {
743 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
744 unsigned long flags;
745
746 m->actual_length = 0;
747 m->status = -EINPROGRESS;
748
749 spin_lock_irqsave(&mpc8xxx_spi->lock, flags);
750 list_add_tail(&m->queue, &mpc8xxx_spi->queue);
751 queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
752 spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags);
753
754 return 0;
755 }
756
757
758 static void mpc8xxx_spi_cleanup(struct spi_device *spi)
759 {
760 kfree(spi->controller_state);
761 }
762
763 static void *mpc8xxx_spi_alloc_dummy_rx(void)
764 {
765 mutex_lock(&mpc8xxx_dummy_rx_lock);
766
767 if (!mpc8xxx_dummy_rx)
768 mpc8xxx_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL);
769 if (mpc8xxx_dummy_rx)
770 mpc8xxx_dummy_rx_refcnt++;
771
772 mutex_unlock(&mpc8xxx_dummy_rx_lock);
773
774 return mpc8xxx_dummy_rx;
775 }
776
777 static void mpc8xxx_spi_free_dummy_rx(void)
778 {
779 mutex_lock(&mpc8xxx_dummy_rx_lock);
780
781 switch (mpc8xxx_dummy_rx_refcnt) {
782 case 0:
783 WARN_ON(1);
784 break;
785 case 1:
786 kfree(mpc8xxx_dummy_rx);
787 mpc8xxx_dummy_rx = NULL;
788 /* fall through */
789 default:
790 mpc8xxx_dummy_rx_refcnt--;
791 break;
792 }
793
794 mutex_unlock(&mpc8xxx_dummy_rx_lock);
795 }
796
797 static unsigned long mpc8xxx_spi_cpm_get_pram(struct mpc8xxx_spi *mspi)
798 {
799 struct device *dev = mspi->dev;
800 struct device_node *np = dev_archdata_get_node(&dev->archdata);
801 const u32 *iprop;
802 int size;
803 unsigned long spi_base_ofs;
804 unsigned long pram_ofs = -ENOMEM;
805
806 /* Can't use of_address_to_resource(), QE muram isn't at 0. */
807 iprop = of_get_property(np, "reg", &size);
808
809 /* QE with a fixed pram location? */
810 if (mspi->flags & SPI_QE && iprop && size == sizeof(*iprop) * 4)
811 return cpm_muram_alloc_fixed(iprop[2], SPI_PRAM_SIZE);
812
813 /* QE but with a dynamic pram location? */
814 if (mspi->flags & SPI_QE) {
815 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
816 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, mspi->subblock,
817 QE_CR_PROTOCOL_UNSPECIFIED, pram_ofs);
818 return pram_ofs;
819 }
820
821 /* CPM1 and CPM2 pram must be at a fixed addr. */
822 if (!iprop || size != sizeof(*iprop) * 4)
823 return -ENOMEM;
824
825 spi_base_ofs = cpm_muram_alloc_fixed(iprop[2], 2);
826 if (IS_ERR_VALUE(spi_base_ofs))
827 return -ENOMEM;
828
829 if (mspi->flags & SPI_CPM2) {
830 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
831 if (!IS_ERR_VALUE(pram_ofs)) {
832 u16 __iomem *spi_base = cpm_muram_addr(spi_base_ofs);
833
834 out_be16(spi_base, pram_ofs);
835 }
836 } else {
837 struct spi_pram __iomem *pram = cpm_muram_addr(spi_base_ofs);
838 u16 rpbase = in_be16(&pram->rpbase);
839
840 /* Microcode relocation patch applied? */
841 if (rpbase)
842 pram_ofs = rpbase;
843 else
844 return spi_base_ofs;
845 }
846
847 cpm_muram_free(spi_base_ofs);
848 return pram_ofs;
849 }
850
851 static int mpc8xxx_spi_cpm_init(struct mpc8xxx_spi *mspi)
852 {
853 struct device *dev = mspi->dev;
854 struct device_node *np = dev_archdata_get_node(&dev->archdata);
855 const u32 *iprop;
856 int size;
857 unsigned long pram_ofs;
858 unsigned long bds_ofs;
859
860 if (!(mspi->flags & SPI_CPM_MODE))
861 return 0;
862
863 if (!mpc8xxx_spi_alloc_dummy_rx())
864 return -ENOMEM;
865
866 if (mspi->flags & SPI_QE) {
867 iprop = of_get_property(np, "cell-index", &size);
868 if (iprop && size == sizeof(*iprop))
869 mspi->subblock = *iprop;
870
871 switch (mspi->subblock) {
872 default:
873 dev_warn(dev, "cell-index unspecified, assuming SPI1");
874 /* fall through */
875 case 0:
876 mspi->subblock = QE_CR_SUBBLOCK_SPI1;
877 break;
878 case 1:
879 mspi->subblock = QE_CR_SUBBLOCK_SPI2;
880 break;
881 }
882 }
883
884 pram_ofs = mpc8xxx_spi_cpm_get_pram(mspi);
885 if (IS_ERR_VALUE(pram_ofs)) {
886 dev_err(dev, "can't allocate spi parameter ram\n");
887 goto err_pram;
888 }
889
890 bds_ofs = cpm_muram_alloc(sizeof(*mspi->tx_bd) +
891 sizeof(*mspi->rx_bd), 8);
892 if (IS_ERR_VALUE(bds_ofs)) {
893 dev_err(dev, "can't allocate bds\n");
894 goto err_bds;
895 }
896
897 mspi->dma_dummy_tx = dma_map_single(dev, empty_zero_page, PAGE_SIZE,
898 DMA_TO_DEVICE);
899 if (dma_mapping_error(dev, mspi->dma_dummy_tx)) {
900 dev_err(dev, "unable to map dummy tx buffer\n");
901 goto err_dummy_tx;
902 }
903
904 mspi->dma_dummy_rx = dma_map_single(dev, mpc8xxx_dummy_rx, SPI_MRBLR,
905 DMA_FROM_DEVICE);
906 if (dma_mapping_error(dev, mspi->dma_dummy_rx)) {
907 dev_err(dev, "unable to map dummy rx buffer\n");
908 goto err_dummy_rx;
909 }
910
911 mspi->pram = cpm_muram_addr(pram_ofs);
912
913 mspi->tx_bd = cpm_muram_addr(bds_ofs);
914 mspi->rx_bd = cpm_muram_addr(bds_ofs + sizeof(*mspi->tx_bd));
915
916 /* Initialize parameter ram. */
917 out_be16(&mspi->pram->tbase, cpm_muram_offset(mspi->tx_bd));
918 out_be16(&mspi->pram->rbase, cpm_muram_offset(mspi->rx_bd));
919 out_8(&mspi->pram->tfcr, CPMFCR_EB | CPMFCR_GBL);
920 out_8(&mspi->pram->rfcr, CPMFCR_EB | CPMFCR_GBL);
921 out_be16(&mspi->pram->mrblr, SPI_MRBLR);
922 out_be32(&mspi->pram->rstate, 0);
923 out_be32(&mspi->pram->rdp, 0);
924 out_be16(&mspi->pram->rbptr, 0);
925 out_be16(&mspi->pram->rbc, 0);
926 out_be32(&mspi->pram->rxtmp, 0);
927 out_be32(&mspi->pram->tstate, 0);
928 out_be32(&mspi->pram->tdp, 0);
929 out_be16(&mspi->pram->tbptr, 0);
930 out_be16(&mspi->pram->tbc, 0);
931 out_be32(&mspi->pram->txtmp, 0);
932
933 return 0;
934
935 err_dummy_rx:
936 dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
937 err_dummy_tx:
938 cpm_muram_free(bds_ofs);
939 err_bds:
940 cpm_muram_free(pram_ofs);
941 err_pram:
942 mpc8xxx_spi_free_dummy_rx();
943 return -ENOMEM;
944 }
945
946 static void mpc8xxx_spi_cpm_free(struct mpc8xxx_spi *mspi)
947 {
948 struct device *dev = mspi->dev;
949
950 dma_unmap_single(dev, mspi->dma_dummy_rx, SPI_MRBLR, DMA_FROM_DEVICE);
951 dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
952 cpm_muram_free(cpm_muram_offset(mspi->tx_bd));
953 cpm_muram_free(cpm_muram_offset(mspi->pram));
954 mpc8xxx_spi_free_dummy_rx();
955 }
956
957 static const char *mpc8xxx_spi_strmode(unsigned int flags)
958 {
959 if (flags & SPI_QE_CPU_MODE) {
960 return "QE CPU";
961 } else if (flags & SPI_CPM_MODE) {
962 if (flags & SPI_QE)
963 return "QE";
964 else if (flags & SPI_CPM2)
965 return "CPM2";
966 else
967 return "CPM1";
968 }
969 return "CPU";
970 }
971
972 static struct spi_master * __devinit
973 mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
974 {
975 struct fsl_spi_platform_data *pdata = dev->platform_data;
976 struct spi_master *master;
977 struct mpc8xxx_spi *mpc8xxx_spi;
978 u32 regval;
979 int ret = 0;
980
981 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
982 if (master == NULL) {
983 ret = -ENOMEM;
984 goto err;
985 }
986
987 dev_set_drvdata(dev, master);
988
989 /* the spi->mode bits understood by this driver: */
990 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
991 | SPI_LSB_FIRST | SPI_LOOP;
992
993 master->setup = mpc8xxx_spi_setup;
994 master->transfer = mpc8xxx_spi_transfer;
995 master->cleanup = mpc8xxx_spi_cleanup;
996
997 mpc8xxx_spi = spi_master_get_devdata(master);
998 mpc8xxx_spi->dev = dev;
999 mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
1000 mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
1001 mpc8xxx_spi->flags = pdata->flags;
1002 mpc8xxx_spi->spibrg = pdata->sysclk;
1003
1004 ret = mpc8xxx_spi_cpm_init(mpc8xxx_spi);
1005 if (ret)
1006 goto err_cpm_init;
1007
1008 mpc8xxx_spi->rx_shift = 0;
1009 mpc8xxx_spi->tx_shift = 0;
1010 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
1011 mpc8xxx_spi->rx_shift = 16;
1012 mpc8xxx_spi->tx_shift = 24;
1013 }
1014
1015 init_completion(&mpc8xxx_spi->done);
1016
1017 mpc8xxx_spi->base = ioremap(mem->start, resource_size(mem));
1018 if (mpc8xxx_spi->base == NULL) {
1019 ret = -ENOMEM;
1020 goto err_ioremap;
1021 }
1022
1023 mpc8xxx_spi->irq = irq;
1024
1025 /* Register for SPI Interrupt */
1026 ret = request_irq(mpc8xxx_spi->irq, mpc8xxx_spi_irq,
1027 0, "mpc8xxx_spi", mpc8xxx_spi);
1028
1029 if (ret != 0)
1030 goto unmap_io;
1031
1032 master->bus_num = pdata->bus_num;
1033 master->num_chipselect = pdata->max_chipselect;
1034
1035 /* SPI controller initializations */
1036 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, 0);
1037 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
1038 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->command, 0);
1039 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, 0xffffffff);
1040
1041 /* Enable SPI interface */
1042 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
1043 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
1044 regval |= SPMODE_OP;
1045
1046 mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, regval);
1047 spin_lock_init(&mpc8xxx_spi->lock);
1048 init_completion(&mpc8xxx_spi->done);
1049 INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work);
1050 INIT_LIST_HEAD(&mpc8xxx_spi->queue);
1051
1052 mpc8xxx_spi->workqueue = create_singlethread_workqueue(
1053 dev_name(master->dev.parent));
1054 if (mpc8xxx_spi->workqueue == NULL) {
1055 ret = -EBUSY;
1056 goto free_irq;
1057 }
1058
1059 ret = spi_register_master(master);
1060 if (ret < 0)
1061 goto unreg_master;
1062
1063 dev_info(dev, "at 0x%p (irq = %d), %s mode\n", mpc8xxx_spi->base,
1064 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
1065
1066 return master;
1067
1068 unreg_master:
1069 destroy_workqueue(mpc8xxx_spi->workqueue);
1070 free_irq:
1071 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
1072 unmap_io:
1073 iounmap(mpc8xxx_spi->base);
1074 err_ioremap:
1075 mpc8xxx_spi_cpm_free(mpc8xxx_spi);
1076 err_cpm_init:
1077 spi_master_put(master);
1078 err:
1079 return ERR_PTR(ret);
1080 }
1081
1082 static int __devexit mpc8xxx_spi_remove(struct device *dev)
1083 {
1084 struct mpc8xxx_spi *mpc8xxx_spi;
1085 struct spi_master *master;
1086
1087 master = dev_get_drvdata(dev);
1088 mpc8xxx_spi = spi_master_get_devdata(master);
1089
1090 flush_workqueue(mpc8xxx_spi->workqueue);
1091 destroy_workqueue(mpc8xxx_spi->workqueue);
1092 spi_unregister_master(master);
1093
1094 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
1095 iounmap(mpc8xxx_spi->base);
1096 mpc8xxx_spi_cpm_free(mpc8xxx_spi);
1097
1098 return 0;
1099 }
1100
1101 struct mpc8xxx_spi_probe_info {
1102 struct fsl_spi_platform_data pdata;
1103 int *gpios;
1104 bool *alow_flags;
1105 };
1106
1107 static struct mpc8xxx_spi_probe_info *
1108 to_of_pinfo(struct fsl_spi_platform_data *pdata)
1109 {
1110 return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
1111 }
1112
1113 static void mpc8xxx_spi_cs_control(struct spi_device *spi, bool on)
1114 {
1115 struct device *dev = spi->dev.parent;
1116 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
1117 u16 cs = spi->chip_select;
1118 int gpio = pinfo->gpios[cs];
1119 bool alow = pinfo->alow_flags[cs];
1120
1121 gpio_set_value(gpio, on ^ alow);
1122 }
1123
1124 static int of_mpc8xxx_spi_get_chipselects(struct device *dev)
1125 {
1126 struct device_node *np = dev_archdata_get_node(&dev->archdata);
1127 struct fsl_spi_platform_data *pdata = dev->platform_data;
1128 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
1129 unsigned int ngpios;
1130 int i = 0;
1131 int ret;
1132
1133 ngpios = of_gpio_count(np);
1134 if (!ngpios) {
1135 /*
1136 * SPI w/o chip-select line. One SPI device is still permitted
1137 * though.
1138 */
1139 pdata->max_chipselect = 1;
1140 return 0;
1141 }
1142
1143 pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
1144 if (!pinfo->gpios)
1145 return -ENOMEM;
1146 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
1147
1148 pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
1149 GFP_KERNEL);
1150 if (!pinfo->alow_flags) {
1151 ret = -ENOMEM;
1152 goto err_alloc_flags;
1153 }
1154
1155 for (; i < ngpios; i++) {
1156 int gpio;
1157 enum of_gpio_flags flags;
1158
1159 gpio = of_get_gpio_flags(np, i, &flags);
1160 if (!gpio_is_valid(gpio)) {
1161 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
1162 ret = gpio;
1163 goto err_loop;
1164 }
1165
1166 ret = gpio_request(gpio, dev_name(dev));
1167 if (ret) {
1168 dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
1169 goto err_loop;
1170 }
1171
1172 pinfo->gpios[i] = gpio;
1173 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
1174
1175 ret = gpio_direction_output(pinfo->gpios[i],
1176 pinfo->alow_flags[i]);
1177 if (ret) {
1178 dev_err(dev, "can't set output direction for gpio "
1179 "#%d: %d\n", i, ret);
1180 goto err_loop;
1181 }
1182 }
1183
1184 pdata->max_chipselect = ngpios;
1185 pdata->cs_control = mpc8xxx_spi_cs_control;
1186
1187 return 0;
1188
1189 err_loop:
1190 while (i >= 0) {
1191 if (gpio_is_valid(pinfo->gpios[i]))
1192 gpio_free(pinfo->gpios[i]);
1193 i--;
1194 }
1195
1196 kfree(pinfo->alow_flags);
1197 pinfo->alow_flags = NULL;
1198 err_alloc_flags:
1199 kfree(pinfo->gpios);
1200 pinfo->gpios = NULL;
1201 return ret;
1202 }
1203
1204 static int of_mpc8xxx_spi_free_chipselects(struct device *dev)
1205 {
1206 struct fsl_spi_platform_data *pdata = dev->platform_data;
1207 struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
1208 int i;
1209
1210 if (!pinfo->gpios)
1211 return 0;
1212
1213 for (i = 0; i < pdata->max_chipselect; i++) {
1214 if (gpio_is_valid(pinfo->gpios[i]))
1215 gpio_free(pinfo->gpios[i]);
1216 }
1217
1218 kfree(pinfo->gpios);
1219 kfree(pinfo->alow_flags);
1220 return 0;
1221 }
1222
1223 static int __devinit of_mpc8xxx_spi_probe(struct of_device *ofdev,
1224 const struct of_device_id *ofid)
1225 {
1226 struct device *dev = &ofdev->dev;
1227 struct device_node *np = ofdev->node;
1228 struct mpc8xxx_spi_probe_info *pinfo;
1229 struct fsl_spi_platform_data *pdata;
1230 struct spi_master *master;
1231 struct resource mem;
1232 struct resource irq;
1233 const void *prop;
1234 int ret = -ENOMEM;
1235
1236 pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL);
1237 if (!pinfo)
1238 return -ENOMEM;
1239
1240 pdata = &pinfo->pdata;
1241 dev->platform_data = pdata;
1242
1243 /* Allocate bus num dynamically. */
1244 pdata->bus_num = -1;
1245
1246 /* SPI controller is either clocked from QE or SoC clock. */
1247 pdata->sysclk = get_brgfreq();
1248 if (pdata->sysclk == -1) {
1249 pdata->sysclk = fsl_get_sys_freq();
1250 if (pdata->sysclk == -1) {
1251 ret = -ENODEV;
1252 goto err_clk;
1253 }
1254 }
1255
1256 prop = of_get_property(np, "mode", NULL);
1257 if (prop && !strcmp(prop, "cpu-qe"))
1258 pdata->flags = SPI_QE_CPU_MODE;
1259 else if (prop && !strcmp(prop, "qe"))
1260 pdata->flags = SPI_CPM_MODE | SPI_QE;
1261 else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
1262 pdata->flags = SPI_CPM_MODE | SPI_CPM2;
1263 else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
1264 pdata->flags = SPI_CPM_MODE | SPI_CPM1;
1265
1266 ret = of_mpc8xxx_spi_get_chipselects(dev);
1267 if (ret)
1268 goto err;
1269
1270 ret = of_address_to_resource(np, 0, &mem);
1271 if (ret)
1272 goto err;
1273
1274 ret = of_irq_to_resource(np, 0, &irq);
1275 if (!ret) {
1276 ret = -EINVAL;
1277 goto err;
1278 }
1279
1280 master = mpc8xxx_spi_probe(dev, &mem, irq.start);
1281 if (IS_ERR(master)) {
1282 ret = PTR_ERR(master);
1283 goto err;
1284 }
1285
1286 of_register_spi_devices(master, np);
1287
1288 return 0;
1289
1290 err:
1291 of_mpc8xxx_spi_free_chipselects(dev);
1292 err_clk:
1293 kfree(pinfo);
1294 return ret;
1295 }
1296
1297 static int __devexit of_mpc8xxx_spi_remove(struct of_device *ofdev)
1298 {
1299 int ret;
1300
1301 ret = mpc8xxx_spi_remove(&ofdev->dev);
1302 if (ret)
1303 return ret;
1304 of_mpc8xxx_spi_free_chipselects(&ofdev->dev);
1305 return 0;
1306 }
1307
1308 static const struct of_device_id of_mpc8xxx_spi_match[] = {
1309 { .compatible = "fsl,spi" },
1310 {},
1311 };
1312 MODULE_DEVICE_TABLE(of, of_mpc8xxx_spi_match);
1313
1314 static struct of_platform_driver of_mpc8xxx_spi_driver = {
1315 .name = "mpc8xxx_spi",
1316 .match_table = of_mpc8xxx_spi_match,
1317 .probe = of_mpc8xxx_spi_probe,
1318 .remove = __devexit_p(of_mpc8xxx_spi_remove),
1319 };
1320
1321 #ifdef CONFIG_MPC832x_RDB
1322 /*
1323 * XXX XXX XXX
1324 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
1325 * only. The driver should go away soon, since newer MPC8323E-RDB's device
1326 * tree can work with OpenFirmware driver. But for now we support old trees
1327 * as well.
1328 */
1329 static int __devinit plat_mpc8xxx_spi_probe(struct platform_device *pdev)
1330 {
1331 struct resource *mem;
1332 int irq;
1333 struct spi_master *master;
1334
1335 if (!pdev->dev.platform_data)
1336 return -EINVAL;
1337
1338 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1339 if (!mem)
1340 return -EINVAL;
1341
1342 irq = platform_get_irq(pdev, 0);
1343 if (irq <= 0)
1344 return -EINVAL;
1345
1346 master = mpc8xxx_spi_probe(&pdev->dev, mem, irq);
1347 if (IS_ERR(master))
1348 return PTR_ERR(master);
1349 return 0;
1350 }
1351
1352 static int __devexit plat_mpc8xxx_spi_remove(struct platform_device *pdev)
1353 {
1354 return mpc8xxx_spi_remove(&pdev->dev);
1355 }
1356
1357 MODULE_ALIAS("platform:mpc8xxx_spi");
1358 static struct platform_driver mpc8xxx_spi_driver = {
1359 .probe = plat_mpc8xxx_spi_probe,
1360 .remove = __devexit_p(plat_mpc8xxx_spi_remove),
1361 .driver = {
1362 .name = "mpc8xxx_spi",
1363 .owner = THIS_MODULE,
1364 },
1365 };
1366
1367 static bool legacy_driver_failed;
1368
1369 static void __init legacy_driver_register(void)
1370 {
1371 legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
1372 }
1373
1374 static void __exit legacy_driver_unregister(void)
1375 {
1376 if (legacy_driver_failed)
1377 return;
1378 platform_driver_unregister(&mpc8xxx_spi_driver);
1379 }
1380 #else
1381 static void __init legacy_driver_register(void) {}
1382 static void __exit legacy_driver_unregister(void) {}
1383 #endif /* CONFIG_MPC832x_RDB */
1384
1385 static int __init mpc8xxx_spi_init(void)
1386 {
1387 legacy_driver_register();
1388 return of_register_platform_driver(&of_mpc8xxx_spi_driver);
1389 }
1390
1391 static void __exit mpc8xxx_spi_exit(void)
1392 {
1393 of_unregister_platform_driver(&of_mpc8xxx_spi_driver);
1394 legacy_driver_unregister();
1395 }
1396
1397 module_init(mpc8xxx_spi_init);
1398 module_exit(mpc8xxx_spi_exit);
1399
1400 MODULE_AUTHOR("Kumar Gala");
1401 MODULE_DESCRIPTION("Simple MPC8xxx SPI Driver");
1402 MODULE_LICENSE("GPL");
Linux with added FPC-III support