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Staging: strip: delete the driver
[linux/fpc-iii.git] / drivers / usb / musb / tusb6010_omap.c
blob5afa070d7dc95aae24fdb0792c3e92e3b05a1b6c
1 /*
2 * TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/errno.h>
14 #include <linux/init.h>
15 #include <linux/usb.h>
16 #include <linux/platform_device.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/slab.h>
19 #include <plat/dma.h>
20 #include <plat/mux.h>
21
22 #include "musb_core.h"
23
24 #define to_chdat(c) ((struct tusb_omap_dma_ch *)(c)->private_data)
25
26 #define MAX_DMAREQ 5 /* REVISIT: Really 6, but req5 not OK */
27
28 struct tusb_omap_dma_ch {
29 struct musb *musb;
30 void __iomem *tbase;
31 unsigned long phys_offset;
32 int epnum;
33 u8 tx;
34 struct musb_hw_ep *hw_ep;
35
36 int ch;
37 s8 dmareq;
38 s8 sync_dev;
39
40 struct tusb_omap_dma *tusb_dma;
41
42 void __iomem *dma_addr;
43
44 u32 len;
45 u16 packet_sz;
46 u16 transfer_packet_sz;
47 u32 transfer_len;
48 u32 completed_len;
49 };
50
51 struct tusb_omap_dma {
52 struct dma_controller controller;
53 struct musb *musb;
54 void __iomem *tbase;
55
56 int ch;
57 s8 dmareq;
58 s8 sync_dev;
59 unsigned multichannel:1;
60 };
61
62 static int tusb_omap_dma_start(struct dma_controller *c)
63 {
64 struct tusb_omap_dma *tusb_dma;
65
66 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
67
68 /* DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
69
70 return 0;
71 }
72
73 static int tusb_omap_dma_stop(struct dma_controller *c)
74 {
75 struct tusb_omap_dma *tusb_dma;
76
77 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
78
79 /* DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
80
81 return 0;
82 }
83
84 /*
85 * Allocate dmareq0 to the current channel unless it's already taken
86 */
87 static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat)
88 {
89 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
90
91 if (reg != 0) {
92 DBG(3, "ep%i dmareq0 is busy for ep%i\n",
93 chdat->epnum, reg & 0xf);
94 return -EAGAIN;
95 }
96
97 if (chdat->tx)
98 reg = (1 << 4) | chdat->epnum;
99 else
100 reg = chdat->epnum;
101
102 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
103
104 return 0;
105 }
106
107 static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat)
108 {
109 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
110
111 if ((reg & 0xf) != chdat->epnum) {
112 printk(KERN_ERR "ep%i trying to release dmareq0 for ep%i\n",
113 chdat->epnum, reg & 0xf);
114 return;
115 }
116 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, 0);
117 }
118
119 /*
120 * See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in
121 * musb_gadget.c.
122 */
123 static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
124 {
125 struct dma_channel *channel = (struct dma_channel *)data;
126 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
127 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
128 struct musb *musb = chdat->musb;
129 struct musb_hw_ep *hw_ep = chdat->hw_ep;
130 void __iomem *ep_conf = hw_ep->conf;
131 void __iomem *mbase = musb->mregs;
132 unsigned long remaining, flags, pio;
133 int ch;
134
135 spin_lock_irqsave(&musb->lock, flags);
136
137 if (tusb_dma->multichannel)
138 ch = chdat->ch;
139 else
140 ch = tusb_dma->ch;
141
142 if (ch_status != OMAP_DMA_BLOCK_IRQ)
143 printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status);
144
145 DBG(3, "ep%i %s dma callback ch: %i status: %x\n",
146 chdat->epnum, chdat->tx ? "tx" : "rx",
147 ch, ch_status);
148
149 if (chdat->tx)
150 remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
151 else
152 remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
153
154 remaining = TUSB_EP_CONFIG_XFR_SIZE(remaining);
155
156 /* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */
157 if (unlikely(remaining > chdat->transfer_len)) {
158 DBG(2, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n",
159 chdat->tx ? "tx" : "rx", chdat->ch,
160 remaining);
161 remaining = 0;
162 }
163
164 channel->actual_len = chdat->transfer_len - remaining;
165 pio = chdat->len - channel->actual_len;
166
167 DBG(3, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len);
168
169 /* Transfer remaining 1 - 31 bytes */
170 if (pio > 0 && pio < 32) {
171 u8 *buf;
172
173 DBG(3, "Using PIO for remaining %lu bytes\n", pio);
174 buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len;
175 if (chdat->tx) {
176 dma_cache_maint(phys_to_virt((u32)chdat->dma_addr),
177 chdat->transfer_len, DMA_TO_DEVICE);
178 musb_write_fifo(hw_ep, pio, buf);
179 } else {
180 musb_read_fifo(hw_ep, pio, buf);
181 dma_cache_maint(phys_to_virt((u32)chdat->dma_addr),
182 chdat->transfer_len, DMA_FROM_DEVICE);
183 }
184 channel->actual_len += pio;
185 }
186
187 if (!tusb_dma->multichannel)
188 tusb_omap_free_shared_dmareq(chdat);
189
190 channel->status = MUSB_DMA_STATUS_FREE;
191
192 /* Handle only RX callbacks here. TX callbacks must be handled based
193 * on the TUSB DMA status interrupt.
194 * REVISIT: Use both TUSB DMA status interrupt and OMAP DMA callback
195 * interrupt for RX and TX.
196 */
197 if (!chdat->tx)
198 musb_dma_completion(musb, chdat->epnum, chdat->tx);
199
200 /* We must terminate short tx transfers manually by setting TXPKTRDY.
201 * REVISIT: This same problem may occur with other MUSB dma as well.
202 * Easy to test with g_ether by pinging the MUSB board with ping -s54.
203 */
204 if ((chdat->transfer_len < chdat->packet_sz)
205 || (chdat->transfer_len % chdat->packet_sz != 0)) {
206 u16 csr;
207
208 if (chdat->tx) {
209 DBG(3, "terminating short tx packet\n");
210 musb_ep_select(mbase, chdat->epnum);
211 csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
212 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
213 | MUSB_TXCSR_P_WZC_BITS;
214 musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
215 }
216 }
217
218 spin_unlock_irqrestore(&musb->lock, flags);
219 }
220
221 static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
222 u8 rndis_mode, dma_addr_t dma_addr, u32 len)
223 {
224 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
225 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
226 struct musb *musb = chdat->musb;
227 struct musb_hw_ep *hw_ep = chdat->hw_ep;
228 void __iomem *mbase = musb->mregs;
229 void __iomem *ep_conf = hw_ep->conf;
230 dma_addr_t fifo = hw_ep->fifo_sync;
231 struct omap_dma_channel_params dma_params;
232 u32 dma_remaining;
233 int src_burst, dst_burst;
234 u16 csr;
235 int ch;
236 s8 dmareq;
237 s8 sync_dev;
238
239 if (unlikely(dma_addr & 0x1) || (len < 32) || (len > packet_sz))
240 return false;
241
242 /*
243 * HW issue #10: Async dma will eventually corrupt the XFR_SIZE
244 * register which will cause missed DMA interrupt. We could try to
245 * use a timer for the callback, but it is unsafe as the XFR_SIZE
246 * register is corrupt, and we won't know if the DMA worked.
247 */
248 if (dma_addr & 0x2)
249 return false;
250
251 /*
252 * Because of HW issue #10, it seems like mixing sync DMA and async
253 * PIO access can confuse the DMA. Make sure XFR_SIZE is reset before
254 * using the channel for DMA.
255 */
256 if (chdat->tx)
257 dma_remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
258 else
259 dma_remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
260
261 dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining);
262 if (dma_remaining) {
263 DBG(2, "Busy %s dma ch%i, not using: %08x\n",
264 chdat->tx ? "tx" : "rx", chdat->ch,
265 dma_remaining);
266 return false;
267 }
268
269 chdat->transfer_len = len & ~0x1f;
270
271 if (len < packet_sz)
272 chdat->transfer_packet_sz = chdat->transfer_len;
273 else
274 chdat->transfer_packet_sz = packet_sz;
275
276 if (tusb_dma->multichannel) {
277 ch = chdat->ch;
278 dmareq = chdat->dmareq;
279 sync_dev = chdat->sync_dev;
280 } else {
281 if (tusb_omap_use_shared_dmareq(chdat) != 0) {
282 DBG(3, "could not get dma for ep%i\n", chdat->epnum);
283 return false;
284 }
285 if (tusb_dma->ch < 0) {
286 /* REVISIT: This should get blocked earlier, happens
287 * with MSC ErrorRecoveryTest
288 */
289 WARN_ON(1);
290 return false;
291 }
292
293 ch = tusb_dma->ch;
294 dmareq = tusb_dma->dmareq;
295 sync_dev = tusb_dma->sync_dev;
296 omap_set_dma_callback(ch, tusb_omap_dma_cb, channel);
297 }
298
299 chdat->packet_sz = packet_sz;
300 chdat->len = len;
301 channel->actual_len = 0;
302 chdat->dma_addr = (void __iomem *)dma_addr;
303 channel->status = MUSB_DMA_STATUS_BUSY;
304
305 /* Since we're recycling dma areas, we need to clean or invalidate */
306 if (chdat->tx)
307 dma_cache_maint(phys_to_virt(dma_addr), len, DMA_TO_DEVICE);
308 else
309 dma_cache_maint(phys_to_virt(dma_addr), len, DMA_FROM_DEVICE);
310
311 /* Use 16-bit transfer if dma_addr is not 32-bit aligned */
312 if ((dma_addr & 0x3) == 0) {
313 dma_params.data_type = OMAP_DMA_DATA_TYPE_S32;
314 dma_params.elem_count = 8; /* Elements in frame */
315 } else {
316 dma_params.data_type = OMAP_DMA_DATA_TYPE_S16;
317 dma_params.elem_count = 16; /* Elements in frame */
318 fifo = hw_ep->fifo_async;
319 }
320
321 dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */
322
323 DBG(3, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n",
324 chdat->epnum, chdat->tx ? "tx" : "rx",
325 ch, dma_addr, chdat->transfer_len, len,
326 chdat->transfer_packet_sz, packet_sz);
327
328 /*
329 * Prepare omap DMA for transfer
330 */
331 if (chdat->tx) {
332 dma_params.src_amode = OMAP_DMA_AMODE_POST_INC;
333 dma_params.src_start = (unsigned long)dma_addr;
334 dma_params.src_ei = 0;
335 dma_params.src_fi = 0;
336
337 dma_params.dst_amode = OMAP_DMA_AMODE_DOUBLE_IDX;
338 dma_params.dst_start = (unsigned long)fifo;
339 dma_params.dst_ei = 1;
340 dma_params.dst_fi = -31; /* Loop 32 byte window */
341
342 dma_params.trigger = sync_dev;
343 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME;
344 dma_params.src_or_dst_synch = 0; /* Dest sync */
345
346 src_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 read */
347 dst_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 write */
348 } else {
349 dma_params.src_amode = OMAP_DMA_AMODE_DOUBLE_IDX;
350 dma_params.src_start = (unsigned long)fifo;
351 dma_params.src_ei = 1;
352 dma_params.src_fi = -31; /* Loop 32 byte window */
353
354 dma_params.dst_amode = OMAP_DMA_AMODE_POST_INC;
355 dma_params.dst_start = (unsigned long)dma_addr;
356 dma_params.dst_ei = 0;
357 dma_params.dst_fi = 0;
358
359 dma_params.trigger = sync_dev;
360 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME;
361 dma_params.src_or_dst_synch = 1; /* Source sync */
362
363 src_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 read */
364 dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */
365 }
366
367 DBG(3, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n",
368 chdat->epnum, chdat->tx ? "tx" : "rx",
369 (dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16,
370 ((dma_addr & 0x3) == 0) ? "sync" : "async",
371 dma_params.src_start, dma_params.dst_start);
372
373 omap_set_dma_params(ch, &dma_params);
374 omap_set_dma_src_burst_mode(ch, src_burst);
375 omap_set_dma_dest_burst_mode(ch, dst_burst);
376 omap_set_dma_write_mode(ch, OMAP_DMA_WRITE_LAST_NON_POSTED);
377
378 /*
379 * Prepare MUSB for DMA transfer
380 */
381 if (chdat->tx) {
382 musb_ep_select(mbase, chdat->epnum);
383 csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
384 csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB
385 | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
386 csr &= ~MUSB_TXCSR_P_UNDERRUN;
387 musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
388 } else {
389 musb_ep_select(mbase, chdat->epnum);
390 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
391 csr |= MUSB_RXCSR_DMAENAB;
392 csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE);
393 musb_writew(hw_ep->regs, MUSB_RXCSR,
394 csr | MUSB_RXCSR_P_WZC_BITS);
395 }
396
397 /*
398 * Start DMA transfer
399 */
400 omap_start_dma(ch);
401
402 if (chdat->tx) {
403 /* Send transfer_packet_sz packets at a time */
404 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET,
405 chdat->transfer_packet_sz);
406
407 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
408 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
409 } else {
410 /* Receive transfer_packet_sz packets at a time */
411 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET,
412 chdat->transfer_packet_sz << 16);
413
414 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
415 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
416 }
417
418 return true;
419 }
420
421 static int tusb_omap_dma_abort(struct dma_channel *channel)
422 {
423 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
424 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
425
426 if (!tusb_dma->multichannel) {
427 if (tusb_dma->ch >= 0) {
428 omap_stop_dma(tusb_dma->ch);
429 omap_free_dma(tusb_dma->ch);
430 tusb_dma->ch = -1;
431 }
432
433 tusb_dma->dmareq = -1;
434 tusb_dma->sync_dev = -1;
435 }
436
437 channel->status = MUSB_DMA_STATUS_FREE;
438
439 return 0;
440 }
441
442 static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch *chdat)
443 {
444 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
445 int i, dmareq_nr = -1;
446
447 const int sync_dev[6] = {
448 OMAP24XX_DMA_EXT_DMAREQ0,
449 OMAP24XX_DMA_EXT_DMAREQ1,
450 OMAP242X_DMA_EXT_DMAREQ2,
451 OMAP242X_DMA_EXT_DMAREQ3,
452 OMAP242X_DMA_EXT_DMAREQ4,
453 OMAP242X_DMA_EXT_DMAREQ5,
454 };
455
456 for (i = 0; i < MAX_DMAREQ; i++) {
457 int cur = (reg & (0xf << (i * 5))) >> (i * 5);
458 if (cur == 0) {
459 dmareq_nr = i;
460 break;
461 }
462 }
463
464 if (dmareq_nr == -1)
465 return -EAGAIN;
466
467 reg |= (chdat->epnum << (dmareq_nr * 5));
468 if (chdat->tx)
469 reg |= ((1 << 4) << (dmareq_nr * 5));
470 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
471
472 chdat->dmareq = dmareq_nr;
473 chdat->sync_dev = sync_dev[chdat->dmareq];
474
475 return 0;
476 }
477
478 static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch *chdat)
479 {
480 u32 reg;
481
482 if (!chdat || chdat->dmareq < 0)
483 return;
484
485 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
486 reg &= ~(0x1f << (chdat->dmareq * 5));
487 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
488
489 chdat->dmareq = -1;
490 chdat->sync_dev = -1;
491 }
492
493 static struct dma_channel *dma_channel_pool[MAX_DMAREQ];
494
495 static struct dma_channel *
496 tusb_omap_dma_allocate(struct dma_controller *c,
497 struct musb_hw_ep *hw_ep,
498 u8 tx)
499 {
500 int ret, i;
501 const char *dev_name;
502 struct tusb_omap_dma *tusb_dma;
503 struct musb *musb;
504 void __iomem *tbase;
505 struct dma_channel *channel = NULL;
506 struct tusb_omap_dma_ch *chdat = NULL;
507 u32 reg;
508
509 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
510 musb = tusb_dma->musb;
511 tbase = musb->ctrl_base;
512
513 reg = musb_readl(tbase, TUSB_DMA_INT_MASK);
514 if (tx)
515 reg &= ~(1 << hw_ep->epnum);
516 else
517 reg &= ~(1 << (hw_ep->epnum + 15));
518 musb_writel(tbase, TUSB_DMA_INT_MASK, reg);
519
520 /* REVISIT: Why does dmareq5 not work? */
521 if (hw_ep->epnum == 0) {
522 DBG(3, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx");
523 return NULL;
524 }
525
526 for (i = 0; i < MAX_DMAREQ; i++) {
527 struct dma_channel *ch = dma_channel_pool[i];
528 if (ch->status == MUSB_DMA_STATUS_UNKNOWN) {
529 ch->status = MUSB_DMA_STATUS_FREE;
530 channel = ch;
531 chdat = ch->private_data;
532 break;
533 }
534 }
535
536 if (!channel)
537 return NULL;
538
539 if (tx) {
540 chdat->tx = 1;
541 dev_name = "TUSB transmit";
542 } else {
543 chdat->tx = 0;
544 dev_name = "TUSB receive";
545 }
546
547 chdat->musb = tusb_dma->musb;
548 chdat->tbase = tusb_dma->tbase;
549 chdat->hw_ep = hw_ep;
550 chdat->epnum = hw_ep->epnum;
551 chdat->dmareq = -1;
552 chdat->completed_len = 0;
553 chdat->tusb_dma = tusb_dma;
554
555 channel->max_len = 0x7fffffff;
556 channel->desired_mode = 0;
557 channel->actual_len = 0;
558
559 if (tusb_dma->multichannel) {
560 ret = tusb_omap_dma_allocate_dmareq(chdat);
561 if (ret != 0)
562 goto free_dmareq;
563
564 ret = omap_request_dma(chdat->sync_dev, dev_name,
565 tusb_omap_dma_cb, channel, &chdat->ch);
566 if (ret != 0)
567 goto free_dmareq;
568 } else if (tusb_dma->ch == -1) {
569 tusb_dma->dmareq = 0;
570 tusb_dma->sync_dev = OMAP24XX_DMA_EXT_DMAREQ0;
571
572 /* Callback data gets set later in the shared dmareq case */
573 ret = omap_request_dma(tusb_dma->sync_dev, "TUSB shared",
574 tusb_omap_dma_cb, NULL, &tusb_dma->ch);
575 if (ret != 0)
576 goto free_dmareq;
577
578 chdat->dmareq = -1;
579 chdat->ch = -1;
580 }
581
582 DBG(3, "ep%i %s dma: %s dma%i dmareq%i sync%i\n",
583 chdat->epnum,
584 chdat->tx ? "tx" : "rx",
585 chdat->ch >= 0 ? "dedicated" : "shared",
586 chdat->ch >= 0 ? chdat->ch : tusb_dma->ch,
587 chdat->dmareq >= 0 ? chdat->dmareq : tusb_dma->dmareq,
588 chdat->sync_dev >= 0 ? chdat->sync_dev : tusb_dma->sync_dev);
589
590 return channel;
591
592 free_dmareq:
593 tusb_omap_dma_free_dmareq(chdat);
594
595 DBG(3, "ep%i: Could not get a DMA channel\n", chdat->epnum);
596 channel->status = MUSB_DMA_STATUS_UNKNOWN;
597
598 return NULL;
599 }
600
601 static void tusb_omap_dma_release(struct dma_channel *channel)
602 {
603 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
604 struct musb *musb = chdat->musb;
605 void __iomem *tbase = musb->ctrl_base;
606 u32 reg;
607
608 DBG(3, "ep%i ch%i\n", chdat->epnum, chdat->ch);
609
610 reg = musb_readl(tbase, TUSB_DMA_INT_MASK);
611 if (chdat->tx)
612 reg |= (1 << chdat->epnum);
613 else
614 reg |= (1 << (chdat->epnum + 15));
615 musb_writel(tbase, TUSB_DMA_INT_MASK, reg);
616
617 reg = musb_readl(tbase, TUSB_DMA_INT_CLEAR);
618 if (chdat->tx)
619 reg |= (1 << chdat->epnum);
620 else
621 reg |= (1 << (chdat->epnum + 15));
622 musb_writel(tbase, TUSB_DMA_INT_CLEAR, reg);
623
624 channel->status = MUSB_DMA_STATUS_UNKNOWN;
625
626 if (chdat->ch >= 0) {
627 omap_stop_dma(chdat->ch);
628 omap_free_dma(chdat->ch);
629 chdat->ch = -1;
630 }
631
632 if (chdat->dmareq >= 0)
633 tusb_omap_dma_free_dmareq(chdat);
634
635 channel = NULL;
636 }
637
638 void dma_controller_destroy(struct dma_controller *c)
639 {
640 struct tusb_omap_dma *tusb_dma;
641 int i;
642
643 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
644 for (i = 0; i < MAX_DMAREQ; i++) {
645 struct dma_channel *ch = dma_channel_pool[i];
646 if (ch) {
647 kfree(ch->private_data);
648 kfree(ch);
649 }
650 }
651
652 if (tusb_dma && !tusb_dma->multichannel && tusb_dma->ch >= 0)
653 omap_free_dma(tusb_dma->ch);
654
655 kfree(tusb_dma);
656 }
657
658 struct dma_controller *__init
659 dma_controller_create(struct musb *musb, void __iomem *base)
660 {
661 void __iomem *tbase = musb->ctrl_base;
662 struct tusb_omap_dma *tusb_dma;
663 int i;
664
665 /* REVISIT: Get dmareq lines used from board-*.c */
666
667 musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff);
668 musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0);
669
670 musb_writel(tbase, TUSB_DMA_REQ_CONF,
671 TUSB_DMA_REQ_CONF_BURST_SIZE(2)
672 | TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f)
673 | TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
674
675 tusb_dma = kzalloc(sizeof(struct tusb_omap_dma), GFP_KERNEL);
676 if (!tusb_dma)
677 goto cleanup;
678
679 tusb_dma->musb = musb;
680 tusb_dma->tbase = musb->ctrl_base;
681
682 tusb_dma->ch = -1;
683 tusb_dma->dmareq = -1;
684 tusb_dma->sync_dev = -1;
685
686 tusb_dma->controller.start = tusb_omap_dma_start;
687 tusb_dma->controller.stop = tusb_omap_dma_stop;
688 tusb_dma->controller.channel_alloc = tusb_omap_dma_allocate;
689 tusb_dma->controller.channel_release = tusb_omap_dma_release;
690 tusb_dma->controller.channel_program = tusb_omap_dma_program;
691 tusb_dma->controller.channel_abort = tusb_omap_dma_abort;
692
693 if (tusb_get_revision(musb) >= TUSB_REV_30)
694 tusb_dma->multichannel = 1;
695
696 for (i = 0; i < MAX_DMAREQ; i++) {
697 struct dma_channel *ch;
698 struct tusb_omap_dma_ch *chdat;
699
700 ch = kzalloc(sizeof(struct dma_channel), GFP_KERNEL);
701 if (!ch)
702 goto cleanup;
703
704 dma_channel_pool[i] = ch;
705
706 chdat = kzalloc(sizeof(struct tusb_omap_dma_ch), GFP_KERNEL);
707 if (!chdat)
708 goto cleanup;
709
710 ch->status = MUSB_DMA_STATUS_UNKNOWN;
711 ch->private_data = chdat;
712 }
713
714 return &tusb_dma->controller;
715
716 cleanup:
717 dma_controller_destroy(&tusb_dma->controller);
718
719 return NULL;
720 }
Linux with added FPC-III support