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ptp: fix missing break in switch
[linux/fpc-iii.git] / drivers / scsi / advansys.c
blob620b04b7c13d94ad77591294463766c473c396ff
1 #define DRV_NAME "advansys"
2 #define ASC_VERSION "3.4" /* AdvanSys Driver Version */
3
4 /*
5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
6 *
7 * Copyright (c) 1995-2000 Advanced System Products, Inc.
8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
10 * All Rights Reserved.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18 /*
19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
20 * changed its name to ConnectCom Solutions, Inc.
21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
22 */
23
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/ioport.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/slab.h>
32 #include <linux/mm.h>
33 #include <linux/proc_fs.h>
34 #include <linux/init.h>
35 #include <linux/blkdev.h>
36 #include <linux/isa.h>
37 #include <linux/eisa.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/firmware.h>
42
43 #include <asm/io.h>
44 #include <asm/dma.h>
45
46 #include <scsi/scsi_cmnd.h>
47 #include <scsi/scsi_device.h>
48 #include <scsi/scsi_tcq.h>
49 #include <scsi/scsi.h>
50 #include <scsi/scsi_host.h>
51
52 /* Fixed in linux-4.2, not backported to 3.18:
53 *
54 * 1. Although all of the necessary command mapping places have the
55 * appropriate dma_map.. APIs, the driver still processes its internal
56 * queue using bus_to_virt() and virt_to_bus() which are illegal under
57 * the API. The entire queue processing structure will need to be
58 * altered to fix this.
59 * 2. Need to add memory mapping workaround. Test the memory mapping.
60 * If it doesn't work revert to I/O port access. Can a test be done
61 * safely?
62 * 3. Handle an interrupt not working. Keep an interrupt counter in
63 * the interrupt handler. In the timeout function if the interrupt
64 * has not occurred then print a message and run in polled mode.
65 * 4. Need to add support for target mode commands, cf. CAM XPT.
66 * 5. check DMA mapping functions for failure
67 * 6. Use scsi_transport_spi
68 * 7. advansys_info is not safe against multiple simultaneous callers
69 * 8. Add module_param to override ISA/VLB ioport array
70 */
71
72 /* Enable driver /proc statistics. */
73 #define ADVANSYS_STATS
74
75 /* Enable driver tracing. */
76 #undef ADVANSYS_DEBUG
77
78 /*
79 * Portable Data Types
80 *
81 * Any instance where a 32-bit long or pointer type is assumed
82 * for precision or HW defined structures, the following define
83 * types must be used. In Linux the char, short, and int types
84 * are all consistent at 8, 16, and 32 bits respectively. Pointers
85 * and long types are 64 bits on Alpha and UltraSPARC.
86 */
87 #define ASC_PADDR __u32 /* Physical/Bus address data type. */
88 #define ASC_VADDR __u32 /* Virtual address data type. */
89 #define ASC_DCNT __u32 /* Unsigned Data count type. */
90 #define ASC_SDCNT __s32 /* Signed Data count type. */
91
92 typedef unsigned char uchar;
93
94 #ifndef TRUE
95 #define TRUE (1)
96 #endif
97 #ifndef FALSE
98 #define FALSE (0)
99 #endif
100
101 #define ERR (-1)
102 #define UW_ERR (uint)(0xFFFF)
103 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
104
105 #define PCI_VENDOR_ID_ASP 0x10cd
106 #define PCI_DEVICE_ID_ASP_1200A 0x1100
107 #define PCI_DEVICE_ID_ASP_ABP940 0x1200
108 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300
109 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
110 #define PCI_DEVICE_ID_38C0800_REV1 0x2500
111 #define PCI_DEVICE_ID_38C1600_REV1 0x2700
112
113 /*
114 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
115 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
116 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
117 * SRB structure.
118 */
119 #define CC_VERY_LONG_SG_LIST 0
120 #define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
121
122 #define PortAddr unsigned int /* port address size */
123 #define inp(port) inb(port)
124 #define outp(port, byte) outb((byte), (port))
125
126 #define inpw(port) inw(port)
127 #define outpw(port, word) outw((word), (port))
128
129 #define ASC_MAX_SG_QUEUE 7
130 #define ASC_MAX_SG_LIST 255
131
132 #define ASC_CS_TYPE unsigned short
133
134 #define ASC_IS_ISA (0x0001)
135 #define ASC_IS_ISAPNP (0x0081)
136 #define ASC_IS_EISA (0x0002)
137 #define ASC_IS_PCI (0x0004)
138 #define ASC_IS_PCI_ULTRA (0x0104)
139 #define ASC_IS_PCMCIA (0x0008)
140 #define ASC_IS_MCA (0x0020)
141 #define ASC_IS_VL (0x0040)
142 #define ASC_IS_WIDESCSI_16 (0x0100)
143 #define ASC_IS_WIDESCSI_32 (0x0200)
144 #define ASC_IS_BIG_ENDIAN (0x8000)
145
146 #define ASC_CHIP_MIN_VER_VL (0x01)
147 #define ASC_CHIP_MAX_VER_VL (0x07)
148 #define ASC_CHIP_MIN_VER_PCI (0x09)
149 #define ASC_CHIP_MAX_VER_PCI (0x0F)
150 #define ASC_CHIP_VER_PCI_BIT (0x08)
151 #define ASC_CHIP_MIN_VER_ISA (0x11)
152 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
153 #define ASC_CHIP_MAX_VER_ISA (0x27)
154 #define ASC_CHIP_VER_ISA_BIT (0x30)
155 #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
156 #define ASC_CHIP_VER_ASYN_BUG (0x21)
157 #define ASC_CHIP_VER_PCI 0x08
158 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
159 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
160 #define ASC_CHIP_MIN_VER_EISA (0x41)
161 #define ASC_CHIP_MAX_VER_EISA (0x47)
162 #define ASC_CHIP_VER_EISA_BIT (0x40)
163 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
164 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
165 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
166 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
167
168 #define ASC_SCSI_ID_BITS 3
169 #define ASC_SCSI_TIX_TYPE uchar
170 #define ASC_ALL_DEVICE_BIT_SET 0xFF
171 #define ASC_SCSI_BIT_ID_TYPE uchar
172 #define ASC_MAX_TID 7
173 #define ASC_MAX_LUN 7
174 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
175 #define ASC_MAX_SENSE_LEN 32
176 #define ASC_MIN_SENSE_LEN 14
177 #define ASC_SCSI_RESET_HOLD_TIME_US 60
178
179 /*
180 * Narrow boards only support 12-byte commands, while wide boards
181 * extend to 16-byte commands.
182 */
183 #define ASC_MAX_CDB_LEN 12
184 #define ADV_MAX_CDB_LEN 16
185
186 #define MS_SDTR_LEN 0x03
187 #define MS_WDTR_LEN 0x02
188
189 #define ASC_SG_LIST_PER_Q 7
190 #define QS_FREE 0x00
191 #define QS_READY 0x01
192 #define QS_DISC1 0x02
193 #define QS_DISC2 0x04
194 #define QS_BUSY 0x08
195 #define QS_ABORTED 0x40
196 #define QS_DONE 0x80
197 #define QC_NO_CALLBACK 0x01
198 #define QC_SG_SWAP_QUEUE 0x02
199 #define QC_SG_HEAD 0x04
200 #define QC_DATA_IN 0x08
201 #define QC_DATA_OUT 0x10
202 #define QC_URGENT 0x20
203 #define QC_MSG_OUT 0x40
204 #define QC_REQ_SENSE 0x80
205 #define QCSG_SG_XFER_LIST 0x02
206 #define QCSG_SG_XFER_MORE 0x04
207 #define QCSG_SG_XFER_END 0x08
208 #define QD_IN_PROGRESS 0x00
209 #define QD_NO_ERROR 0x01
210 #define QD_ABORTED_BY_HOST 0x02
211 #define QD_WITH_ERROR 0x04
212 #define QD_INVALID_REQUEST 0x80
213 #define QD_INVALID_HOST_NUM 0x81
214 #define QD_INVALID_DEVICE 0x82
215 #define QD_ERR_INTERNAL 0xFF
216 #define QHSTA_NO_ERROR 0x00
217 #define QHSTA_M_SEL_TIMEOUT 0x11
218 #define QHSTA_M_DATA_OVER_RUN 0x12
219 #define QHSTA_M_DATA_UNDER_RUN 0x12
220 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
221 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
222 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
223 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
224 #define QHSTA_D_HOST_ABORT_FAILED 0x23
225 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
226 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
227 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
228 #define QHSTA_M_WTM_TIMEOUT 0x41
229 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
230 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
231 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
232 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
233 #define QHSTA_M_BAD_TAG_CODE 0x46
234 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
235 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
236 #define QHSTA_D_LRAM_CMP_ERROR 0x81
237 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
238 #define ASC_FLAG_SCSIQ_REQ 0x01
239 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
240 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
241 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
242 #define ASC_FLAG_WIN16 0x10
243 #define ASC_FLAG_WIN32 0x20
244 #define ASC_FLAG_ISA_OVER_16MB 0x40
245 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
246 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
247 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
248 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
249 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
250 #define ASC_SCSIQ_CPY_BEG 4
251 #define ASC_SCSIQ_SGHD_CPY_BEG 2
252 #define ASC_SCSIQ_B_FWD 0
253 #define ASC_SCSIQ_B_BWD 1
254 #define ASC_SCSIQ_B_STATUS 2
255 #define ASC_SCSIQ_B_QNO 3
256 #define ASC_SCSIQ_B_CNTL 4
257 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
258 #define ASC_SCSIQ_D_DATA_ADDR 8
259 #define ASC_SCSIQ_D_DATA_CNT 12
260 #define ASC_SCSIQ_B_SENSE_LEN 20
261 #define ASC_SCSIQ_DONE_INFO_BEG 22
262 #define ASC_SCSIQ_D_SRBPTR 22
263 #define ASC_SCSIQ_B_TARGET_IX 26
264 #define ASC_SCSIQ_B_CDB_LEN 28
265 #define ASC_SCSIQ_B_TAG_CODE 29
266 #define ASC_SCSIQ_W_VM_ID 30
267 #define ASC_SCSIQ_DONE_STATUS 32
268 #define ASC_SCSIQ_HOST_STATUS 33
269 #define ASC_SCSIQ_SCSI_STATUS 34
270 #define ASC_SCSIQ_CDB_BEG 36
271 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
272 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
273 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
274 #define ASC_SCSIQ_B_SG_WK_QP 49
275 #define ASC_SCSIQ_B_SG_WK_IX 50
276 #define ASC_SCSIQ_W_ALT_DC1 52
277 #define ASC_SCSIQ_B_LIST_CNT 6
278 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
279 #define ASC_SGQ_B_SG_CNTL 4
280 #define ASC_SGQ_B_SG_HEAD_QP 5
281 #define ASC_SGQ_B_SG_LIST_CNT 6
282 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
283 #define ASC_SGQ_LIST_BEG 8
284 #define ASC_DEF_SCSI1_QNG 4
285 #define ASC_MAX_SCSI1_QNG 4
286 #define ASC_DEF_SCSI2_QNG 16
287 #define ASC_MAX_SCSI2_QNG 32
288 #define ASC_TAG_CODE_MASK 0x23
289 #define ASC_STOP_REQ_RISC_STOP 0x01
290 #define ASC_STOP_ACK_RISC_STOP 0x03
291 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
292 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
293 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
294 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
295 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
296 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
297 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
298 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
299 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
300 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
301
302 typedef struct asc_scsiq_1 {
303 uchar status;
304 uchar q_no;
305 uchar cntl;
306 uchar sg_queue_cnt;
307 uchar target_id;
308 uchar target_lun;
309 ASC_PADDR data_addr;
310 ASC_DCNT data_cnt;
311 ASC_PADDR sense_addr;
312 uchar sense_len;
313 uchar extra_bytes;
314 } ASC_SCSIQ_1;
315
316 typedef struct asc_scsiq_2 {
317 ASC_VADDR srb_ptr;
318 uchar target_ix;
319 uchar flag;
320 uchar cdb_len;
321 uchar tag_code;
322 ushort vm_id;
323 } ASC_SCSIQ_2;
324
325 typedef struct asc_scsiq_3 {
326 uchar done_stat;
327 uchar host_stat;
328 uchar scsi_stat;
329 uchar scsi_msg;
330 } ASC_SCSIQ_3;
331
332 typedef struct asc_scsiq_4 {
333 uchar cdb[ASC_MAX_CDB_LEN];
334 uchar y_first_sg_list_qp;
335 uchar y_working_sg_qp;
336 uchar y_working_sg_ix;
337 uchar y_res;
338 ushort x_req_count;
339 ushort x_reconnect_rtn;
340 ASC_PADDR x_saved_data_addr;
341 ASC_DCNT x_saved_data_cnt;
342 } ASC_SCSIQ_4;
343
344 typedef struct asc_q_done_info {
345 ASC_SCSIQ_2 d2;
346 ASC_SCSIQ_3 d3;
347 uchar q_status;
348 uchar q_no;
349 uchar cntl;
350 uchar sense_len;
351 uchar extra_bytes;
352 uchar res;
353 ASC_DCNT remain_bytes;
354 } ASC_QDONE_INFO;
355
356 typedef struct asc_sg_list {
357 ASC_PADDR addr;
358 ASC_DCNT bytes;
359 } ASC_SG_LIST;
360
361 typedef struct asc_sg_head {
362 ushort entry_cnt;
363 ushort queue_cnt;
364 ushort entry_to_copy;
365 ushort res;
366 ASC_SG_LIST sg_list[0];
367 } ASC_SG_HEAD;
368
369 typedef struct asc_scsi_q {
370 ASC_SCSIQ_1 q1;
371 ASC_SCSIQ_2 q2;
372 uchar *cdbptr;
373 ASC_SG_HEAD *sg_head;
374 ushort remain_sg_entry_cnt;
375 ushort next_sg_index;
376 } ASC_SCSI_Q;
377
378 typedef struct asc_scsi_req_q {
379 ASC_SCSIQ_1 r1;
380 ASC_SCSIQ_2 r2;
381 uchar *cdbptr;
382 ASC_SG_HEAD *sg_head;
383 uchar *sense_ptr;
384 ASC_SCSIQ_3 r3;
385 uchar cdb[ASC_MAX_CDB_LEN];
386 uchar sense[ASC_MIN_SENSE_LEN];
387 } ASC_SCSI_REQ_Q;
388
389 typedef struct asc_scsi_bios_req_q {
390 ASC_SCSIQ_1 r1;
391 ASC_SCSIQ_2 r2;
392 uchar *cdbptr;
393 ASC_SG_HEAD *sg_head;
394 uchar *sense_ptr;
395 ASC_SCSIQ_3 r3;
396 uchar cdb[ASC_MAX_CDB_LEN];
397 uchar sense[ASC_MIN_SENSE_LEN];
398 } ASC_SCSI_BIOS_REQ_Q;
399
400 typedef struct asc_risc_q {
401 uchar fwd;
402 uchar bwd;
403 ASC_SCSIQ_1 i1;
404 ASC_SCSIQ_2 i2;
405 ASC_SCSIQ_3 i3;
406 ASC_SCSIQ_4 i4;
407 } ASC_RISC_Q;
408
409 typedef struct asc_sg_list_q {
410 uchar seq_no;
411 uchar q_no;
412 uchar cntl;
413 uchar sg_head_qp;
414 uchar sg_list_cnt;
415 uchar sg_cur_list_cnt;
416 } ASC_SG_LIST_Q;
417
418 typedef struct asc_risc_sg_list_q {
419 uchar fwd;
420 uchar bwd;
421 ASC_SG_LIST_Q sg;
422 ASC_SG_LIST sg_list[7];
423 } ASC_RISC_SG_LIST_Q;
424
425 #define ASCQ_ERR_Q_STATUS 0x0D
426 #define ASCQ_ERR_CUR_QNG 0x17
427 #define ASCQ_ERR_SG_Q_LINKS 0x18
428 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
429 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
430 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
431
432 /*
433 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
434 */
435 #define ASC_WARN_NO_ERROR 0x0000
436 #define ASC_WARN_IO_PORT_ROTATE 0x0001
437 #define ASC_WARN_EEPROM_CHKSUM 0x0002
438 #define ASC_WARN_IRQ_MODIFIED 0x0004
439 #define ASC_WARN_AUTO_CONFIG 0x0008
440 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
441 #define ASC_WARN_EEPROM_RECOVER 0x0020
442 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
443
444 /*
445 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'.
446 */
447 #define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
448 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
449 #define ASC_IERR_SET_PC_ADDR 0x0004
450 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
451 #define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */
452 #define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */
453 #define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */
454 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
455 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */
456 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
457 #define ASC_IERR_NO_BUS_TYPE 0x0400
458 #define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
459 #define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */
460 #define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */
461
462 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
463 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
464 #define ASC_MIN_FREE_Q (0x02)
465 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
466 #define ASC_MAX_TOTAL_QNG 240
467 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
468 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
469 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
470 #define ASC_MAX_INRAM_TAG_QNG 16
471 #define ASC_IOADR_GAP 0x10
472 #define ASC_SYN_MAX_OFFSET 0x0F
473 #define ASC_DEF_SDTR_OFFSET 0x0F
474 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
475 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
476
477 /* The narrow chip only supports a limited selection of transfer rates.
478 * These are encoded in the range 0..7 or 0..15 depending whether the chip
479 * is Ultra-capable or not. These tables let us convert from one to the other.
480 */
481 static const unsigned char asc_syn_xfer_period[8] = {
482 25, 30, 35, 40, 50, 60, 70, 85
483 };
484
485 static const unsigned char asc_syn_ultra_xfer_period[16] = {
486 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
487 };
488
489 typedef struct ext_msg {
490 uchar msg_type;
491 uchar msg_len;
492 uchar msg_req;
493 union {
494 struct {
495 uchar sdtr_xfer_period;
496 uchar sdtr_req_ack_offset;
497 } sdtr;
498 struct {
499 uchar wdtr_width;
500 } wdtr;
501 struct {
502 uchar mdp_b3;
503 uchar mdp_b2;
504 uchar mdp_b1;
505 uchar mdp_b0;
506 } mdp;
507 } u_ext_msg;
508 uchar res;
509 } EXT_MSG;
510
511 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
512 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
513 #define wdtr_width u_ext_msg.wdtr.wdtr_width
514 #define mdp_b3 u_ext_msg.mdp_b3
515 #define mdp_b2 u_ext_msg.mdp_b2
516 #define mdp_b1 u_ext_msg.mdp_b1
517 #define mdp_b0 u_ext_msg.mdp_b0
518
519 typedef struct asc_dvc_cfg {
520 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
521 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
522 ASC_SCSI_BIT_ID_TYPE disc_enable;
523 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
524 uchar chip_scsi_id;
525 uchar isa_dma_speed;
526 uchar isa_dma_channel;
527 uchar chip_version;
528 ushort mcode_date;
529 ushort mcode_version;
530 uchar max_tag_qng[ASC_MAX_TID + 1];
531 uchar sdtr_period_offset[ASC_MAX_TID + 1];
532 uchar adapter_info[6];
533 } ASC_DVC_CFG;
534
535 #define ASC_DEF_DVC_CNTL 0xFFFF
536 #define ASC_DEF_CHIP_SCSI_ID 7
537 #define ASC_DEF_ISA_DMA_SPEED 4
538 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
539 #define ASC_INIT_STATE_END_GET_CFG 0x0002
540 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
541 #define ASC_INIT_STATE_END_SET_CFG 0x0008
542 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
543 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
544 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
545 #define ASC_INIT_STATE_END_INQUIRY 0x0080
546 #define ASC_INIT_RESET_SCSI_DONE 0x0100
547 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
548 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
549 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
550 #define ASC_MIN_TAGGED_CMD 7
551 #define ASC_MAX_SCSI_RESET_WAIT 30
552 #define ASC_OVERRUN_BSIZE 64
553
554 struct asc_dvc_var; /* Forward Declaration. */
555
556 typedef struct asc_dvc_var {
557 PortAddr iop_base;
558 ushort err_code;
559 ushort dvc_cntl;
560 ushort bug_fix_cntl;
561 ushort bus_type;
562 ASC_SCSI_BIT_ID_TYPE init_sdtr;
563 ASC_SCSI_BIT_ID_TYPE sdtr_done;
564 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
565 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
566 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
567 ASC_SCSI_BIT_ID_TYPE start_motor;
568 uchar *overrun_buf;
569 dma_addr_t overrun_dma;
570 uchar scsi_reset_wait;
571 uchar chip_no;
572 char is_in_int;
573 uchar max_total_qng;
574 uchar cur_total_qng;
575 uchar in_critical_cnt;
576 uchar last_q_shortage;
577 ushort init_state;
578 uchar cur_dvc_qng[ASC_MAX_TID + 1];
579 uchar max_dvc_qng[ASC_MAX_TID + 1];
580 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
581 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
582 const uchar *sdtr_period_tbl;
583 ASC_DVC_CFG *cfg;
584 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
585 char redo_scam;
586 ushort res2;
587 uchar dos_int13_table[ASC_MAX_TID + 1];
588 ASC_DCNT max_dma_count;
589 ASC_SCSI_BIT_ID_TYPE no_scam;
590 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
591 uchar min_sdtr_index;
592 uchar max_sdtr_index;
593 struct asc_board *drv_ptr;
594 int ptr_map_count;
595 void **ptr_map;
596 ASC_DCNT uc_break;
597 } ASC_DVC_VAR;
598
599 typedef struct asc_dvc_inq_info {
600 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
601 } ASC_DVC_INQ_INFO;
602
603 typedef struct asc_cap_info {
604 ASC_DCNT lba;
605 ASC_DCNT blk_size;
606 } ASC_CAP_INFO;
607
608 typedef struct asc_cap_info_array {
609 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
610 } ASC_CAP_INFO_ARRAY;
611
612 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
613 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
614 #define ASC_CNTL_INITIATOR (ushort)0x0001
615 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
616 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
617 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
618 #define ASC_CNTL_NO_SCAM (ushort)0x0010
619 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
620 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
621 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
622 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
623 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
624 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
625 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
626 #define ASC_CNTL_BURST_MODE (ushort)0x2000
627 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
628 #define ASC_EEP_DVC_CFG_BEG_VL 2
629 #define ASC_EEP_MAX_DVC_ADDR_VL 15
630 #define ASC_EEP_DVC_CFG_BEG 32
631 #define ASC_EEP_MAX_DVC_ADDR 45
632 #define ASC_EEP_MAX_RETRY 20
633
634 /*
635 * These macros keep the chip SCSI id and ISA DMA speed
636 * bitfields in board order. C bitfields aren't portable
637 * between big and little-endian platforms so they are
638 * not used.
639 */
640
641 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
642 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
643 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
644 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
645 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
646 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
647
648 typedef struct asceep_config {
649 ushort cfg_lsw;
650 ushort cfg_msw;
651 uchar init_sdtr;
652 uchar disc_enable;
653 uchar use_cmd_qng;
654 uchar start_motor;
655 uchar max_total_qng;
656 uchar max_tag_qng;
657 uchar bios_scan;
658 uchar power_up_wait;
659 uchar no_scam;
660 uchar id_speed; /* low order 4 bits is chip scsi id */
661 /* high order 4 bits is isa dma speed */
662 uchar dos_int13_table[ASC_MAX_TID + 1];
663 uchar adapter_info[6];
664 ushort cntl;
665 ushort chksum;
666 } ASCEEP_CONFIG;
667
668 #define ASC_EEP_CMD_READ 0x80
669 #define ASC_EEP_CMD_WRITE 0x40
670 #define ASC_EEP_CMD_WRITE_ABLE 0x30
671 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
672 #define ASCV_MSGOUT_BEG 0x0000
673 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
674 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
675 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
676 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
677 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
678 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
679 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
680 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
681 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
682 #define ASCV_BREAK_ADDR (ushort)0x0028
683 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
684 #define ASCV_BREAK_CONTROL (ushort)0x002C
685 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
686
687 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
688 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
689 #define ASCV_MCODE_SIZE_W (ushort)0x0034
690 #define ASCV_STOP_CODE_B (ushort)0x0036
691 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
692 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
693 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
694 #define ASCV_HALTCODE_W (ushort)0x0040
695 #define ASCV_CHKSUM_W (ushort)0x0042
696 #define ASCV_MC_DATE_W (ushort)0x0044
697 #define ASCV_MC_VER_W (ushort)0x0046
698 #define ASCV_NEXTRDY_B (ushort)0x0048
699 #define ASCV_DONENEXT_B (ushort)0x0049
700 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
701 #define ASCV_SCSIBUSY_B (ushort)0x004B
702 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
703 #define ASCV_CURCDB_B (ushort)0x004D
704 #define ASCV_RCLUN_B (ushort)0x004E
705 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
706 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
707 #define ASCV_DISC_ENABLE_B (ushort)0x0052
708 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
709 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
710 #define ASCV_MCODE_CNTL_B (ushort)0x0056
711 #define ASCV_NULL_TARGET_B (ushort)0x0057
712 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
713 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
714 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
715 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
716 #define ASCV_HOST_FLAG_B (ushort)0x005D
717 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
718 #define ASCV_VER_SERIAL_B (ushort)0x0065
719 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
720 #define ASCV_WTM_FLAG_B (ushort)0x0068
721 #define ASCV_RISC_FLAG_B (ushort)0x006A
722 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
723 #define ASC_HOST_FLAG_IN_ISR 0x01
724 #define ASC_HOST_FLAG_ACK_INT 0x02
725 #define ASC_RISC_FLAG_GEN_INT 0x01
726 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
727 #define IOP_CTRL (0x0F)
728 #define IOP_STATUS (0x0E)
729 #define IOP_INT_ACK IOP_STATUS
730 #define IOP_REG_IFC (0x0D)
731 #define IOP_SYN_OFFSET (0x0B)
732 #define IOP_EXTRA_CONTROL (0x0D)
733 #define IOP_REG_PC (0x0C)
734 #define IOP_RAM_ADDR (0x0A)
735 #define IOP_RAM_DATA (0x08)
736 #define IOP_EEP_DATA (0x06)
737 #define IOP_EEP_CMD (0x07)
738 #define IOP_VERSION (0x03)
739 #define IOP_CONFIG_HIGH (0x04)
740 #define IOP_CONFIG_LOW (0x02)
741 #define IOP_SIG_BYTE (0x01)
742 #define IOP_SIG_WORD (0x00)
743 #define IOP_REG_DC1 (0x0E)
744 #define IOP_REG_DC0 (0x0C)
745 #define IOP_REG_SB (0x0B)
746 #define IOP_REG_DA1 (0x0A)
747 #define IOP_REG_DA0 (0x08)
748 #define IOP_REG_SC (0x09)
749 #define IOP_DMA_SPEED (0x07)
750 #define IOP_REG_FLAG (0x07)
751 #define IOP_FIFO_H (0x06)
752 #define IOP_FIFO_L (0x04)
753 #define IOP_REG_ID (0x05)
754 #define IOP_REG_QP (0x03)
755 #define IOP_REG_IH (0x02)
756 #define IOP_REG_IX (0x01)
757 #define IOP_REG_AX (0x00)
758 #define IFC_REG_LOCK (0x00)
759 #define IFC_REG_UNLOCK (0x09)
760 #define IFC_WR_EN_FILTER (0x10)
761 #define IFC_RD_NO_EEPROM (0x10)
762 #define IFC_SLEW_RATE (0x20)
763 #define IFC_ACT_NEG (0x40)
764 #define IFC_INP_FILTER (0x80)
765 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
766 #define SC_SEL (uchar)(0x80)
767 #define SC_BSY (uchar)(0x40)
768 #define SC_ACK (uchar)(0x20)
769 #define SC_REQ (uchar)(0x10)
770 #define SC_ATN (uchar)(0x08)
771 #define SC_IO (uchar)(0x04)
772 #define SC_CD (uchar)(0x02)
773 #define SC_MSG (uchar)(0x01)
774 #define SEC_SCSI_CTL (uchar)(0x80)
775 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
776 #define SEC_SLEW_RATE (uchar)(0x20)
777 #define SEC_ENABLE_FILTER (uchar)(0x10)
778 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
779 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
780 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
781 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
782 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
783 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
784 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
785 #define ASC_MAX_QNO 0xF8
786 #define ASC_DATA_SEC_BEG (ushort)0x0080
787 #define ASC_DATA_SEC_END (ushort)0x0080
788 #define ASC_CODE_SEC_BEG (ushort)0x0080
789 #define ASC_CODE_SEC_END (ushort)0x0080
790 #define ASC_QADR_BEG (0x4000)
791 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
792 #define ASC_QADR_END (ushort)0x7FFF
793 #define ASC_QLAST_ADR (ushort)0x7FC0
794 #define ASC_QBLK_SIZE 0x40
795 #define ASC_BIOS_DATA_QBEG 0xF8
796 #define ASC_MIN_ACTIVE_QNO 0x01
797 #define ASC_QLINK_END 0xFF
798 #define ASC_EEPROM_WORDS 0x10
799 #define ASC_MAX_MGS_LEN 0x10
800 #define ASC_BIOS_ADDR_DEF 0xDC00
801 #define ASC_BIOS_SIZE 0x3800
802 #define ASC_BIOS_RAM_OFF 0x3800
803 #define ASC_BIOS_RAM_SIZE 0x800
804 #define ASC_BIOS_MIN_ADDR 0xC000
805 #define ASC_BIOS_MAX_ADDR 0xEC00
806 #define ASC_BIOS_BANK_SIZE 0x0400
807 #define ASC_MCODE_START_ADDR 0x0080
808 #define ASC_CFG0_HOST_INT_ON 0x0020
809 #define ASC_CFG0_BIOS_ON 0x0040
810 #define ASC_CFG0_VERA_BURST_ON 0x0080
811 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
812 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
813 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
814 #define ASC_CFG_MSW_CLR_MASK 0x3080
815 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
816 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
817 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
818 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
819 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
820 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
821 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
822 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
823 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
824 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
825 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
826 #define CSW_HALTED (ASC_CS_TYPE)0x0010
827 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
828 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
829 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
830 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
831 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
832 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
833 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
834 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
835 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
836 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
837 #define CC_CHIP_RESET (uchar)0x80
838 #define CC_SCSI_RESET (uchar)0x40
839 #define CC_HALT (uchar)0x20
840 #define CC_SINGLE_STEP (uchar)0x10
841 #define CC_DMA_ABLE (uchar)0x08
842 #define CC_TEST (uchar)0x04
843 #define CC_BANK_ONE (uchar)0x02
844 #define CC_DIAG (uchar)0x01
845 #define ASC_1000_ID0W 0x04C1
846 #define ASC_1000_ID0W_FIX 0x00C1
847 #define ASC_1000_ID1B 0x25
848 #define ASC_EISA_REV_IOP_MASK (0x0C83)
849 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
850 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
851 #define INS_HALTINT (ushort)0x6281
852 #define INS_HALT (ushort)0x6280
853 #define INS_SINT (ushort)0x6200
854 #define INS_RFLAG_WTM (ushort)0x7380
855 #define ASC_MC_SAVE_CODE_WSIZE 0x500
856 #define ASC_MC_SAVE_DATA_WSIZE 0x40
857
858 typedef struct asc_mc_saved {
859 ushort data[ASC_MC_SAVE_DATA_WSIZE];
860 ushort code[ASC_MC_SAVE_CODE_WSIZE];
861 } ASC_MC_SAVED;
862
863 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
864 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
865 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
866 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
867 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
868 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
869 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
870 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
871 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
872 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
873 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
874 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
875 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
876 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
877 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
878 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
879 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
880 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
881 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
882 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
883 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
884 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
885 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
886 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
887 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
888 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
889 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
890 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
891 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
892 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
893 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
894 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
895 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
896 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
897 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
898 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
899 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
900 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
901 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
902 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
903 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
904 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
905 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
906 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
907 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
908 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
909 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
910 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
911 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
912 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
913 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
914 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
915 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
916 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
917 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
918 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
919 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
920 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
921 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
922 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
923 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
924 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
925 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
926 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
927 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
928 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
929 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
930
931 /*
932 * Portable Data Types
933 *
934 * Any instance where a 32-bit long or pointer type is assumed
935 * for precision or HW defined structures, the following define
936 * types must be used. In Linux the char, short, and int types
937 * are all consistent at 8, 16, and 32 bits respectively. Pointers
938 * and long types are 64 bits on Alpha and UltraSPARC.
939 */
940 #define ADV_PADDR __u32 /* Physical address data type. */
941 #define ADV_VADDR __u32 /* Virtual address data type. */
942 #define ADV_DCNT __u32 /* Unsigned Data count type. */
943 #define ADV_SDCNT __s32 /* Signed Data count type. */
944
945 /*
946 * These macros are used to convert a virtual address to a
947 * 32-bit value. This currently can be used on Linux Alpha
948 * which uses 64-bit virtual address but a 32-bit bus address.
949 * This is likely to break in the future, but doing this now
950 * will give us time to change the HW and FW to handle 64-bit
951 * addresses.
952 */
953 #define ADV_VADDR_TO_U32 virt_to_bus
954 #define ADV_U32_TO_VADDR bus_to_virt
955
956 #define AdvPortAddr void __iomem * /* Virtual memory address size */
957
958 /*
959 * Define Adv Library required memory access macros.
960 */
961 #define ADV_MEM_READB(addr) readb(addr)
962 #define ADV_MEM_READW(addr) readw(addr)
963 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
964 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
965 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
966
967 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
968
969 /*
970 * Define total number of simultaneous maximum element scatter-gather
971 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
972 * maximum number of outstanding commands per wide host adapter. Each
973 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
974 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
975 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
976 * structures or 255 scatter-gather elements.
977 */
978 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
979
980 /*
981 * Define maximum number of scatter-gather elements per request.
982 */
983 #define ADV_MAX_SG_LIST 255
984 #define NO_OF_SG_PER_BLOCK 15
985
986 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
987 #define ADV_EEP_DVC_CFG_END (0x15)
988 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
989 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
990
991 #define ADV_EEP_DELAY_MS 100
992
993 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
994 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
995 /*
996 * For the ASC3550 Bit 13 is Termination Polarity control bit.
997 * For later ICs Bit 13 controls whether the CIS (Card Information
998 * Service Section) is loaded from EEPROM.
999 */
1000 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
1001 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
1002 /*
1003 * ASC38C1600 Bit 11
1004 *
1005 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
1006 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
1007 * Function 0 will specify INT B.
1008 *
1009 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
1010 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
1011 * Function 1 will specify INT A.
1012 */
1013 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
1014
1015 typedef struct adveep_3550_config {
1016 /* Word Offset, Description */
1017
1018 ushort cfg_lsw; /* 00 power up initialization */
1019 /* bit 13 set - Term Polarity Control */
1020 /* bit 14 set - BIOS Enable */
1021 /* bit 15 set - Big Endian Mode */
1022 ushort cfg_msw; /* 01 unused */
1023 ushort disc_enable; /* 02 disconnect enable */
1024 ushort wdtr_able; /* 03 Wide DTR able */
1025 ushort sdtr_able; /* 04 Synchronous DTR able */
1026 ushort start_motor; /* 05 send start up motor */
1027 ushort tagqng_able; /* 06 tag queuing able */
1028 ushort bios_scan; /* 07 BIOS device control */
1029 ushort scam_tolerant; /* 08 no scam */
1030
1031 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1032 uchar bios_boot_delay; /* power up wait */
1033
1034 uchar scsi_reset_delay; /* 10 reset delay */
1035 uchar bios_id_lun; /* first boot device scsi id & lun */
1036 /* high nibble is lun */
1037 /* low nibble is scsi id */
1038
1039 uchar termination; /* 11 0 - automatic */
1040 /* 1 - low off / high off */
1041 /* 2 - low off / high on */
1042 /* 3 - low on / high on */
1043 /* There is no low on / high off */
1044
1045 uchar reserved1; /* reserved byte (not used) */
1046
1047 ushort bios_ctrl; /* 12 BIOS control bits */
1048 /* bit 0 BIOS don't act as initiator. */
1049 /* bit 1 BIOS > 1 GB support */
1050 /* bit 2 BIOS > 2 Disk Support */
1051 /* bit 3 BIOS don't support removables */
1052 /* bit 4 BIOS support bootable CD */
1053 /* bit 5 BIOS scan enabled */
1054 /* bit 6 BIOS support multiple LUNs */
1055 /* bit 7 BIOS display of message */
1056 /* bit 8 SCAM disabled */
1057 /* bit 9 Reset SCSI bus during init. */
1058 /* bit 10 */
1059 /* bit 11 No verbose initialization. */
1060 /* bit 12 SCSI parity enabled */
1061 /* bit 13 */
1062 /* bit 14 */
1063 /* bit 15 */
1064 ushort ultra_able; /* 13 ULTRA speed able */
1065 ushort reserved2; /* 14 reserved */
1066 uchar max_host_qng; /* 15 maximum host queuing */
1067 uchar max_dvc_qng; /* maximum per device queuing */
1068 ushort dvc_cntl; /* 16 control bit for driver */
1069 ushort bug_fix; /* 17 control bit for bug fix */
1070 ushort serial_number_word1; /* 18 Board serial number word 1 */
1071 ushort serial_number_word2; /* 19 Board serial number word 2 */
1072 ushort serial_number_word3; /* 20 Board serial number word 3 */
1073 ushort check_sum; /* 21 EEP check sum */
1074 uchar oem_name[16]; /* 22 OEM name */
1075 ushort dvc_err_code; /* 30 last device driver error code */
1076 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1077 ushort adv_err_addr; /* 32 last uc error address */
1078 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1079 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1080 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1081 ushort num_of_err; /* 36 number of error */
1082 } ADVEEP_3550_CONFIG;
1083
1084 typedef struct adveep_38C0800_config {
1085 /* Word Offset, Description */
1086
1087 ushort cfg_lsw; /* 00 power up initialization */
1088 /* bit 13 set - Load CIS */
1089 /* bit 14 set - BIOS Enable */
1090 /* bit 15 set - Big Endian Mode */
1091 ushort cfg_msw; /* 01 unused */
1092 ushort disc_enable; /* 02 disconnect enable */
1093 ushort wdtr_able; /* 03 Wide DTR able */
1094 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1095 ushort start_motor; /* 05 send start up motor */
1096 ushort tagqng_able; /* 06 tag queuing able */
1097 ushort bios_scan; /* 07 BIOS device control */
1098 ushort scam_tolerant; /* 08 no scam */
1099
1100 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1101 uchar bios_boot_delay; /* power up wait */
1102
1103 uchar scsi_reset_delay; /* 10 reset delay */
1104 uchar bios_id_lun; /* first boot device scsi id & lun */
1105 /* high nibble is lun */
1106 /* low nibble is scsi id */
1107
1108 uchar termination_se; /* 11 0 - automatic */
1109 /* 1 - low off / high off */
1110 /* 2 - low off / high on */
1111 /* 3 - low on / high on */
1112 /* There is no low on / high off */
1113
1114 uchar termination_lvd; /* 11 0 - automatic */
1115 /* 1 - low off / high off */
1116 /* 2 - low off / high on */
1117 /* 3 - low on / high on */
1118 /* There is no low on / high off */
1119
1120 ushort bios_ctrl; /* 12 BIOS control bits */
1121 /* bit 0 BIOS don't act as initiator. */
1122 /* bit 1 BIOS > 1 GB support */
1123 /* bit 2 BIOS > 2 Disk Support */
1124 /* bit 3 BIOS don't support removables */
1125 /* bit 4 BIOS support bootable CD */
1126 /* bit 5 BIOS scan enabled */
1127 /* bit 6 BIOS support multiple LUNs */
1128 /* bit 7 BIOS display of message */
1129 /* bit 8 SCAM disabled */
1130 /* bit 9 Reset SCSI bus during init. */
1131 /* bit 10 */
1132 /* bit 11 No verbose initialization. */
1133 /* bit 12 SCSI parity enabled */
1134 /* bit 13 */
1135 /* bit 14 */
1136 /* bit 15 */
1137 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1138 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1139 uchar max_host_qng; /* 15 maximum host queueing */
1140 uchar max_dvc_qng; /* maximum per device queuing */
1141 ushort dvc_cntl; /* 16 control bit for driver */
1142 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1143 ushort serial_number_word1; /* 18 Board serial number word 1 */
1144 ushort serial_number_word2; /* 19 Board serial number word 2 */
1145 ushort serial_number_word3; /* 20 Board serial number word 3 */
1146 ushort check_sum; /* 21 EEP check sum */
1147 uchar oem_name[16]; /* 22 OEM name */
1148 ushort dvc_err_code; /* 30 last device driver error code */
1149 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1150 ushort adv_err_addr; /* 32 last uc error address */
1151 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1152 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1153 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1154 ushort reserved36; /* 36 reserved */
1155 ushort reserved37; /* 37 reserved */
1156 ushort reserved38; /* 38 reserved */
1157 ushort reserved39; /* 39 reserved */
1158 ushort reserved40; /* 40 reserved */
1159 ushort reserved41; /* 41 reserved */
1160 ushort reserved42; /* 42 reserved */
1161 ushort reserved43; /* 43 reserved */
1162 ushort reserved44; /* 44 reserved */
1163 ushort reserved45; /* 45 reserved */
1164 ushort reserved46; /* 46 reserved */
1165 ushort reserved47; /* 47 reserved */
1166 ushort reserved48; /* 48 reserved */
1167 ushort reserved49; /* 49 reserved */
1168 ushort reserved50; /* 50 reserved */
1169 ushort reserved51; /* 51 reserved */
1170 ushort reserved52; /* 52 reserved */
1171 ushort reserved53; /* 53 reserved */
1172 ushort reserved54; /* 54 reserved */
1173 ushort reserved55; /* 55 reserved */
1174 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1175 ushort cisprt_msw; /* 57 CIS PTR MSW */
1176 ushort subsysvid; /* 58 SubSystem Vendor ID */
1177 ushort subsysid; /* 59 SubSystem ID */
1178 ushort reserved60; /* 60 reserved */
1179 ushort reserved61; /* 61 reserved */
1180 ushort reserved62; /* 62 reserved */
1181 ushort reserved63; /* 63 reserved */
1182 } ADVEEP_38C0800_CONFIG;
1183
1184 typedef struct adveep_38C1600_config {
1185 /* Word Offset, Description */
1186
1187 ushort cfg_lsw; /* 00 power up initialization */
1188 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1189 /* clear - Func. 0 INTA, Func. 1 INTB */
1190 /* bit 13 set - Load CIS */
1191 /* bit 14 set - BIOS Enable */
1192 /* bit 15 set - Big Endian Mode */
1193 ushort cfg_msw; /* 01 unused */
1194 ushort disc_enable; /* 02 disconnect enable */
1195 ushort wdtr_able; /* 03 Wide DTR able */
1196 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1197 ushort start_motor; /* 05 send start up motor */
1198 ushort tagqng_able; /* 06 tag queuing able */
1199 ushort bios_scan; /* 07 BIOS device control */
1200 ushort scam_tolerant; /* 08 no scam */
1201
1202 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1203 uchar bios_boot_delay; /* power up wait */
1204
1205 uchar scsi_reset_delay; /* 10 reset delay */
1206 uchar bios_id_lun; /* first boot device scsi id & lun */
1207 /* high nibble is lun */
1208 /* low nibble is scsi id */
1209
1210 uchar termination_se; /* 11 0 - automatic */
1211 /* 1 - low off / high off */
1212 /* 2 - low off / high on */
1213 /* 3 - low on / high on */
1214 /* There is no low on / high off */
1215
1216 uchar termination_lvd; /* 11 0 - automatic */
1217 /* 1 - low off / high off */
1218 /* 2 - low off / high on */
1219 /* 3 - low on / high on */
1220 /* There is no low on / high off */
1221
1222 ushort bios_ctrl; /* 12 BIOS control bits */
1223 /* bit 0 BIOS don't act as initiator. */
1224 /* bit 1 BIOS > 1 GB support */
1225 /* bit 2 BIOS > 2 Disk Support */
1226 /* bit 3 BIOS don't support removables */
1227 /* bit 4 BIOS support bootable CD */
1228 /* bit 5 BIOS scan enabled */
1229 /* bit 6 BIOS support multiple LUNs */
1230 /* bit 7 BIOS display of message */
1231 /* bit 8 SCAM disabled */
1232 /* bit 9 Reset SCSI bus during init. */
1233 /* bit 10 Basic Integrity Checking disabled */
1234 /* bit 11 No verbose initialization. */
1235 /* bit 12 SCSI parity enabled */
1236 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1237 /* bit 14 */
1238 /* bit 15 */
1239 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1240 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1241 uchar max_host_qng; /* 15 maximum host queueing */
1242 uchar max_dvc_qng; /* maximum per device queuing */
1243 ushort dvc_cntl; /* 16 control bit for driver */
1244 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1245 ushort serial_number_word1; /* 18 Board serial number word 1 */
1246 ushort serial_number_word2; /* 19 Board serial number word 2 */
1247 ushort serial_number_word3; /* 20 Board serial number word 3 */
1248 ushort check_sum; /* 21 EEP check sum */
1249 uchar oem_name[16]; /* 22 OEM name */
1250 ushort dvc_err_code; /* 30 last device driver error code */
1251 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1252 ushort adv_err_addr; /* 32 last uc error address */
1253 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1254 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1255 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1256 ushort reserved36; /* 36 reserved */
1257 ushort reserved37; /* 37 reserved */
1258 ushort reserved38; /* 38 reserved */
1259 ushort reserved39; /* 39 reserved */
1260 ushort reserved40; /* 40 reserved */
1261 ushort reserved41; /* 41 reserved */
1262 ushort reserved42; /* 42 reserved */
1263 ushort reserved43; /* 43 reserved */
1264 ushort reserved44; /* 44 reserved */
1265 ushort reserved45; /* 45 reserved */
1266 ushort reserved46; /* 46 reserved */
1267 ushort reserved47; /* 47 reserved */
1268 ushort reserved48; /* 48 reserved */
1269 ushort reserved49; /* 49 reserved */
1270 ushort reserved50; /* 50 reserved */
1271 ushort reserved51; /* 51 reserved */
1272 ushort reserved52; /* 52 reserved */
1273 ushort reserved53; /* 53 reserved */
1274 ushort reserved54; /* 54 reserved */
1275 ushort reserved55; /* 55 reserved */
1276 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1277 ushort cisprt_msw; /* 57 CIS PTR MSW */
1278 ushort subsysvid; /* 58 SubSystem Vendor ID */
1279 ushort subsysid; /* 59 SubSystem ID */
1280 ushort reserved60; /* 60 reserved */
1281 ushort reserved61; /* 61 reserved */
1282 ushort reserved62; /* 62 reserved */
1283 ushort reserved63; /* 63 reserved */
1284 } ADVEEP_38C1600_CONFIG;
1285
1286 /*
1287 * EEPROM Commands
1288 */
1289 #define ASC_EEP_CMD_DONE 0x0200
1290
1291 /* bios_ctrl */
1292 #define BIOS_CTRL_BIOS 0x0001
1293 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
1294 #define BIOS_CTRL_GT_2_DISK 0x0004
1295 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1296 #define BIOS_CTRL_BOOTABLE_CD 0x0010
1297 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
1298 #define BIOS_CTRL_DISPLAY_MSG 0x0080
1299 #define BIOS_CTRL_NO_SCAM 0x0100
1300 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1301 #define BIOS_CTRL_INIT_VERBOSE 0x0800
1302 #define BIOS_CTRL_SCSI_PARITY 0x1000
1303 #define BIOS_CTRL_AIPP_DIS 0x2000
1304
1305 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1306
1307 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1308
1309 /*
1310 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1311 * a special 16K Adv Library and Microcode version. After the issue is
1312 * resolved, should restore 32K support.
1313 *
1314 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1315 */
1316 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1317
1318 /*
1319 * Byte I/O register address from base of 'iop_base'.
1320 */
1321 #define IOPB_INTR_STATUS_REG 0x00
1322 #define IOPB_CHIP_ID_1 0x01
1323 #define IOPB_INTR_ENABLES 0x02
1324 #define IOPB_CHIP_TYPE_REV 0x03
1325 #define IOPB_RES_ADDR_4 0x04
1326 #define IOPB_RES_ADDR_5 0x05
1327 #define IOPB_RAM_DATA 0x06
1328 #define IOPB_RES_ADDR_7 0x07
1329 #define IOPB_FLAG_REG 0x08
1330 #define IOPB_RES_ADDR_9 0x09
1331 #define IOPB_RISC_CSR 0x0A
1332 #define IOPB_RES_ADDR_B 0x0B
1333 #define IOPB_RES_ADDR_C 0x0C
1334 #define IOPB_RES_ADDR_D 0x0D
1335 #define IOPB_SOFT_OVER_WR 0x0E
1336 #define IOPB_RES_ADDR_F 0x0F
1337 #define IOPB_MEM_CFG 0x10
1338 #define IOPB_RES_ADDR_11 0x11
1339 #define IOPB_GPIO_DATA 0x12
1340 #define IOPB_RES_ADDR_13 0x13
1341 #define IOPB_FLASH_PAGE 0x14
1342 #define IOPB_RES_ADDR_15 0x15
1343 #define IOPB_GPIO_CNTL 0x16
1344 #define IOPB_RES_ADDR_17 0x17
1345 #define IOPB_FLASH_DATA 0x18
1346 #define IOPB_RES_ADDR_19 0x19
1347 #define IOPB_RES_ADDR_1A 0x1A
1348 #define IOPB_RES_ADDR_1B 0x1B
1349 #define IOPB_RES_ADDR_1C 0x1C
1350 #define IOPB_RES_ADDR_1D 0x1D
1351 #define IOPB_RES_ADDR_1E 0x1E
1352 #define IOPB_RES_ADDR_1F 0x1F
1353 #define IOPB_DMA_CFG0 0x20
1354 #define IOPB_DMA_CFG1 0x21
1355 #define IOPB_TICKLE 0x22
1356 #define IOPB_DMA_REG_WR 0x23
1357 #define IOPB_SDMA_STATUS 0x24
1358 #define IOPB_SCSI_BYTE_CNT 0x25
1359 #define IOPB_HOST_BYTE_CNT 0x26
1360 #define IOPB_BYTE_LEFT_TO_XFER 0x27
1361 #define IOPB_BYTE_TO_XFER_0 0x28
1362 #define IOPB_BYTE_TO_XFER_1 0x29
1363 #define IOPB_BYTE_TO_XFER_2 0x2A
1364 #define IOPB_BYTE_TO_XFER_3 0x2B
1365 #define IOPB_ACC_GRP 0x2C
1366 #define IOPB_RES_ADDR_2D 0x2D
1367 #define IOPB_DEV_ID 0x2E
1368 #define IOPB_RES_ADDR_2F 0x2F
1369 #define IOPB_SCSI_DATA 0x30
1370 #define IOPB_RES_ADDR_31 0x31
1371 #define IOPB_RES_ADDR_32 0x32
1372 #define IOPB_SCSI_DATA_HSHK 0x33
1373 #define IOPB_SCSI_CTRL 0x34
1374 #define IOPB_RES_ADDR_35 0x35
1375 #define IOPB_RES_ADDR_36 0x36
1376 #define IOPB_RES_ADDR_37 0x37
1377 #define IOPB_RAM_BIST 0x38
1378 #define IOPB_PLL_TEST 0x39
1379 #define IOPB_PCI_INT_CFG 0x3A
1380 #define IOPB_RES_ADDR_3B 0x3B
1381 #define IOPB_RFIFO_CNT 0x3C
1382 #define IOPB_RES_ADDR_3D 0x3D
1383 #define IOPB_RES_ADDR_3E 0x3E
1384 #define IOPB_RES_ADDR_3F 0x3F
1385
1386 /*
1387 * Word I/O register address from base of 'iop_base'.
1388 */
1389 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
1390 #define IOPW_CTRL_REG 0x02 /* CC */
1391 #define IOPW_RAM_ADDR 0x04 /* LA */
1392 #define IOPW_RAM_DATA 0x06 /* LD */
1393 #define IOPW_RES_ADDR_08 0x08
1394 #define IOPW_RISC_CSR 0x0A /* CSR */
1395 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1396 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1397 #define IOPW_RES_ADDR_10 0x10
1398 #define IOPW_SEL_MASK 0x12 /* SM */
1399 #define IOPW_RES_ADDR_14 0x14
1400 #define IOPW_FLASH_ADDR 0x16 /* FA */
1401 #define IOPW_RES_ADDR_18 0x18
1402 #define IOPW_EE_CMD 0x1A /* EC */
1403 #define IOPW_EE_DATA 0x1C /* ED */
1404 #define IOPW_SFIFO_CNT 0x1E /* SFC */
1405 #define IOPW_RES_ADDR_20 0x20
1406 #define IOPW_Q_BASE 0x22 /* QB */
1407 #define IOPW_QP 0x24 /* QP */
1408 #define IOPW_IX 0x26 /* IX */
1409 #define IOPW_SP 0x28 /* SP */
1410 #define IOPW_PC 0x2A /* PC */
1411 #define IOPW_RES_ADDR_2C 0x2C
1412 #define IOPW_RES_ADDR_2E 0x2E
1413 #define IOPW_SCSI_DATA 0x30 /* SD */
1414 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1415 #define IOPW_SCSI_CTRL 0x34 /* SC */
1416 #define IOPW_HSHK_CFG 0x36 /* HCFG */
1417 #define IOPW_SXFR_STATUS 0x36 /* SXS */
1418 #define IOPW_SXFR_CNTL 0x38 /* SXL */
1419 #define IOPW_SXFR_CNTH 0x3A /* SXH */
1420 #define IOPW_RES_ADDR_3C 0x3C
1421 #define IOPW_RFIFO_DATA 0x3E /* RFD */
1422
1423 /*
1424 * Doubleword I/O register address from base of 'iop_base'.
1425 */
1426 #define IOPDW_RES_ADDR_0 0x00
1427 #define IOPDW_RAM_DATA 0x04
1428 #define IOPDW_RES_ADDR_8 0x08
1429 #define IOPDW_RES_ADDR_C 0x0C
1430 #define IOPDW_RES_ADDR_10 0x10
1431 #define IOPDW_COMMA 0x14
1432 #define IOPDW_COMMB 0x18
1433 #define IOPDW_RES_ADDR_1C 0x1C
1434 #define IOPDW_SDMA_ADDR0 0x20
1435 #define IOPDW_SDMA_ADDR1 0x24
1436 #define IOPDW_SDMA_COUNT 0x28
1437 #define IOPDW_SDMA_ERROR 0x2C
1438 #define IOPDW_RDMA_ADDR0 0x30
1439 #define IOPDW_RDMA_ADDR1 0x34
1440 #define IOPDW_RDMA_COUNT 0x38
1441 #define IOPDW_RDMA_ERROR 0x3C
1442
1443 #define ADV_CHIP_ID_BYTE 0x25
1444 #define ADV_CHIP_ID_WORD 0x04C1
1445
1446 #define ADV_INTR_ENABLE_HOST_INTR 0x01
1447 #define ADV_INTR_ENABLE_SEL_INTR 0x02
1448 #define ADV_INTR_ENABLE_DPR_INTR 0x04
1449 #define ADV_INTR_ENABLE_RTA_INTR 0x08
1450 #define ADV_INTR_ENABLE_RMA_INTR 0x10
1451 #define ADV_INTR_ENABLE_RST_INTR 0x20
1452 #define ADV_INTR_ENABLE_DPE_INTR 0x40
1453 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1454
1455 #define ADV_INTR_STATUS_INTRA 0x01
1456 #define ADV_INTR_STATUS_INTRB 0x02
1457 #define ADV_INTR_STATUS_INTRC 0x04
1458
1459 #define ADV_RISC_CSR_STOP (0x0000)
1460 #define ADV_RISC_TEST_COND (0x2000)
1461 #define ADV_RISC_CSR_RUN (0x4000)
1462 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1463
1464 #define ADV_CTRL_REG_HOST_INTR 0x0100
1465 #define ADV_CTRL_REG_SEL_INTR 0x0200
1466 #define ADV_CTRL_REG_DPR_INTR 0x0400
1467 #define ADV_CTRL_REG_RTA_INTR 0x0800
1468 #define ADV_CTRL_REG_RMA_INTR 0x1000
1469 #define ADV_CTRL_REG_RES_BIT14 0x2000
1470 #define ADV_CTRL_REG_DPE_INTR 0x4000
1471 #define ADV_CTRL_REG_POWER_DONE 0x8000
1472 #define ADV_CTRL_REG_ANY_INTR 0xFF00
1473
1474 #define ADV_CTRL_REG_CMD_RESET 0x00C6
1475 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1476 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1477 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1478 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1479
1480 #define ADV_TICKLE_NOP 0x00
1481 #define ADV_TICKLE_A 0x01
1482 #define ADV_TICKLE_B 0x02
1483 #define ADV_TICKLE_C 0x03
1484
1485 #define AdvIsIntPending(port) \
1486 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1487
1488 /*
1489 * SCSI_CFG0 Register bit definitions
1490 */
1491 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1492 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1493 #define EVEN_PARITY 0x1000 /* Select Even Parity */
1494 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1495 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1496 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1497 #define SCAM_EN 0x0080 /* Enable SCAM selection */
1498 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1499 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1500 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1501 #define OUR_ID 0x000F /* SCSI ID */
1502
1503 /*
1504 * SCSI_CFG1 Register bit definitions
1505 */
1506 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1507 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1508 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1509 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
1510 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1511 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1512 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1513 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1514 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1515 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1516 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1517 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1518 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1519 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1520 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1521
1522 /*
1523 * Addendum for ASC-38C0800 Chip
1524 *
1525 * The ASC-38C1600 Chip uses the same definitions except that the
1526 * bus mode override bits [12:10] have been moved to byte register
1527 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1528 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1529 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1530 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1531 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1532 */
1533 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1534 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1535 #define HVD 0x1000 /* HVD Device Detect */
1536 #define LVD 0x0800 /* LVD Device Detect */
1537 #define SE 0x0400 /* SE Device Detect */
1538 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
1539 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1540 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1541 #define TERM_SE 0x0030 /* SE Termination Bits */
1542 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1543 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1544 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1545 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1546 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1547 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1548 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1549 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1550
1551 #define CABLE_ILLEGAL_A 0x7
1552 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1553
1554 #define CABLE_ILLEGAL_B 0xB
1555 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1556
1557 /*
1558 * MEM_CFG Register bit definitions
1559 */
1560 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1561 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1562 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1563 #define RAM_SZ_2KB 0x00 /* 2 KB */
1564 #define RAM_SZ_4KB 0x04 /* 4 KB */
1565 #define RAM_SZ_8KB 0x08 /* 8 KB */
1566 #define RAM_SZ_16KB 0x0C /* 16 KB */
1567 #define RAM_SZ_32KB 0x10 /* 32 KB */
1568 #define RAM_SZ_64KB 0x14 /* 64 KB */
1569
1570 /*
1571 * DMA_CFG0 Register bit definitions
1572 *
1573 * This register is only accessible to the host.
1574 */
1575 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1576 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1577 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
1578 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
1579 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
1580 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
1581 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1582 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
1583 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
1584 #define START_CTL 0x0C /* DMA start conditions */
1585 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
1586 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1587 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1588 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1589 #define READ_CMD 0x03 /* Memory Read Method */
1590 #define READ_CMD_MR 0x00 /* Memory Read */
1591 #define READ_CMD_MRL 0x02 /* Memory Read Long */
1592 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1593
1594 /*
1595 * ASC-38C0800 RAM BIST Register bit definitions
1596 */
1597 #define RAM_TEST_MODE 0x80
1598 #define PRE_TEST_MODE 0x40
1599 #define NORMAL_MODE 0x00
1600 #define RAM_TEST_DONE 0x10
1601 #define RAM_TEST_STATUS 0x0F
1602 #define RAM_TEST_HOST_ERROR 0x08
1603 #define RAM_TEST_INTRAM_ERROR 0x04
1604 #define RAM_TEST_RISC_ERROR 0x02
1605 #define RAM_TEST_SCSI_ERROR 0x01
1606 #define RAM_TEST_SUCCESS 0x00
1607 #define PRE_TEST_VALUE 0x05
1608 #define NORMAL_VALUE 0x00
1609
1610 /*
1611 * ASC38C1600 Definitions
1612 *
1613 * IOPB_PCI_INT_CFG Bit Field Definitions
1614 */
1615
1616 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1617
1618 /*
1619 * Bit 1 can be set to change the interrupt for the Function to operate in
1620 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1621 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1622 * mode, otherwise the operating mode is undefined.
1623 */
1624 #define TOTEMPOLE 0x02
1625
1626 /*
1627 * Bit 0 can be used to change the Int Pin for the Function. The value is
1628 * 0 by default for both Functions with Function 0 using INT A and Function
1629 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1630 * INT A is used.
1631 *
1632 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1633 * value specified in the PCI Configuration Space.
1634 */
1635 #define INTAB 0x01
1636
1637 /*
1638 * Adv Library Status Definitions
1639 */
1640 #define ADV_TRUE 1
1641 #define ADV_FALSE 0
1642 #define ADV_SUCCESS 1
1643 #define ADV_BUSY 0
1644 #define ADV_ERROR (-1)
1645
1646 /*
1647 * ADV_DVC_VAR 'warn_code' values
1648 */
1649 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1650 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1651 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
1652 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1653
1654 #define ADV_MAX_TID 15 /* max. target identifier */
1655 #define ADV_MAX_LUN 7 /* max. logical unit number */
1656
1657 /*
1658 * Fixed locations of microcode operating variables.
1659 */
1660 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1661 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1662 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1663 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1664 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1665 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1666 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1667 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1668 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1669 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1670 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1671 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1672 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1673 #define ASC_MC_CHIP_TYPE 0x009A
1674 #define ASC_MC_INTRB_CODE 0x009B
1675 #define ASC_MC_WDTR_ABLE 0x009C
1676 #define ASC_MC_SDTR_ABLE 0x009E
1677 #define ASC_MC_TAGQNG_ABLE 0x00A0
1678 #define ASC_MC_DISC_ENABLE 0x00A2
1679 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
1680 #define ASC_MC_IDLE_CMD 0x00A6
1681 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1682 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1683 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1684 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1685 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1686 #define ASC_MC_SDTR_DONE 0x00B6
1687 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1688 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1689 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
1690 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1691 #define ASC_MC_WDTR_DONE 0x0124
1692 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1693 #define ASC_MC_ICQ 0x0160
1694 #define ASC_MC_IRQ 0x0164
1695 #define ASC_MC_PPR_ABLE 0x017A
1696
1697 /*
1698 * BIOS LRAM variable absolute offsets.
1699 */
1700 #define BIOS_CODESEG 0x54
1701 #define BIOS_CODELEN 0x56
1702 #define BIOS_SIGNATURE 0x58
1703 #define BIOS_VERSION 0x5A
1704
1705 /*
1706 * Microcode Control Flags
1707 *
1708 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1709 * and handled by the microcode.
1710 */
1711 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1712 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1713
1714 /*
1715 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1716 */
1717 #define HSHK_CFG_WIDE_XFR 0x8000
1718 #define HSHK_CFG_RATE 0x0F00
1719 #define HSHK_CFG_OFFSET 0x001F
1720
1721 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1722 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1723 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1724 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1725
1726 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1727 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1728 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1729 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1730 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1731
1732 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1733 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1734 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1735 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1736 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1737 /*
1738 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1739 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1740 */
1741 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
1742 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
1743
1744 /*
1745 * All fields here are accessed by the board microcode and need to be
1746 * little-endian.
1747 */
1748 typedef struct adv_carr_t {
1749 ADV_VADDR carr_va; /* Carrier Virtual Address */
1750 ADV_PADDR carr_pa; /* Carrier Physical Address */
1751 ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1752 /*
1753 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
1754 *
1755 * next_vpa [3:1] Reserved Bits
1756 * next_vpa [0] Done Flag set in Response Queue.
1757 */
1758 ADV_VADDR next_vpa;
1759 } ADV_CARR_T;
1760
1761 /*
1762 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1763 */
1764 #define ASC_NEXT_VPA_MASK 0xFFFFFFF0
1765
1766 #define ASC_RQ_DONE 0x00000001
1767 #define ASC_RQ_GOOD 0x00000002
1768 #define ASC_CQ_STOPPER 0x00000000
1769
1770 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1771
1772 #define ADV_CARRIER_NUM_PAGE_CROSSING \
1773 (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + (PAGE_SIZE - 1))/PAGE_SIZE)
1774
1775 #define ADV_CARRIER_BUFSIZE \
1776 ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
1777
1778 /*
1779 * ASC_SCSI_REQ_Q 'a_flag' definitions
1780 *
1781 * The Adv Library should limit use to the lower nibble (4 bits) of
1782 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1783 */
1784 #define ADV_POLL_REQUEST 0x01 /* poll for request completion */
1785 #define ADV_SCSIQ_DONE 0x02 /* request done */
1786 #define ADV_DONT_RETRY 0x08 /* don't do retry */
1787
1788 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
1789 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
1790 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
1791
1792 /*
1793 * Adapter temporary configuration structure
1794 *
1795 * This structure can be discarded after initialization. Don't add
1796 * fields here needed after initialization.
1797 *
1798 * Field naming convention:
1799 *
1800 * *_enable indicates the field enables or disables a feature. The
1801 * value of the field is never reset.
1802 */
1803 typedef struct adv_dvc_cfg {
1804 ushort disc_enable; /* enable disconnection */
1805 uchar chip_version; /* chip version */
1806 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1807 ushort control_flag; /* Microcode Control Flag */
1808 ushort mcode_date; /* Microcode date */
1809 ushort mcode_version; /* Microcode version */
1810 ushort serial1; /* EEPROM serial number word 1 */
1811 ushort serial2; /* EEPROM serial number word 2 */
1812 ushort serial3; /* EEPROM serial number word 3 */
1813 } ADV_DVC_CFG;
1814
1815 struct adv_dvc_var;
1816 struct adv_scsi_req_q;
1817
1818 typedef struct asc_sg_block {
1819 uchar reserved1;
1820 uchar reserved2;
1821 uchar reserved3;
1822 uchar sg_cnt; /* Valid entries in block. */
1823 ADV_PADDR sg_ptr; /* Pointer to next sg block. */
1824 struct {
1825 ADV_PADDR sg_addr; /* SG element address. */
1826 ADV_DCNT sg_count; /* SG element count. */
1827 } sg_list[NO_OF_SG_PER_BLOCK];
1828 } ADV_SG_BLOCK;
1829
1830 /*
1831 * ADV_SCSI_REQ_Q - microcode request structure
1832 *
1833 * All fields in this structure up to byte 60 are used by the microcode.
1834 * The microcode makes assumptions about the size and ordering of fields
1835 * in this structure. Do not change the structure definition here without
1836 * coordinating the change with the microcode.
1837 *
1838 * All fields accessed by microcode must be maintained in little_endian
1839 * order.
1840 */
1841 typedef struct adv_scsi_req_q {
1842 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
1843 uchar target_cmd;
1844 uchar target_id; /* Device target identifier. */
1845 uchar target_lun; /* Device target logical unit number. */
1846 ADV_PADDR data_addr; /* Data buffer physical address. */
1847 ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */
1848 ADV_PADDR sense_addr;
1849 ADV_PADDR carr_pa;
1850 uchar mflag;
1851 uchar sense_len;
1852 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
1853 uchar scsi_cntl;
1854 uchar done_status; /* Completion status. */
1855 uchar scsi_status; /* SCSI status byte. */
1856 uchar host_status; /* Ucode host status. */
1857 uchar sg_working_ix;
1858 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
1859 ADV_PADDR sg_real_addr; /* SG list physical address. */
1860 ADV_PADDR scsiq_rptr;
1861 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
1862 ADV_VADDR scsiq_ptr;
1863 ADV_VADDR carr_va;
1864 /*
1865 * End of microcode structure - 60 bytes. The rest of the structure
1866 * is used by the Adv Library and ignored by the microcode.
1867 */
1868 ADV_VADDR srb_ptr;
1869 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
1870 char *vdata_addr; /* Data buffer virtual address. */
1871 uchar a_flag;
1872 uchar pad[2]; /* Pad out to a word boundary. */
1873 } ADV_SCSI_REQ_Q;
1874
1875 /*
1876 * The following two structures are used to process Wide Board requests.
1877 *
1878 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1879 * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
1880 * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
1881 * Mid-Level SCSI request structure.
1882 *
1883 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1884 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1885 * up to 255 scatter-gather elements may be used per request or
1886 * ADV_SCSI_REQ_Q.
1887 *
1888 * Both structures must be 32 byte aligned.
1889 */
1890 typedef struct adv_sgblk {
1891 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
1892 uchar align[32]; /* Sgblock structure padding. */
1893 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
1894 } adv_sgblk_t;
1895
1896 typedef struct adv_req {
1897 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
1898 uchar align[32]; /* Request structure padding. */
1899 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
1900 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
1901 struct adv_req *next_reqp; /* Next Request Structure. */
1902 } adv_req_t;
1903
1904 /*
1905 * Adapter operation variable structure.
1906 *
1907 * One structure is required per host adapter.
1908 *
1909 * Field naming convention:
1910 *
1911 * *_able indicates both whether a feature should be enabled or disabled
1912 * and whether a device isi capable of the feature. At initialization
1913 * this field may be set, but later if a device is found to be incapable
1914 * of the feature, the field is cleared.
1915 */
1916 typedef struct adv_dvc_var {
1917 AdvPortAddr iop_base; /* I/O port address */
1918 ushort err_code; /* fatal error code */
1919 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
1920 ushort wdtr_able; /* try WDTR for a device */
1921 ushort sdtr_able; /* try SDTR for a device */
1922 ushort ultra_able; /* try SDTR Ultra speed for a device */
1923 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
1924 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
1925 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
1926 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
1927 ushort tagqng_able; /* try tagged queuing with a device */
1928 ushort ppr_able; /* PPR message capable per TID bitmask. */
1929 uchar max_dvc_qng; /* maximum number of tagged commands per device */
1930 ushort start_motor; /* start motor command allowed */
1931 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
1932 uchar chip_no; /* should be assigned by caller */
1933 uchar max_host_qng; /* maximum number of Q'ed command allowed */
1934 ushort no_scam; /* scam_tolerant of EEPROM */
1935 struct asc_board *drv_ptr; /* driver pointer to private structure */
1936 uchar chip_scsi_id; /* chip SCSI target ID */
1937 uchar chip_type;
1938 uchar bist_err_code;
1939 ADV_CARR_T *carrier_buf;
1940 ADV_CARR_T *carr_freelist; /* Carrier free list. */
1941 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
1942 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
1943 ushort carr_pending_cnt; /* Count of pending carriers. */
1944 struct adv_req *orig_reqp; /* adv_req_t memory block. */
1945 /*
1946 * Note: The following fields will not be used after initialization. The
1947 * driver may discard the buffer after initialization is done.
1948 */
1949 ADV_DVC_CFG *cfg; /* temporary configuration structure */
1950 } ADV_DVC_VAR;
1951
1952 /*
1953 * Microcode idle loop commands
1954 */
1955 #define IDLE_CMD_COMPLETED 0
1956 #define IDLE_CMD_STOP_CHIP 0x0001
1957 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
1958 #define IDLE_CMD_SEND_INT 0x0004
1959 #define IDLE_CMD_ABORT 0x0008
1960 #define IDLE_CMD_DEVICE_RESET 0x0010
1961 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
1962 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
1963 #define IDLE_CMD_SCSIREQ 0x0080
1964
1965 #define IDLE_CMD_STATUS_SUCCESS 0x0001
1966 #define IDLE_CMD_STATUS_FAILURE 0x0002
1967
1968 /*
1969 * AdvSendIdleCmd() flag definitions.
1970 */
1971 #define ADV_NOWAIT 0x01
1972
1973 /*
1974 * Wait loop time out values.
1975 */
1976 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
1977 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
1978 #define SCSI_MAX_RETRY 10 /* retry count */
1979
1980 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
1981 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
1982 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
1983 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
1984
1985 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
1986
1987 /* Read byte from a register. */
1988 #define AdvReadByteRegister(iop_base, reg_off) \
1989 (ADV_MEM_READB((iop_base) + (reg_off)))
1990
1991 /* Write byte to a register. */
1992 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
1993 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1994
1995 /* Read word (2 bytes) from a register. */
1996 #define AdvReadWordRegister(iop_base, reg_off) \
1997 (ADV_MEM_READW((iop_base) + (reg_off)))
1998
1999 /* Write word (2 bytes) to a register. */
2000 #define AdvWriteWordRegister(iop_base, reg_off, word) \
2001 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
2002
2003 /* Write dword (4 bytes) to a register. */
2004 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
2005 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
2006
2007 /* Read byte from LRAM. */
2008 #define AdvReadByteLram(iop_base, addr, byte) \
2009 do { \
2010 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2011 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
2012 } while (0)
2013
2014 /* Write byte to LRAM. */
2015 #define AdvWriteByteLram(iop_base, addr, byte) \
2016 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2017 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
2018
2019 /* Read word (2 bytes) from LRAM. */
2020 #define AdvReadWordLram(iop_base, addr, word) \
2021 do { \
2022 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2023 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
2024 } while (0)
2025
2026 /* Write word (2 bytes) to LRAM. */
2027 #define AdvWriteWordLram(iop_base, addr, word) \
2028 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2029 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2030
2031 /* Write little-endian double word (4 bytes) to LRAM */
2032 /* Because of unspecified C language ordering don't use auto-increment. */
2033 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
2034 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2035 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2036 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2037 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2038 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2039 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2040
2041 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
2042 #define AdvReadWordAutoIncLram(iop_base) \
2043 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2044
2045 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
2046 #define AdvWriteWordAutoIncLram(iop_base, word) \
2047 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2048
2049 /*
2050 * Define macro to check for Condor signature.
2051 *
2052 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2053 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2054 */
2055 #define AdvFindSignature(iop_base) \
2056 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2057 ADV_CHIP_ID_BYTE) && \
2058 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2059 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
2060
2061 /*
2062 * Define macro to Return the version number of the chip at 'iop_base'.
2063 *
2064 * The second parameter 'bus_type' is currently unused.
2065 */
2066 #define AdvGetChipVersion(iop_base, bus_type) \
2067 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2068
2069 /*
2070 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
2071 * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
2072 *
2073 * If the request has not yet been sent to the device it will simply be
2074 * aborted from RISC memory. If the request is disconnected it will be
2075 * aborted on reselection by sending an Abort Message to the target ID.
2076 *
2077 * Return value:
2078 * ADV_TRUE(1) - Queue was successfully aborted.
2079 * ADV_FALSE(0) - Queue was not found on the active queue list.
2080 */
2081 #define AdvAbortQueue(asc_dvc, scsiq) \
2082 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2083 (ADV_DCNT) (scsiq))
2084
2085 /*
2086 * Send a Bus Device Reset Message to the specified target ID.
2087 *
2088 * All outstanding commands will be purged if sending the
2089 * Bus Device Reset Message is successful.
2090 *
2091 * Return Value:
2092 * ADV_TRUE(1) - All requests on the target are purged.
2093 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2094 * are not purged.
2095 */
2096 #define AdvResetDevice(asc_dvc, target_id) \
2097 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2098 (ADV_DCNT) (target_id))
2099
2100 /*
2101 * SCSI Wide Type definition.
2102 */
2103 #define ADV_SCSI_BIT_ID_TYPE ushort
2104
2105 /*
2106 * AdvInitScsiTarget() 'cntl_flag' options.
2107 */
2108 #define ADV_SCAN_LUN 0x01
2109 #define ADV_CAPINFO_NOLUN 0x02
2110
2111 /*
2112 * Convert target id to target id bit mask.
2113 */
2114 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2115
2116 /*
2117 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2118 */
2119
2120 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
2121 #define QD_NO_ERROR 0x01
2122 #define QD_ABORTED_BY_HOST 0x02
2123 #define QD_WITH_ERROR 0x04
2124
2125 #define QHSTA_NO_ERROR 0x00
2126 #define QHSTA_M_SEL_TIMEOUT 0x11
2127 #define QHSTA_M_DATA_OVER_RUN 0x12
2128 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2129 #define QHSTA_M_QUEUE_ABORTED 0x15
2130 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2131 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2132 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2133 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2134 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2135 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2136 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
2137 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2138 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2139 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2140 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2141 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2142 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2143 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2144 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2145 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
2146 #define QHSTA_M_WTM_TIMEOUT 0x41
2147 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2148 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2149 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2150 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2151 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2152 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
2153
2154 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2155 #define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7)
2156 #define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF)
2157 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2158
2159 /*
2160 * Total contiguous memory needed for driver SG blocks.
2161 *
2162 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2163 * number of scatter-gather elements the driver supports in a
2164 * single request.
2165 */
2166
2167 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2168 (sizeof(ADV_SG_BLOCK) * \
2169 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2170
2171 /* struct asc_board flags */
2172 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
2173
2174 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2175
2176 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
2177
2178 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
2179
2180 /* Asc Library return codes */
2181 #define ASC_TRUE 1
2182 #define ASC_FALSE 0
2183 #define ASC_NOERROR 1
2184 #define ASC_BUSY 0
2185 #define ASC_ERROR (-1)
2186
2187 /* struct scsi_cmnd function return codes */
2188 #define STATUS_BYTE(byte) (byte)
2189 #define MSG_BYTE(byte) ((byte) << 8)
2190 #define HOST_BYTE(byte) ((byte) << 16)
2191 #define DRIVER_BYTE(byte) ((byte) << 24)
2192
2193 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2194 #ifndef ADVANSYS_STATS
2195 #define ASC_STATS_ADD(shost, counter, count)
2196 #else /* ADVANSYS_STATS */
2197 #define ASC_STATS_ADD(shost, counter, count) \
2198 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2199 #endif /* ADVANSYS_STATS */
2200
2201 /* If the result wraps when calculating tenths, return 0. */
2202 #define ASC_TENTHS(num, den) \
2203 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2204 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2205
2206 /*
2207 * Display a message to the console.
2208 */
2209 #define ASC_PRINT(s) \
2210 { \
2211 printk("advansys: "); \
2212 printk(s); \
2213 }
2214
2215 #define ASC_PRINT1(s, a1) \
2216 { \
2217 printk("advansys: "); \
2218 printk((s), (a1)); \
2219 }
2220
2221 #define ASC_PRINT2(s, a1, a2) \
2222 { \
2223 printk("advansys: "); \
2224 printk((s), (a1), (a2)); \
2225 }
2226
2227 #define ASC_PRINT3(s, a1, a2, a3) \
2228 { \
2229 printk("advansys: "); \
2230 printk((s), (a1), (a2), (a3)); \
2231 }
2232
2233 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2234 { \
2235 printk("advansys: "); \
2236 printk((s), (a1), (a2), (a3), (a4)); \
2237 }
2238
2239 #ifndef ADVANSYS_DEBUG
2240
2241 #define ASC_DBG(lvl, s...)
2242 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2243 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2244 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2245 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2246 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2247 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2248 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2249 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2250 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2251
2252 #else /* ADVANSYS_DEBUG */
2253
2254 /*
2255 * Debugging Message Levels:
2256 * 0: Errors Only
2257 * 1: High-Level Tracing
2258 * 2-N: Verbose Tracing
2259 */
2260
2261 #define ASC_DBG(lvl, format, arg...) { \
2262 if (asc_dbglvl >= (lvl)) \
2263 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \
2264 __func__ , ## arg); \
2265 }
2266
2267 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2268 { \
2269 if (asc_dbglvl >= (lvl)) { \
2270 asc_prt_scsi_host(s); \
2271 } \
2272 }
2273
2274 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2275 { \
2276 if (asc_dbglvl >= (lvl)) { \
2277 asc_prt_asc_scsi_q(scsiqp); \
2278 } \
2279 }
2280
2281 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2282 { \
2283 if (asc_dbglvl >= (lvl)) { \
2284 asc_prt_asc_qdone_info(qdone); \
2285 } \
2286 }
2287
2288 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2289 { \
2290 if (asc_dbglvl >= (lvl)) { \
2291 asc_prt_adv_scsi_req_q(scsiqp); \
2292 } \
2293 }
2294
2295 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2296 { \
2297 if (asc_dbglvl >= (lvl)) { \
2298 asc_prt_hex((name), (start), (length)); \
2299 } \
2300 }
2301
2302 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2303 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2304
2305 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2306 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2307
2308 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2309 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2310 #endif /* ADVANSYS_DEBUG */
2311
2312 #ifdef ADVANSYS_STATS
2313
2314 /* Per board statistics structure */
2315 struct asc_stats {
2316 /* Driver Entrypoint Statistics */
2317 ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */
2318 ADV_DCNT reset; /* # calls to advansys_eh_bus_reset() */
2319 ADV_DCNT biosparam; /* # calls to advansys_biosparam() */
2320 ADV_DCNT interrupt; /* # advansys_interrupt() calls */
2321 ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */
2322 ADV_DCNT done; /* # calls to request's scsi_done function */
2323 ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
2324 ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
2325 ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
2326 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2327 ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */
2328 ADV_DCNT exe_busy; /* # ASC_BUSY returns. */
2329 ADV_DCNT exe_error; /* # ASC_ERROR returns. */
2330 ADV_DCNT exe_unknown; /* # unknown returns. */
2331 /* Data Transfer Statistics */
2332 ADV_DCNT xfer_cnt; /* # I/O requests received */
2333 ADV_DCNT xfer_elem; /* # scatter-gather elements */
2334 ADV_DCNT xfer_sect; /* # 512-byte blocks */
2335 };
2336 #endif /* ADVANSYS_STATS */
2337
2338 /*
2339 * Structure allocated for each board.
2340 *
2341 * This structure is allocated by scsi_host_alloc() at the end
2342 * of the 'Scsi_Host' structure starting at the 'hostdata'
2343 * field. It is guaranteed to be allocated from DMA-able memory.
2344 */
2345 struct asc_board {
2346 struct device *dev;
2347 uint flags; /* Board flags */
2348 unsigned int irq;
2349 union {
2350 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
2351 ADV_DVC_VAR adv_dvc_var; /* Wide board */
2352 } dvc_var;
2353 union {
2354 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
2355 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
2356 } dvc_cfg;
2357 ushort asc_n_io_port; /* Number I/O ports. */
2358 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
2359 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2360 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
2361 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2362 union {
2363 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
2364 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
2365 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
2366 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
2367 } eep_config;
2368 ulong last_reset; /* Saved last reset time */
2369 /* /proc/scsi/advansys/[0...] */
2370 #ifdef ADVANSYS_STATS
2371 struct asc_stats asc_stats; /* Board statistics */
2372 #endif /* ADVANSYS_STATS */
2373 /*
2374 * The following fields are used only for Narrow Boards.
2375 */
2376 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
2377 /*
2378 * The following fields are used only for Wide Boards.
2379 */
2380 void __iomem *ioremap_addr; /* I/O Memory remap address. */
2381 ushort ioport; /* I/O Port address. */
2382 adv_req_t *adv_reqp; /* Request structures. */
2383 adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */
2384 ushort bios_signature; /* BIOS Signature. */
2385 ushort bios_version; /* BIOS Version. */
2386 ushort bios_codeseg; /* BIOS Code Segment. */
2387 ushort bios_codelen; /* BIOS Code Segment Length. */
2388 };
2389
2390 #define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
2391 dvc_var.asc_dvc_var)
2392 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2393 dvc_var.adv_dvc_var)
2394 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2395
2396 #ifdef ADVANSYS_DEBUG
2397 static int asc_dbglvl = 3;
2398
2399 /*
2400 * asc_prt_asc_dvc_var()
2401 */
2402 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2403 {
2404 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2405
2406 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2407 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2408
2409 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2410 (unsigned)h->init_sdtr);
2411
2412 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2413 "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2414 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2415 (unsigned)h->chip_no);
2416
2417 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2418 "%u,\n", (unsigned)h->queue_full_or_busy,
2419 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2420
2421 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2422 "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2423 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2424 (unsigned)h->in_critical_cnt);
2425
2426 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2427 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2428 (unsigned)h->init_state, (unsigned)h->no_scam,
2429 (unsigned)h->pci_fix_asyn_xfer);
2430
2431 printk(" cfg 0x%lx\n", (ulong)h->cfg);
2432 }
2433
2434 /*
2435 * asc_prt_asc_dvc_cfg()
2436 */
2437 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2438 {
2439 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2440
2441 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2442 h->can_tagged_qng, h->cmd_qng_enabled);
2443 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2444 h->disc_enable, h->sdtr_enable);
2445
2446 printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2447 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2448 h->isa_dma_channel, h->chip_version);
2449
2450 printk(" mcode_date 0x%x, mcode_version %d\n",
2451 h->mcode_date, h->mcode_version);
2452 }
2453
2454 /*
2455 * asc_prt_adv_dvc_var()
2456 *
2457 * Display an ADV_DVC_VAR structure.
2458 */
2459 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2460 {
2461 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2462
2463 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2464 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2465
2466 printk(" sdtr_able 0x%x, wdtr_able 0x%x\n",
2467 (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
2468
2469 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n",
2470 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2471
2472 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
2473 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2474 (ulong)h->carr_freelist);
2475
2476 printk(" icq_sp 0x%lx, irq_sp 0x%lx\n",
2477 (ulong)h->icq_sp, (ulong)h->irq_sp);
2478
2479 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
2480 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2481
2482 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
2483 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2484 }
2485
2486 /*
2487 * asc_prt_adv_dvc_cfg()
2488 *
2489 * Display an ADV_DVC_CFG structure.
2490 */
2491 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2492 {
2493 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2494
2495 printk(" disc_enable 0x%x, termination 0x%x\n",
2496 h->disc_enable, h->termination);
2497
2498 printk(" chip_version 0x%x, mcode_date 0x%x\n",
2499 h->chip_version, h->mcode_date);
2500
2501 printk(" mcode_version 0x%x, control_flag 0x%x\n",
2502 h->mcode_version, h->control_flag);
2503 }
2504
2505 /*
2506 * asc_prt_scsi_host()
2507 */
2508 static void asc_prt_scsi_host(struct Scsi_Host *s)
2509 {
2510 struct asc_board *boardp = shost_priv(s);
2511
2512 printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
2513 printk(" host_busy %u, host_no %d,\n",
2514 atomic_read(&s->host_busy), s->host_no);
2515
2516 printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2517 (ulong)s->base, (ulong)s->io_port, boardp->irq);
2518
2519 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2520 s->dma_channel, s->this_id, s->can_queue);
2521
2522 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2523 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2524
2525 if (ASC_NARROW_BOARD(boardp)) {
2526 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2527 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2528 } else {
2529 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2530 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
2531 }
2532 }
2533
2534 /*
2535 * asc_prt_hex()
2536 *
2537 * Print hexadecimal output in 4 byte groupings 32 bytes
2538 * or 8 double-words per line.
2539 */
2540 static void asc_prt_hex(char *f, uchar *s, int l)
2541 {
2542 int i;
2543 int j;
2544 int k;
2545 int m;
2546
2547 printk("%s: (%d bytes)\n", f, l);
2548
2549 for (i = 0; i < l; i += 32) {
2550
2551 /* Display a maximum of 8 double-words per line. */
2552 if ((k = (l - i) / 4) >= 8) {
2553 k = 8;
2554 m = 0;
2555 } else {
2556 m = (l - i) % 4;
2557 }
2558
2559 for (j = 0; j < k; j++) {
2560 printk(" %2.2X%2.2X%2.2X%2.2X",
2561 (unsigned)s[i + (j * 4)],
2562 (unsigned)s[i + (j * 4) + 1],
2563 (unsigned)s[i + (j * 4) + 2],
2564 (unsigned)s[i + (j * 4) + 3]);
2565 }
2566
2567 switch (m) {
2568 case 0:
2569 default:
2570 break;
2571 case 1:
2572 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2573 break;
2574 case 2:
2575 printk(" %2.2X%2.2X",
2576 (unsigned)s[i + (j * 4)],
2577 (unsigned)s[i + (j * 4) + 1]);
2578 break;
2579 case 3:
2580 printk(" %2.2X%2.2X%2.2X",
2581 (unsigned)s[i + (j * 4) + 1],
2582 (unsigned)s[i + (j * 4) + 2],
2583 (unsigned)s[i + (j * 4) + 3]);
2584 break;
2585 }
2586
2587 printk("\n");
2588 }
2589 }
2590
2591 /*
2592 * asc_prt_asc_scsi_q()
2593 */
2594 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2595 {
2596 ASC_SG_HEAD *sgp;
2597 int i;
2598
2599 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2600
2601 printk
2602 (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
2603 q->q2.target_ix, q->q1.target_lun, (ulong)q->q2.srb_ptr,
2604 q->q2.tag_code);
2605
2606 printk
2607 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2608 (ulong)le32_to_cpu(q->q1.data_addr),
2609 (ulong)le32_to_cpu(q->q1.data_cnt),
2610 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2611
2612 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2613 (ulong)q->cdbptr, q->q2.cdb_len,
2614 (ulong)q->sg_head, q->q1.sg_queue_cnt);
2615
2616 if (q->sg_head) {
2617 sgp = q->sg_head;
2618 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2619 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2620 sgp->queue_cnt);
2621 for (i = 0; i < sgp->entry_cnt; i++) {
2622 printk(" [%u]: addr 0x%lx, bytes %lu\n",
2623 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2624 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2625 }
2626
2627 }
2628 }
2629
2630 /*
2631 * asc_prt_asc_qdone_info()
2632 */
2633 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2634 {
2635 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2636 printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
2637 (ulong)q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
2638 q->d2.tag_code);
2639 printk
2640 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2641 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2642 }
2643
2644 /*
2645 * asc_prt_adv_sgblock()
2646 *
2647 * Display an ADV_SG_BLOCK structure.
2648 */
2649 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2650 {
2651 int i;
2652
2653 printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2654 (ulong)b, sgblockno);
2655 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
2656 b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2657 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2658 if (b->sg_ptr != 0)
2659 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2660 for (i = 0; i < b->sg_cnt; i++) {
2661 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2662 i, (ulong)b->sg_list[i].sg_addr,
2663 (ulong)b->sg_list[i].sg_count);
2664 }
2665 }
2666
2667 /*
2668 * asc_prt_adv_scsi_req_q()
2669 *
2670 * Display an ADV_SCSI_REQ_Q structure.
2671 */
2672 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2673 {
2674 int sg_blk_cnt;
2675 struct asc_sg_block *sg_ptr;
2676
2677 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2678
2679 printk(" target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
2680 q->target_id, q->target_lun, (ulong)q->srb_ptr, q->a_flag);
2681
2682 printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
2683 q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr);
2684
2685 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2686 (ulong)le32_to_cpu(q->data_cnt),
2687 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2688
2689 printk
2690 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2691 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2692
2693 printk(" sg_working_ix 0x%x, target_cmd %u\n",
2694 q->sg_working_ix, q->target_cmd);
2695
2696 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2697 (ulong)le32_to_cpu(q->scsiq_rptr),
2698 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2699
2700 /* Display the request's ADV_SG_BLOCK structures. */
2701 if (q->sg_list_ptr != NULL) {
2702 sg_blk_cnt = 0;
2703 while (1) {
2704 /*
2705 * 'sg_ptr' is a physical address. Convert it to a virtual
2706 * address by indexing 'sg_blk_cnt' into the virtual address
2707 * array 'sg_list_ptr'.
2708 *
2709 * XXX - Assumes all SG physical blocks are virtually contiguous.
2710 */
2711 sg_ptr =
2712 &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]);
2713 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2714 if (sg_ptr->sg_ptr == 0) {
2715 break;
2716 }
2717 sg_blk_cnt++;
2718 }
2719 }
2720 }
2721 #endif /* ADVANSYS_DEBUG */
2722
2723 /*
2724 * The advansys chip/microcode contains a 32-bit identifier for each command
2725 * known as the 'srb'. I don't know what it stands for. The driver used
2726 * to encode the scsi_cmnd pointer by calling virt_to_bus and retrieve it
2727 * with bus_to_virt. Now the driver keeps a per-host map of integers to
2728 * pointers. It auto-expands when full, unless it can't allocate memory.
2729 * Note that an srb of 0 is treated specially by the chip/firmware, hence
2730 * the return of i+1 in this routine, and the corresponding subtraction in
2731 * the inverse routine.
2732 */
2733 #define BAD_SRB 0
2734 static u32 advansys_ptr_to_srb(struct asc_dvc_var *asc_dvc, void *ptr)
2735 {
2736 int i;
2737 void **new_ptr;
2738
2739 for (i = 0; i < asc_dvc->ptr_map_count; i++) {
2740 if (!asc_dvc->ptr_map[i])
2741 goto out;
2742 }
2743
2744 if (asc_dvc->ptr_map_count == 0)
2745 asc_dvc->ptr_map_count = 1;
2746 else
2747 asc_dvc->ptr_map_count *= 2;
2748
2749 new_ptr = krealloc(asc_dvc->ptr_map,
2750 asc_dvc->ptr_map_count * sizeof(void *), GFP_ATOMIC);
2751 if (!new_ptr)
2752 return BAD_SRB;
2753 asc_dvc->ptr_map = new_ptr;
2754 out:
2755 ASC_DBG(3, "Putting ptr %p into array offset %d\n", ptr, i);
2756 asc_dvc->ptr_map[i] = ptr;
2757 return i + 1;
2758 }
2759
2760 static void * advansys_srb_to_ptr(struct asc_dvc_var *asc_dvc, u32 srb)
2761 {
2762 void *ptr;
2763
2764 srb--;
2765 if (srb >= asc_dvc->ptr_map_count) {
2766 printk("advansys: bad SRB %u, max %u\n", srb,
2767 asc_dvc->ptr_map_count);
2768 return NULL;
2769 }
2770 ptr = asc_dvc->ptr_map[srb];
2771 asc_dvc->ptr_map[srb] = NULL;
2772 ASC_DBG(3, "Returning ptr %p from array offset %d\n", ptr, srb);
2773 return ptr;
2774 }
2775
2776 /*
2777 * advansys_info()
2778 *
2779 * Return suitable for printing on the console with the argument
2780 * adapter's configuration information.
2781 *
2782 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2783 * otherwise the static 'info' array will be overrun.
2784 */
2785 static const char *advansys_info(struct Scsi_Host *shost)
2786 {
2787 static char info[ASC_INFO_SIZE];
2788 struct asc_board *boardp = shost_priv(shost);
2789 ASC_DVC_VAR *asc_dvc_varp;
2790 ADV_DVC_VAR *adv_dvc_varp;
2791 char *busname;
2792 char *widename = NULL;
2793
2794 if (ASC_NARROW_BOARD(boardp)) {
2795 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2796 ASC_DBG(1, "begin\n");
2797 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2798 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2799 ASC_IS_ISAPNP) {
2800 busname = "ISA PnP";
2801 } else {
2802 busname = "ISA";
2803 }
2804 sprintf(info,
2805 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2806 ASC_VERSION, busname,
2807 (ulong)shost->io_port,
2808 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2809 boardp->irq, shost->dma_channel);
2810 } else {
2811 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2812 busname = "VL";
2813 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2814 busname = "EISA";
2815 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2816 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2817 == ASC_IS_PCI_ULTRA) {
2818 busname = "PCI Ultra";
2819 } else {
2820 busname = "PCI";
2821 }
2822 } else {
2823 busname = "?";
2824 shost_printk(KERN_ERR, shost, "unknown bus "
2825 "type %d\n", asc_dvc_varp->bus_type);
2826 }
2827 sprintf(info,
2828 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2829 ASC_VERSION, busname, (ulong)shost->io_port,
2830 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2831 boardp->irq);
2832 }
2833 } else {
2834 /*
2835 * Wide Adapter Information
2836 *
2837 * Memory-mapped I/O is used instead of I/O space to access
2838 * the adapter, but display the I/O Port range. The Memory
2839 * I/O address is displayed through the driver /proc file.
2840 */
2841 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2842 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2843 widename = "Ultra-Wide";
2844 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2845 widename = "Ultra2-Wide";
2846 } else {
2847 widename = "Ultra3-Wide";
2848 }
2849 sprintf(info,
2850 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2851 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
2852 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
2853 }
2854 BUG_ON(strlen(info) >= ASC_INFO_SIZE);
2855 ASC_DBG(1, "end\n");
2856 return info;
2857 }
2858
2859 #ifdef CONFIG_PROC_FS
2860
2861 /*
2862 * asc_prt_board_devices()
2863 *
2864 * Print driver information for devices attached to the board.
2865 */
2866 static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost)
2867 {
2868 struct asc_board *boardp = shost_priv(shost);
2869 int chip_scsi_id;
2870 int i;
2871
2872 seq_printf(m,
2873 "\nDevice Information for AdvanSys SCSI Host %d:\n",
2874 shost->host_no);
2875
2876 if (ASC_NARROW_BOARD(boardp)) {
2877 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2878 } else {
2879 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
2880 }
2881
2882 seq_printf(m, "Target IDs Detected:");
2883 for (i = 0; i <= ADV_MAX_TID; i++) {
2884 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i))
2885 seq_printf(m, " %X,", i);
2886 }
2887 seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id);
2888 }
2889
2890 /*
2891 * Display Wide Board BIOS Information.
2892 */
2893 static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost)
2894 {
2895 struct asc_board *boardp = shost_priv(shost);
2896 ushort major, minor, letter;
2897
2898 seq_printf(m, "\nROM BIOS Version: ");
2899
2900 /*
2901 * If the BIOS saved a valid signature, then fill in
2902 * the BIOS code segment base address.
2903 */
2904 if (boardp->bios_signature != 0x55AA) {
2905 seq_printf(m, "Disabled or Pre-3.1\n");
2906 seq_printf(m,
2907 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
2908 seq_printf(m,
2909 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
2910 } else {
2911 major = (boardp->bios_version >> 12) & 0xF;
2912 minor = (boardp->bios_version >> 8) & 0xF;
2913 letter = (boardp->bios_version & 0xFF);
2914
2915 seq_printf(m, "%d.%d%c\n",
2916 major, minor,
2917 letter >= 26 ? '?' : letter + 'A');
2918 /*
2919 * Current available ROM BIOS release is 3.1I for UW
2920 * and 3.2I for U2W. This code doesn't differentiate
2921 * UW and U2W boards.
2922 */
2923 if (major < 3 || (major <= 3 && minor < 1) ||
2924 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
2925 seq_printf(m,
2926 "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
2927 seq_printf(m,
2928 "ftp://ftp.connectcom.net/pub\n");
2929 }
2930 }
2931 }
2932
2933 /*
2934 * Add serial number to information bar if signature AAh
2935 * is found in at bit 15-9 (7 bits) of word 1.
2936 *
2937 * Serial Number consists fo 12 alpha-numeric digits.
2938 *
2939 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
2940 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
2941 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
2942 * 5 - Product revision (A-J) Word0: " "
2943 *
2944 * Signature Word1: 15-9 (7 bits)
2945 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
2946 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
2947 *
2948 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
2949 *
2950 * Note 1: Only production cards will have a serial number.
2951 *
2952 * Note 2: Signature is most significant 7 bits (0xFE).
2953 *
2954 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
2955 */
2956 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
2957 {
2958 ushort w, num;
2959
2960 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
2961 return ASC_FALSE;
2962 } else {
2963 /*
2964 * First word - 6 digits.
2965 */
2966 w = serialnum[0];
2967
2968 /* Product type - 1st digit. */
2969 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
2970 /* Product type is P=Prototype */
2971 *cp += 0x8;
2972 }
2973 cp++;
2974
2975 /* Manufacturing location - 2nd digit. */
2976 *cp++ = 'A' + ((w & 0x1C00) >> 10);
2977
2978 /* Product ID - 3rd, 4th digits. */
2979 num = w & 0x3FF;
2980 *cp++ = '0' + (num / 100);
2981 num %= 100;
2982 *cp++ = '0' + (num / 10);
2983
2984 /* Product revision - 5th digit. */
2985 *cp++ = 'A' + (num % 10);
2986
2987 /*
2988 * Second word
2989 */
2990 w = serialnum[1];
2991
2992 /*
2993 * Year - 6th digit.
2994 *
2995 * If bit 15 of third word is set, then the
2996 * last digit of the year is greater than 7.
2997 */
2998 if (serialnum[2] & 0x8000) {
2999 *cp++ = '8' + ((w & 0x1C0) >> 6);
3000 } else {
3001 *cp++ = '0' + ((w & 0x1C0) >> 6);
3002 }
3003
3004 /* Week of year - 7th, 8th digits. */
3005 num = w & 0x003F;
3006 *cp++ = '0' + num / 10;
3007 num %= 10;
3008 *cp++ = '0' + num;
3009
3010 /*
3011 * Third word
3012 */
3013 w = serialnum[2] & 0x7FFF;
3014
3015 /* Serial number - 9th digit. */
3016 *cp++ = 'A' + (w / 1000);
3017
3018 /* 10th, 11th, 12th digits. */
3019 num = w % 1000;
3020 *cp++ = '0' + num / 100;
3021 num %= 100;
3022 *cp++ = '0' + num / 10;
3023 num %= 10;
3024 *cp++ = '0' + num;
3025
3026 *cp = '\0'; /* Null Terminate the string. */
3027 return ASC_TRUE;
3028 }
3029 }
3030
3031 /*
3032 * asc_prt_asc_board_eeprom()
3033 *
3034 * Print board EEPROM configuration.
3035 */
3036 static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
3037 {
3038 struct asc_board *boardp = shost_priv(shost);
3039 ASC_DVC_VAR *asc_dvc_varp;
3040 ASCEEP_CONFIG *ep;
3041 int i;
3042 #ifdef CONFIG_ISA
3043 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
3044 #endif /* CONFIG_ISA */
3045 uchar serialstr[13];
3046
3047 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
3048 ep = &boardp->eep_config.asc_eep;
3049
3050 seq_printf(m,
3051 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3052 shost->host_no);
3053
3054 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
3055 == ASC_TRUE)
3056 seq_printf(m, " Serial Number: %s\n", serialstr);
3057 else if (ep->adapter_info[5] == 0xBB)
3058 seq_printf(m,
3059 " Default Settings Used for EEPROM-less Adapter.\n");
3060 else
3061 seq_printf(m,
3062 " Serial Number Signature Not Present.\n");
3063
3064 seq_printf(m,
3065 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3066 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
3067 ep->max_tag_qng);
3068
3069 seq_printf(m,
3070 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
3071
3072 seq_printf(m, " Target ID: ");
3073 for (i = 0; i <= ASC_MAX_TID; i++)
3074 seq_printf(m, " %d", i);
3075 seq_printf(m, "\n");
3076
3077 seq_printf(m, " Disconnects: ");
3078 for (i = 0; i <= ASC_MAX_TID; i++)
3079 seq_printf(m, " %c",
3080 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3081 seq_printf(m, "\n");
3082
3083 seq_printf(m, " Command Queuing: ");
3084 for (i = 0; i <= ASC_MAX_TID; i++)
3085 seq_printf(m, " %c",
3086 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3087 seq_printf(m, "\n");
3088
3089 seq_printf(m, " Start Motor: ");
3090 for (i = 0; i <= ASC_MAX_TID; i++)
3091 seq_printf(m, " %c",
3092 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3093 seq_printf(m, "\n");
3094
3095 seq_printf(m, " Synchronous Transfer:");
3096 for (i = 0; i <= ASC_MAX_TID; i++)
3097 seq_printf(m, " %c",
3098 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3099 seq_printf(m, "\n");
3100
3101 #ifdef CONFIG_ISA
3102 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
3103 seq_printf(m,
3104 " Host ISA DMA speed: %d MB/S\n",
3105 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
3106 }
3107 #endif /* CONFIG_ISA */
3108 }
3109
3110 /*
3111 * asc_prt_adv_board_eeprom()
3112 *
3113 * Print board EEPROM configuration.
3114 */
3115 static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
3116 {
3117 struct asc_board *boardp = shost_priv(shost);
3118 ADV_DVC_VAR *adv_dvc_varp;
3119 int i;
3120 char *termstr;
3121 uchar serialstr[13];
3122 ADVEEP_3550_CONFIG *ep_3550 = NULL;
3123 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3124 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3125 ushort word;
3126 ushort *wordp;
3127 ushort sdtr_speed = 0;
3128
3129 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3130 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3131 ep_3550 = &boardp->eep_config.adv_3550_eep;
3132 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3133 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
3134 } else {
3135 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
3136 }
3137
3138 seq_printf(m,
3139 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3140 shost->host_no);
3141
3142 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3143 wordp = &ep_3550->serial_number_word1;
3144 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3145 wordp = &ep_38C0800->serial_number_word1;
3146 } else {
3147 wordp = &ep_38C1600->serial_number_word1;
3148 }
3149
3150 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE)
3151 seq_printf(m, " Serial Number: %s\n", serialstr);
3152 else
3153 seq_printf(m, " Serial Number Signature Not Present.\n");
3154
3155 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3156 seq_printf(m,
3157 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3158 ep_3550->adapter_scsi_id,
3159 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3160 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3161 seq_printf(m,
3162 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3163 ep_38C0800->adapter_scsi_id,
3164 ep_38C0800->max_host_qng,
3165 ep_38C0800->max_dvc_qng);
3166 else
3167 seq_printf(m,
3168 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3169 ep_38C1600->adapter_scsi_id,
3170 ep_38C1600->max_host_qng,
3171 ep_38C1600->max_dvc_qng);
3172 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3173 word = ep_3550->termination;
3174 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3175 word = ep_38C0800->termination_lvd;
3176 } else {
3177 word = ep_38C1600->termination_lvd;
3178 }
3179 switch (word) {
3180 case 1:
3181 termstr = "Low Off/High Off";
3182 break;
3183 case 2:
3184 termstr = "Low Off/High On";
3185 break;
3186 case 3:
3187 termstr = "Low On/High On";
3188 break;
3189 default:
3190 case 0:
3191 termstr = "Automatic";
3192 break;
3193 }
3194
3195 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3196 seq_printf(m,
3197 " termination: %u (%s), bios_ctrl: 0x%x\n",
3198 ep_3550->termination, termstr,
3199 ep_3550->bios_ctrl);
3200 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3201 seq_printf(m,
3202 " termination: %u (%s), bios_ctrl: 0x%x\n",
3203 ep_38C0800->termination_lvd, termstr,
3204 ep_38C0800->bios_ctrl);
3205 else
3206 seq_printf(m,
3207 " termination: %u (%s), bios_ctrl: 0x%x\n",
3208 ep_38C1600->termination_lvd, termstr,
3209 ep_38C1600->bios_ctrl);
3210
3211 seq_printf(m, " Target ID: ");
3212 for (i = 0; i <= ADV_MAX_TID; i++)
3213 seq_printf(m, " %X", i);
3214 seq_printf(m, "\n");
3215
3216 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3217 word = ep_3550->disc_enable;
3218 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3219 word = ep_38C0800->disc_enable;
3220 } else {
3221 word = ep_38C1600->disc_enable;
3222 }
3223 seq_printf(m, " Disconnects: ");
3224 for (i = 0; i <= ADV_MAX_TID; i++)
3225 seq_printf(m, " %c",
3226 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3227 seq_printf(m, "\n");
3228
3229 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3230 word = ep_3550->tagqng_able;
3231 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3232 word = ep_38C0800->tagqng_able;
3233 } else {
3234 word = ep_38C1600->tagqng_able;
3235 }
3236 seq_printf(m, " Command Queuing: ");
3237 for (i = 0; i <= ADV_MAX_TID; i++)
3238 seq_printf(m, " %c",
3239 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3240 seq_printf(m, "\n");
3241
3242 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3243 word = ep_3550->start_motor;
3244 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3245 word = ep_38C0800->start_motor;
3246 } else {
3247 word = ep_38C1600->start_motor;
3248 }
3249 seq_printf(m, " Start Motor: ");
3250 for (i = 0; i <= ADV_MAX_TID; i++)
3251 seq_printf(m, " %c",
3252 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3253 seq_printf(m, "\n");
3254
3255 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3256 seq_printf(m, " Synchronous Transfer:");
3257 for (i = 0; i <= ADV_MAX_TID; i++)
3258 seq_printf(m, " %c",
3259 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3260 'Y' : 'N');
3261 seq_printf(m, "\n");
3262 }
3263
3264 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3265 seq_printf(m, " Ultra Transfer: ");
3266 for (i = 0; i <= ADV_MAX_TID; i++)
3267 seq_printf(m, " %c",
3268 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i))
3269 ? 'Y' : 'N');
3270 seq_printf(m, "\n");
3271 }
3272
3273 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3274 word = ep_3550->wdtr_able;
3275 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3276 word = ep_38C0800->wdtr_able;
3277 } else {
3278 word = ep_38C1600->wdtr_able;
3279 }
3280 seq_printf(m, " Wide Transfer: ");
3281 for (i = 0; i <= ADV_MAX_TID; i++)
3282 seq_printf(m, " %c",
3283 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3284 seq_printf(m, "\n");
3285
3286 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3287 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3288 seq_printf(m,
3289 " Synchronous Transfer Speed (Mhz):\n ");
3290 for (i = 0; i <= ADV_MAX_TID; i++) {
3291 char *speed_str;
3292
3293 if (i == 0) {
3294 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3295 } else if (i == 4) {
3296 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3297 } else if (i == 8) {
3298 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3299 } else if (i == 12) {
3300 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3301 }
3302 switch (sdtr_speed & ADV_MAX_TID) {
3303 case 0:
3304 speed_str = "Off";
3305 break;
3306 case 1:
3307 speed_str = " 5";
3308 break;
3309 case 2:
3310 speed_str = " 10";
3311 break;
3312 case 3:
3313 speed_str = " 20";
3314 break;
3315 case 4:
3316 speed_str = " 40";
3317 break;
3318 case 5:
3319 speed_str = " 80";
3320 break;
3321 default:
3322 speed_str = "Unk";
3323 break;
3324 }
3325 seq_printf(m, "%X:%s ", i, speed_str);
3326 if (i == 7)
3327 seq_printf(m, "\n ");
3328 sdtr_speed >>= 4;
3329 }
3330 seq_printf(m, "\n");
3331 }
3332 }
3333
3334 /*
3335 * asc_prt_driver_conf()
3336 */
3337 static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost)
3338 {
3339 struct asc_board *boardp = shost_priv(shost);
3340 int chip_scsi_id;
3341
3342 seq_printf(m,
3343 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3344 shost->host_no);
3345
3346 seq_printf(m,
3347 " host_busy %u, max_id %u, max_lun %llu, max_channel %u\n",
3348 atomic_read(&shost->host_busy), shost->max_id,
3349 shost->max_lun, shost->max_channel);
3350
3351 seq_printf(m,
3352 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3353 shost->unique_id, shost->can_queue, shost->this_id,
3354 shost->sg_tablesize, shost->cmd_per_lun);
3355
3356 seq_printf(m,
3357 " unchecked_isa_dma %d, use_clustering %d\n",
3358 shost->unchecked_isa_dma, shost->use_clustering);
3359
3360 seq_printf(m,
3361 " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n",
3362 boardp->flags, boardp->last_reset, jiffies,
3363 boardp->asc_n_io_port);
3364
3365 seq_printf(m, " io_port 0x%lx\n", shost->io_port);
3366
3367 if (ASC_NARROW_BOARD(boardp)) {
3368 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3369 } else {
3370 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3371 }
3372 }
3373
3374 /*
3375 * asc_prt_asc_board_info()
3376 *
3377 * Print dynamic board configuration information.
3378 */
3379 static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost)
3380 {
3381 struct asc_board *boardp = shost_priv(shost);
3382 int chip_scsi_id;
3383 ASC_DVC_VAR *v;
3384 ASC_DVC_CFG *c;
3385 int i;
3386 int renegotiate = 0;
3387
3388 v = &boardp->dvc_var.asc_dvc_var;
3389 c = &boardp->dvc_cfg.asc_dvc_cfg;
3390 chip_scsi_id = c->chip_scsi_id;
3391
3392 seq_printf(m,
3393 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3394 shost->host_no);
3395
3396 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3397 "mcode_version 0x%x, err_code %u\n",
3398 c->chip_version, c->mcode_date, c->mcode_version,
3399 v->err_code);
3400
3401 /* Current number of commands waiting for the host. */
3402 seq_printf(m,
3403 " Total Command Pending: %d\n", v->cur_total_qng);
3404
3405 seq_printf(m, " Command Queuing:");
3406 for (i = 0; i <= ASC_MAX_TID; i++) {
3407 if ((chip_scsi_id == i) ||
3408 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3409 continue;
3410 }
3411 seq_printf(m, " %X:%c",
3412 i,
3413 (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3414 }
3415 seq_printf(m, "\n");
3416
3417 /* Current number of commands waiting for a device. */
3418 seq_printf(m, " Command Queue Pending:");
3419 for (i = 0; i <= ASC_MAX_TID; i++) {
3420 if ((chip_scsi_id == i) ||
3421 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3422 continue;
3423 }
3424 seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
3425 }
3426 seq_printf(m, "\n");
3427
3428 /* Current limit on number of commands that can be sent to a device. */
3429 seq_printf(m, " Command Queue Limit:");
3430 for (i = 0; i <= ASC_MAX_TID; i++) {
3431 if ((chip_scsi_id == i) ||
3432 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3433 continue;
3434 }
3435 seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
3436 }
3437 seq_printf(m, "\n");
3438
3439 /* Indicate whether the device has returned queue full status. */
3440 seq_printf(m, " Command Queue Full:");
3441 for (i = 0; i <= ASC_MAX_TID; i++) {
3442 if ((chip_scsi_id == i) ||
3443 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3444 continue;
3445 }
3446 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i))
3447 seq_printf(m, " %X:Y-%d",
3448 i, boardp->queue_full_cnt[i]);
3449 else
3450 seq_printf(m, " %X:N", i);
3451 }
3452 seq_printf(m, "\n");
3453
3454 seq_printf(m, " Synchronous Transfer:");
3455 for (i = 0; i <= ASC_MAX_TID; i++) {
3456 if ((chip_scsi_id == i) ||
3457 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3458 continue;
3459 }
3460 seq_printf(m, " %X:%c",
3461 i,
3462 (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3463 }
3464 seq_printf(m, "\n");
3465
3466 for (i = 0; i <= ASC_MAX_TID; i++) {
3467 uchar syn_period_ix;
3468
3469 if ((chip_scsi_id == i) ||
3470 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3471 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3472 continue;
3473 }
3474
3475 seq_printf(m, " %X:", i);
3476
3477 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3478 seq_printf(m, " Asynchronous");
3479 } else {
3480 syn_period_ix =
3481 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3482 1);
3483
3484 seq_printf(m,
3485 " Transfer Period Factor: %d (%d.%d Mhz),",
3486 v->sdtr_period_tbl[syn_period_ix],
3487 250 / v->sdtr_period_tbl[syn_period_ix],
3488 ASC_TENTHS(250,
3489 v->sdtr_period_tbl[syn_period_ix]));
3490
3491 seq_printf(m, " REQ/ACK Offset: %d",
3492 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3493 }
3494
3495 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3496 seq_printf(m, "*\n");
3497 renegotiate = 1;
3498 } else {
3499 seq_printf(m, "\n");
3500 }
3501 }
3502
3503 if (renegotiate) {
3504 seq_printf(m,
3505 " * = Re-negotiation pending before next command.\n");
3506 }
3507 }
3508
3509 /*
3510 * asc_prt_adv_board_info()
3511 *
3512 * Print dynamic board configuration information.
3513 */
3514 static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost)
3515 {
3516 struct asc_board *boardp = shost_priv(shost);
3517 int i;
3518 ADV_DVC_VAR *v;
3519 ADV_DVC_CFG *c;
3520 AdvPortAddr iop_base;
3521 ushort chip_scsi_id;
3522 ushort lramword;
3523 uchar lrambyte;
3524 ushort tagqng_able;
3525 ushort sdtr_able, wdtr_able;
3526 ushort wdtr_done, sdtr_done;
3527 ushort period = 0;
3528 int renegotiate = 0;
3529
3530 v = &boardp->dvc_var.adv_dvc_var;
3531 c = &boardp->dvc_cfg.adv_dvc_cfg;
3532 iop_base = v->iop_base;
3533 chip_scsi_id = v->chip_scsi_id;
3534
3535 seq_printf(m,
3536 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3537 shost->host_no);
3538
3539 seq_printf(m,
3540 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3541 (unsigned long)v->iop_base,
3542 AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT,
3543 v->err_code);
3544
3545 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3546 "mcode_version 0x%x\n", c->chip_version,
3547 c->mcode_date, c->mcode_version);
3548
3549 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3550 seq_printf(m, " Queuing Enabled:");
3551 for (i = 0; i <= ADV_MAX_TID; i++) {
3552 if ((chip_scsi_id == i) ||
3553 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3554 continue;
3555 }
3556
3557 seq_printf(m, " %X:%c",
3558 i,
3559 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3560 }
3561 seq_printf(m, "\n");
3562
3563 seq_printf(m, " Queue Limit:");
3564 for (i = 0; i <= ADV_MAX_TID; i++) {
3565 if ((chip_scsi_id == i) ||
3566 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3567 continue;
3568 }
3569
3570 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3571 lrambyte);
3572
3573 seq_printf(m, " %X:%d", i, lrambyte);
3574 }
3575 seq_printf(m, "\n");
3576
3577 seq_printf(m, " Command Pending:");
3578 for (i = 0; i <= ADV_MAX_TID; i++) {
3579 if ((chip_scsi_id == i) ||
3580 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3581 continue;
3582 }
3583
3584 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3585 lrambyte);
3586
3587 seq_printf(m, " %X:%d", i, lrambyte);
3588 }
3589 seq_printf(m, "\n");
3590
3591 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
3592 seq_printf(m, " Wide Enabled:");
3593 for (i = 0; i <= ADV_MAX_TID; i++) {
3594 if ((chip_scsi_id == i) ||
3595 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3596 continue;
3597 }
3598
3599 seq_printf(m, " %X:%c",
3600 i,
3601 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3602 }
3603 seq_printf(m, "\n");
3604
3605 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
3606 seq_printf(m, " Transfer Bit Width:");
3607 for (i = 0; i <= ADV_MAX_TID; i++) {
3608 if ((chip_scsi_id == i) ||
3609 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3610 continue;
3611 }
3612
3613 AdvReadWordLram(iop_base,
3614 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3615 lramword);
3616
3617 seq_printf(m, " %X:%d",
3618 i, (lramword & 0x8000) ? 16 : 8);
3619
3620 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3621 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3622 seq_printf(m, "*");
3623 renegotiate = 1;
3624 }
3625 }
3626 seq_printf(m, "\n");
3627
3628 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
3629 seq_printf(m, " Synchronous Enabled:");
3630 for (i = 0; i <= ADV_MAX_TID; i++) {
3631 if ((chip_scsi_id == i) ||
3632 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3633 continue;
3634 }
3635
3636 seq_printf(m, " %X:%c",
3637 i,
3638 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3639 }
3640 seq_printf(m, "\n");
3641
3642 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3643 for (i = 0; i <= ADV_MAX_TID; i++) {
3644
3645 AdvReadWordLram(iop_base,
3646 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3647 lramword);
3648 lramword &= ~0x8000;
3649
3650 if ((chip_scsi_id == i) ||
3651 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3652 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3653 continue;
3654 }
3655
3656 seq_printf(m, " %X:", i);
3657
3658 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
3659 seq_printf(m, " Asynchronous");
3660 } else {
3661 seq_printf(m, " Transfer Period Factor: ");
3662
3663 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
3664 seq_printf(m, "9 (80.0 Mhz),");
3665 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
3666 seq_printf(m, "10 (40.0 Mhz),");
3667 } else { /* 20 Mhz or below. */
3668
3669 period = (((lramword >> 8) * 25) + 50) / 4;
3670
3671 if (period == 0) { /* Should never happen. */
3672 seq_printf(m, "%d (? Mhz), ", period);
3673 } else {
3674 seq_printf(m,
3675 "%d (%d.%d Mhz),",
3676 period, 250 / period,
3677 ASC_TENTHS(250, period));
3678 }
3679 }
3680
3681 seq_printf(m, " REQ/ACK Offset: %d",
3682 lramword & 0x1F);
3683 }
3684
3685 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3686 seq_printf(m, "*\n");
3687 renegotiate = 1;
3688 } else {
3689 seq_printf(m, "\n");
3690 }
3691 }
3692
3693 if (renegotiate) {
3694 seq_printf(m,
3695 " * = Re-negotiation pending before next command.\n");
3696 }
3697 }
3698
3699 #ifdef ADVANSYS_STATS
3700 /*
3701 * asc_prt_board_stats()
3702 */
3703 static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost)
3704 {
3705 struct asc_board *boardp = shost_priv(shost);
3706 struct asc_stats *s = &boardp->asc_stats;
3707
3708 seq_printf(m,
3709 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
3710 shost->host_no);
3711
3712 seq_printf(m,
3713 " queuecommand %u, reset %u, biosparam %u, interrupt %u\n",
3714 s->queuecommand, s->reset, s->biosparam,
3715 s->interrupt);
3716
3717 seq_printf(m,
3718 " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n",
3719 s->callback, s->done, s->build_error,
3720 s->adv_build_noreq, s->adv_build_nosg);
3721
3722 seq_printf(m,
3723 " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n",
3724 s->exe_noerror, s->exe_busy, s->exe_error,
3725 s->exe_unknown);
3726
3727 /*
3728 * Display data transfer statistics.
3729 */
3730 if (s->xfer_cnt > 0) {
3731 seq_printf(m, " xfer_cnt %u, xfer_elem %u, ",
3732 s->xfer_cnt, s->xfer_elem);
3733
3734 seq_printf(m, "xfer_bytes %u.%01u kb\n",
3735 s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
3736
3737 /* Scatter gather transfer statistics */
3738 seq_printf(m, " avg_num_elem %u.%01u, ",
3739 s->xfer_elem / s->xfer_cnt,
3740 ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
3741
3742 seq_printf(m, "avg_elem_size %u.%01u kb, ",
3743 (s->xfer_sect / 2) / s->xfer_elem,
3744 ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
3745
3746 seq_printf(m, "avg_xfer_size %u.%01u kb\n",
3747 (s->xfer_sect / 2) / s->xfer_cnt,
3748 ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
3749 }
3750 }
3751 #endif /* ADVANSYS_STATS */
3752
3753 /*
3754 * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...}
3755 *
3756 * m: seq_file to print into
3757 * shost: Scsi_Host
3758 *
3759 * Return the number of bytes read from or written to a
3760 * /proc/scsi/advansys/[0...] file.
3761 */
3762 static int
3763 advansys_show_info(struct seq_file *m, struct Scsi_Host *shost)
3764 {
3765 struct asc_board *boardp = shost_priv(shost);
3766
3767 ASC_DBG(1, "begin\n");
3768
3769 /*
3770 * User read of /proc/scsi/advansys/[0...] file.
3771 */
3772
3773 /*
3774 * Get board configuration information.
3775 *
3776 * advansys_info() returns the board string from its own static buffer.
3777 */
3778 /* Copy board information. */
3779 seq_printf(m, "%s\n", (char *)advansys_info(shost));
3780 /*
3781 * Display Wide Board BIOS Information.
3782 */
3783 if (!ASC_NARROW_BOARD(boardp))
3784 asc_prt_adv_bios(m, shost);
3785
3786 /*
3787 * Display driver information for each device attached to the board.
3788 */
3789 asc_prt_board_devices(m, shost);
3790
3791 /*
3792 * Display EEPROM configuration for the board.
3793 */
3794 if (ASC_NARROW_BOARD(boardp))
3795 asc_prt_asc_board_eeprom(m, shost);
3796 else
3797 asc_prt_adv_board_eeprom(m, shost);
3798
3799 /*
3800 * Display driver configuration and information for the board.
3801 */
3802 asc_prt_driver_conf(m, shost);
3803
3804 #ifdef ADVANSYS_STATS
3805 /*
3806 * Display driver statistics for the board.
3807 */
3808 asc_prt_board_stats(m, shost);
3809 #endif /* ADVANSYS_STATS */
3810
3811 /*
3812 * Display Asc Library dynamic configuration information
3813 * for the board.
3814 */
3815 if (ASC_NARROW_BOARD(boardp))
3816 asc_prt_asc_board_info(m, shost);
3817 else
3818 asc_prt_adv_board_info(m, shost);
3819 return 0;
3820 }
3821 #endif /* CONFIG_PROC_FS */
3822
3823 static void asc_scsi_done(struct scsi_cmnd *scp)
3824 {
3825 scsi_dma_unmap(scp);
3826 ASC_STATS(scp->device->host, done);
3827 scp->scsi_done(scp);
3828 }
3829
3830 static void AscSetBank(PortAddr iop_base, uchar bank)
3831 {
3832 uchar val;
3833
3834 val = AscGetChipControl(iop_base) &
3835 (~
3836 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
3837 CC_CHIP_RESET));
3838 if (bank == 1) {
3839 val |= CC_BANK_ONE;
3840 } else if (bank == 2) {
3841 val |= CC_DIAG | CC_BANK_ONE;
3842 } else {
3843 val &= ~CC_BANK_ONE;
3844 }
3845 AscSetChipControl(iop_base, val);
3846 }
3847
3848 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
3849 {
3850 AscSetBank(iop_base, 1);
3851 AscWriteChipIH(iop_base, ins_code);
3852 AscSetBank(iop_base, 0);
3853 }
3854
3855 static int AscStartChip(PortAddr iop_base)
3856 {
3857 AscSetChipControl(iop_base, 0);
3858 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3859 return (0);
3860 }
3861 return (1);
3862 }
3863
3864 static int AscStopChip(PortAddr iop_base)
3865 {
3866 uchar cc_val;
3867
3868 cc_val =
3869 AscGetChipControl(iop_base) &
3870 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
3871 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
3872 AscSetChipIH(iop_base, INS_HALT);
3873 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3874 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
3875 return (0);
3876 }
3877 return (1);
3878 }
3879
3880 static int AscIsChipHalted(PortAddr iop_base)
3881 {
3882 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3883 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
3884 return (1);
3885 }
3886 }
3887 return (0);
3888 }
3889
3890 static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
3891 {
3892 PortAddr iop_base;
3893 int i = 10;
3894
3895 iop_base = asc_dvc->iop_base;
3896 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
3897 && (i-- > 0)) {
3898 mdelay(100);
3899 }
3900 AscStopChip(iop_base);
3901 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
3902 udelay(60);
3903 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3904 AscSetChipIH(iop_base, INS_HALT);
3905 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
3906 AscSetChipControl(iop_base, CC_HALT);
3907 mdelay(200);
3908 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
3909 AscSetChipStatus(iop_base, 0);
3910 return (AscIsChipHalted(iop_base));
3911 }
3912
3913 static int AscFindSignature(PortAddr iop_base)
3914 {
3915 ushort sig_word;
3916
3917 ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
3918 iop_base, AscGetChipSignatureByte(iop_base));
3919 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
3920 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
3921 iop_base, AscGetChipSignatureWord(iop_base));
3922 sig_word = AscGetChipSignatureWord(iop_base);
3923 if ((sig_word == (ushort)ASC_1000_ID0W) ||
3924 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
3925 return (1);
3926 }
3927 }
3928 return (0);
3929 }
3930
3931 static void AscEnableInterrupt(PortAddr iop_base)
3932 {
3933 ushort cfg;
3934
3935 cfg = AscGetChipCfgLsw(iop_base);
3936 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
3937 }
3938
3939 static void AscDisableInterrupt(PortAddr iop_base)
3940 {
3941 ushort cfg;
3942
3943 cfg = AscGetChipCfgLsw(iop_base);
3944 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
3945 }
3946
3947 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
3948 {
3949 unsigned char byte_data;
3950 unsigned short word_data;
3951
3952 if (isodd_word(addr)) {
3953 AscSetChipLramAddr(iop_base, addr - 1);
3954 word_data = AscGetChipLramData(iop_base);
3955 byte_data = (word_data >> 8) & 0xFF;
3956 } else {
3957 AscSetChipLramAddr(iop_base, addr);
3958 word_data = AscGetChipLramData(iop_base);
3959 byte_data = word_data & 0xFF;
3960 }
3961 return byte_data;
3962 }
3963
3964 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
3965 {
3966 ushort word_data;
3967
3968 AscSetChipLramAddr(iop_base, addr);
3969 word_data = AscGetChipLramData(iop_base);
3970 return (word_data);
3971 }
3972
3973 #if CC_VERY_LONG_SG_LIST
3974 static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr)
3975 {
3976 ushort val_low, val_high;
3977 ASC_DCNT dword_data;
3978
3979 AscSetChipLramAddr(iop_base, addr);
3980 val_low = AscGetChipLramData(iop_base);
3981 val_high = AscGetChipLramData(iop_base);
3982 dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
3983 return (dword_data);
3984 }
3985 #endif /* CC_VERY_LONG_SG_LIST */
3986
3987 static void
3988 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
3989 {
3990 int i;
3991
3992 AscSetChipLramAddr(iop_base, s_addr);
3993 for (i = 0; i < words; i++) {
3994 AscSetChipLramData(iop_base, set_wval);
3995 }
3996 }
3997
3998 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
3999 {
4000 AscSetChipLramAddr(iop_base, addr);
4001 AscSetChipLramData(iop_base, word_val);
4002 }
4003
4004 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
4005 {
4006 ushort word_data;
4007
4008 if (isodd_word(addr)) {
4009 addr--;
4010 word_data = AscReadLramWord(iop_base, addr);
4011 word_data &= 0x00FF;
4012 word_data |= (((ushort)byte_val << 8) & 0xFF00);
4013 } else {
4014 word_data = AscReadLramWord(iop_base, addr);
4015 word_data &= 0xFF00;
4016 word_data |= ((ushort)byte_val & 0x00FF);
4017 }
4018 AscWriteLramWord(iop_base, addr, word_data);
4019 }
4020
4021 /*
4022 * Copy 2 bytes to LRAM.
4023 *
4024 * The source data is assumed to be in little-endian order in memory
4025 * and is maintained in little-endian order when written to LRAM.
4026 */
4027 static void
4028 AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
4029 const uchar *s_buffer, int words)
4030 {
4031 int i;
4032
4033 AscSetChipLramAddr(iop_base, s_addr);
4034 for (i = 0; i < 2 * words; i += 2) {
4035 /*
4036 * On a little-endian system the second argument below
4037 * produces a little-endian ushort which is written to
4038 * LRAM in little-endian order. On a big-endian system
4039 * the second argument produces a big-endian ushort which
4040 * is "transparently" byte-swapped by outpw() and written
4041 * in little-endian order to LRAM.
4042 */
4043 outpw(iop_base + IOP_RAM_DATA,
4044 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
4045 }
4046 }
4047
4048 /*
4049 * Copy 4 bytes to LRAM.
4050 *
4051 * The source data is assumed to be in little-endian order in memory
4052 * and is maintained in little-endian order when written to LRAM.
4053 */
4054 static void
4055 AscMemDWordCopyPtrToLram(PortAddr iop_base,
4056 ushort s_addr, uchar *s_buffer, int dwords)
4057 {
4058 int i;
4059
4060 AscSetChipLramAddr(iop_base, s_addr);
4061 for (i = 0; i < 4 * dwords; i += 4) {
4062 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
4063 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
4064 }
4065 }
4066
4067 /*
4068 * Copy 2 bytes from LRAM.
4069 *
4070 * The source data is assumed to be in little-endian order in LRAM
4071 * and is maintained in little-endian order when written to memory.
4072 */
4073 static void
4074 AscMemWordCopyPtrFromLram(PortAddr iop_base,
4075 ushort s_addr, uchar *d_buffer, int words)
4076 {
4077 int i;
4078 ushort word;
4079
4080 AscSetChipLramAddr(iop_base, s_addr);
4081 for (i = 0; i < 2 * words; i += 2) {
4082 word = inpw(iop_base + IOP_RAM_DATA);
4083 d_buffer[i] = word & 0xff;
4084 d_buffer[i + 1] = (word >> 8) & 0xff;
4085 }
4086 }
4087
4088 static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
4089 {
4090 ASC_DCNT sum;
4091 int i;
4092
4093 sum = 0L;
4094 for (i = 0; i < words; i++, s_addr += 2) {
4095 sum += AscReadLramWord(iop_base, s_addr);
4096 }
4097 return (sum);
4098 }
4099
4100 static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
4101 {
4102 uchar i;
4103 ushort s_addr;
4104 PortAddr iop_base;
4105 ushort warn_code;
4106
4107 iop_base = asc_dvc->iop_base;
4108 warn_code = 0;
4109 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
4110 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
4111 64) >> 1));
4112 i = ASC_MIN_ACTIVE_QNO;
4113 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
4114 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4115 (uchar)(i + 1));
4116 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4117 (uchar)(asc_dvc->max_total_qng));
4118 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4119 (uchar)i);
4120 i++;
4121 s_addr += ASC_QBLK_SIZE;
4122 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4123 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4124 (uchar)(i + 1));
4125 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4126 (uchar)(i - 1));
4127 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4128 (uchar)i);
4129 }
4130 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4131 (uchar)ASC_QLINK_END);
4132 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4133 (uchar)(asc_dvc->max_total_qng - 1));
4134 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4135 (uchar)asc_dvc->max_total_qng);
4136 i++;
4137 s_addr += ASC_QBLK_SIZE;
4138 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4139 i++, s_addr += ASC_QBLK_SIZE) {
4140 AscWriteLramByte(iop_base,
4141 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4142 AscWriteLramByte(iop_base,
4143 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4144 AscWriteLramByte(iop_base,
4145 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
4146 }
4147 return warn_code;
4148 }
4149
4150 static ASC_DCNT
4151 AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
4152 const uchar *mcode_buf, ushort mcode_size)
4153 {
4154 ASC_DCNT chksum;
4155 ushort mcode_word_size;
4156 ushort mcode_chksum;
4157
4158 /* Write the microcode buffer starting at LRAM address 0. */
4159 mcode_word_size = (ushort)(mcode_size >> 1);
4160 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4161 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
4162
4163 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
4164 ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
4165 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4166 (ushort)ASC_CODE_SEC_BEG,
4167 (ushort)((mcode_size -
4168 s_addr - (ushort)
4169 ASC_CODE_SEC_BEG) /
4170 2));
4171 ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
4172 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4173 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
4174 return chksum;
4175 }
4176
4177 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
4178 {
4179 PortAddr iop_base;
4180 int i;
4181 ushort lram_addr;
4182
4183 iop_base = asc_dvc->iop_base;
4184 AscPutRiscVarFreeQHead(iop_base, 1);
4185 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4186 AscPutVarFreeQHead(iop_base, 1);
4187 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4188 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
4189 (uchar)((int)asc_dvc->max_total_qng + 1));
4190 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
4191 (uchar)((int)asc_dvc->max_total_qng + 2));
4192 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
4193 asc_dvc->max_total_qng);
4194 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
4195 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
4196 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
4197 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
4198 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
4199 AscPutQDoneInProgress(iop_base, 0);
4200 lram_addr = ASC_QADR_BEG;
4201 for (i = 0; i < 32; i++, lram_addr += 2) {
4202 AscWriteLramWord(iop_base, lram_addr, 0);
4203 }
4204 }
4205
4206 static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
4207 {
4208 int i;
4209 ushort warn_code;
4210 PortAddr iop_base;
4211 ASC_PADDR phy_addr;
4212 ASC_DCNT phy_size;
4213 struct asc_board *board = asc_dvc_to_board(asc_dvc);
4214
4215 iop_base = asc_dvc->iop_base;
4216 warn_code = 0;
4217 for (i = 0; i <= ASC_MAX_TID; i++) {
4218 AscPutMCodeInitSDTRAtID(iop_base, i,
4219 asc_dvc->cfg->sdtr_period_offset[i]);
4220 }
4221
4222 AscInitQLinkVar(asc_dvc);
4223 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
4224 asc_dvc->cfg->disc_enable);
4225 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
4226 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
4227
4228 /* Ensure overrun buffer is aligned on an 8 byte boundary. */
4229 BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
4230 asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
4231 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4232 if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
4233 warn_code = -ENOMEM;
4234 goto err_dma_map;
4235 }
4236 phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
4237 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
4238 (uchar *)&phy_addr, 1);
4239 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
4240 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
4241 (uchar *)&phy_size, 1);
4242
4243 asc_dvc->cfg->mcode_date =
4244 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
4245 asc_dvc->cfg->mcode_version =
4246 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
4247
4248 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
4249 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
4250 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
4251 warn_code = UW_ERR;
4252 goto err_mcode_start;
4253 }
4254 if (AscStartChip(iop_base) != 1) {
4255 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
4256 warn_code = UW_ERR;
4257 goto err_mcode_start;
4258 }
4259
4260 return warn_code;
4261
4262 err_mcode_start:
4263 dma_unmap_single(board->dev, asc_dvc->overrun_dma,
4264 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4265 err_dma_map:
4266 asc_dvc->overrun_dma = 0;
4267 return warn_code;
4268 }
4269
4270 static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
4271 {
4272 const struct firmware *fw;
4273 const char fwname[] = "advansys/mcode.bin";
4274 int err;
4275 unsigned long chksum;
4276 ushort warn_code;
4277 PortAddr iop_base;
4278
4279 iop_base = asc_dvc->iop_base;
4280 warn_code = 0;
4281 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
4282 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
4283 AscResetChipAndScsiBus(asc_dvc);
4284 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4285 }
4286 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
4287 if (asc_dvc->err_code != 0)
4288 return UW_ERR;
4289 if (!AscFindSignature(asc_dvc->iop_base)) {
4290 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
4291 return warn_code;
4292 }
4293 AscDisableInterrupt(iop_base);
4294 warn_code |= AscInitLram(asc_dvc);
4295 if (asc_dvc->err_code != 0)
4296 return UW_ERR;
4297
4298 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4299 if (err) {
4300 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4301 fwname, err);
4302 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4303 return err;
4304 }
4305 if (fw->size < 4) {
4306 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4307 fw->size, fwname);
4308 release_firmware(fw);
4309 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4310 return -EINVAL;
4311 }
4312 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4313 (fw->data[1] << 8) | fw->data[0];
4314 ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
4315 if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4316 fw->size - 4) != chksum) {
4317 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4318 release_firmware(fw);
4319 return warn_code;
4320 }
4321 release_firmware(fw);
4322 warn_code |= AscInitMicroCodeVar(asc_dvc);
4323 if (!asc_dvc->overrun_dma)
4324 return warn_code;
4325 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
4326 AscEnableInterrupt(iop_base);
4327 return warn_code;
4328 }
4329
4330 /*
4331 * Load the Microcode
4332 *
4333 * Write the microcode image to RISC memory starting at address 0.
4334 *
4335 * The microcode is stored compressed in the following format:
4336 *
4337 * 254 word (508 byte) table indexed by byte code followed
4338 * by the following byte codes:
4339 *
4340 * 1-Byte Code:
4341 * 00: Emit word 0 in table.
4342 * 01: Emit word 1 in table.
4343 * .
4344 * FD: Emit word 253 in table.
4345 *
4346 * Multi-Byte Code:
4347 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4348 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4349 *
4350 * Returns 0 or an error if the checksum doesn't match
4351 */
4352 static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
4353 int size, int memsize, int chksum)
4354 {
4355 int i, j, end, len = 0;
4356 ADV_DCNT sum;
4357
4358 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4359
4360 for (i = 253 * 2; i < size; i++) {
4361 if (buf[i] == 0xff) {
4362 unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
4363 for (j = 0; j < buf[i + 1]; j++) {
4364 AdvWriteWordAutoIncLram(iop_base, word);
4365 len += 2;
4366 }
4367 i += 3;
4368 } else if (buf[i] == 0xfe) {
4369 unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
4370 AdvWriteWordAutoIncLram(iop_base, word);
4371 i += 2;
4372 len += 2;
4373 } else {
4374 unsigned int off = buf[i] * 2;
4375 unsigned short word = (buf[off + 1] << 8) | buf[off];
4376 AdvWriteWordAutoIncLram(iop_base, word);
4377 len += 2;
4378 }
4379 }
4380
4381 end = len;
4382
4383 while (len < memsize) {
4384 AdvWriteWordAutoIncLram(iop_base, 0);
4385 len += 2;
4386 }
4387
4388 /* Verify the microcode checksum. */
4389 sum = 0;
4390 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4391
4392 for (len = 0; len < end; len += 2) {
4393 sum += AdvReadWordAutoIncLram(iop_base);
4394 }
4395
4396 if (sum != chksum)
4397 return ASC_IERR_MCODE_CHKSUM;
4398
4399 return 0;
4400 }
4401
4402 static void AdvBuildCarrierFreelist(struct adv_dvc_var *asc_dvc)
4403 {
4404 ADV_CARR_T *carrp;
4405 ADV_SDCNT buf_size;
4406 ADV_PADDR carr_paddr;
4407
4408 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
4409 asc_dvc->carr_freelist = NULL;
4410 if (carrp == asc_dvc->carrier_buf) {
4411 buf_size = ADV_CARRIER_BUFSIZE;
4412 } else {
4413 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
4414 }
4415
4416 do {
4417 /* Get physical address of the carrier 'carrp'. */
4418 carr_paddr = cpu_to_le32(virt_to_bus(carrp));
4419
4420 buf_size -= sizeof(ADV_CARR_T);
4421
4422 carrp->carr_pa = carr_paddr;
4423 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
4424
4425 /*
4426 * Insert the carrier at the beginning of the freelist.
4427 */
4428 carrp->next_vpa =
4429 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
4430 asc_dvc->carr_freelist = carrp;
4431
4432 carrp++;
4433 } while (buf_size > 0);
4434 }
4435
4436 /*
4437 * Send an idle command to the chip and wait for completion.
4438 *
4439 * Command completion is polled for once per microsecond.
4440 *
4441 * The function can be called from anywhere including an interrupt handler.
4442 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
4443 * functions to prevent reentrancy.
4444 *
4445 * Return Values:
4446 * ADV_TRUE - command completed successfully
4447 * ADV_FALSE - command failed
4448 * ADV_ERROR - command timed out
4449 */
4450 static int
4451 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
4452 ushort idle_cmd, ADV_DCNT idle_cmd_parameter)
4453 {
4454 int result;
4455 ADV_DCNT i, j;
4456 AdvPortAddr iop_base;
4457
4458 iop_base = asc_dvc->iop_base;
4459
4460 /*
4461 * Clear the idle command status which is set by the microcode
4462 * to a non-zero value to indicate when the command is completed.
4463 * The non-zero result is one of the IDLE_CMD_STATUS_* values
4464 */
4465 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
4466
4467 /*
4468 * Write the idle command value after the idle command parameter
4469 * has been written to avoid a race condition. If the order is not
4470 * followed, the microcode may process the idle command before the
4471 * parameters have been written to LRAM.
4472 */
4473 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
4474 cpu_to_le32(idle_cmd_parameter));
4475 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
4476
4477 /*
4478 * Tickle the RISC to tell it to process the idle command.
4479 */
4480 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
4481 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
4482 /*
4483 * Clear the tickle value. In the ASC-3550 the RISC flag
4484 * command 'clr_tickle_b' does not work unless the host
4485 * value is cleared.
4486 */
4487 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
4488 }
4489
4490 /* Wait for up to 100 millisecond for the idle command to timeout. */
4491 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
4492 /* Poll once each microsecond for command completion. */
4493 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
4494 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
4495 result);
4496 if (result != 0)
4497 return result;
4498 udelay(1);
4499 }
4500 }
4501
4502 BUG(); /* The idle command should never timeout. */
4503 return ADV_ERROR;
4504 }
4505
4506 /*
4507 * Reset SCSI Bus and purge all outstanding requests.
4508 *
4509 * Return Value:
4510 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
4511 * ADV_FALSE(0) - Microcode command failed.
4512 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
4513 * may be hung which requires driver recovery.
4514 */
4515 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
4516 {
4517 int status;
4518
4519 /*
4520 * Send the SCSI Bus Reset idle start idle command which asserts
4521 * the SCSI Bus Reset signal.
4522 */
4523 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
4524 if (status != ADV_TRUE) {
4525 return status;
4526 }
4527
4528 /*
4529 * Delay for the specified SCSI Bus Reset hold time.
4530 *
4531 * The hold time delay is done on the host because the RISC has no
4532 * microsecond accurate timer.
4533 */
4534 udelay(ASC_SCSI_RESET_HOLD_TIME_US);
4535
4536 /*
4537 * Send the SCSI Bus Reset end idle command which de-asserts
4538 * the SCSI Bus Reset signal and purges any pending requests.
4539 */
4540 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
4541 if (status != ADV_TRUE) {
4542 return status;
4543 }
4544
4545 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4546
4547 return status;
4548 }
4549
4550 /*
4551 * Initialize the ASC-3550.
4552 *
4553 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4554 *
4555 * For a non-fatal error return a warning code. If there are no warnings
4556 * then 0 is returned.
4557 *
4558 * Needed after initialization for error recovery.
4559 */
4560 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
4561 {
4562 const struct firmware *fw;
4563 const char fwname[] = "advansys/3550.bin";
4564 AdvPortAddr iop_base;
4565 ushort warn_code;
4566 int begin_addr;
4567 int end_addr;
4568 ushort code_sum;
4569 int word;
4570 int i;
4571 int err;
4572 unsigned long chksum;
4573 ushort scsi_cfg1;
4574 uchar tid;
4575 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4576 ushort wdtr_able = 0, sdtr_able, tagqng_able;
4577 uchar max_cmd[ADV_MAX_TID + 1];
4578
4579 /* If there is already an error, don't continue. */
4580 if (asc_dvc->err_code != 0)
4581 return ADV_ERROR;
4582
4583 /*
4584 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
4585 */
4586 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
4587 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4588 return ADV_ERROR;
4589 }
4590
4591 warn_code = 0;
4592 iop_base = asc_dvc->iop_base;
4593
4594 /*
4595 * Save the RISC memory BIOS region before writing the microcode.
4596 * The BIOS may already be loaded and using its RISC LRAM region
4597 * so its region must be saved and restored.
4598 *
4599 * Note: This code makes the assumption, which is currently true,
4600 * that a chip reset does not clear RISC LRAM.
4601 */
4602 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4603 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4604 bios_mem[i]);
4605 }
4606
4607 /*
4608 * Save current per TID negotiated values.
4609 */
4610 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
4611 ushort bios_version, major, minor;
4612
4613 bios_version =
4614 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
4615 major = (bios_version >> 12) & 0xF;
4616 minor = (bios_version >> 8) & 0xF;
4617 if (major < 3 || (major == 3 && minor == 1)) {
4618 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
4619 AdvReadWordLram(iop_base, 0x120, wdtr_able);
4620 } else {
4621 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4622 }
4623 }
4624 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4625 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4626 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4627 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4628 max_cmd[tid]);
4629 }
4630
4631 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4632 if (err) {
4633 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4634 fwname, err);
4635 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4636 return err;
4637 }
4638 if (fw->size < 4) {
4639 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4640 fw->size, fwname);
4641 release_firmware(fw);
4642 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4643 return -EINVAL;
4644 }
4645 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4646 (fw->data[1] << 8) | fw->data[0];
4647 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4648 fw->size - 4, ADV_3550_MEMSIZE,
4649 chksum);
4650 release_firmware(fw);
4651 if (asc_dvc->err_code)
4652 return ADV_ERROR;
4653
4654 /*
4655 * Restore the RISC memory BIOS region.
4656 */
4657 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4658 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4659 bios_mem[i]);
4660 }
4661
4662 /*
4663 * Calculate and write the microcode code checksum to the microcode
4664 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
4665 */
4666 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
4667 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
4668 code_sum = 0;
4669 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
4670 for (word = begin_addr; word < end_addr; word += 2) {
4671 code_sum += AdvReadWordAutoIncLram(iop_base);
4672 }
4673 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
4674
4675 /*
4676 * Read and save microcode version and date.
4677 */
4678 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
4679 asc_dvc->cfg->mcode_date);
4680 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
4681 asc_dvc->cfg->mcode_version);
4682
4683 /*
4684 * Set the chip type to indicate the ASC3550.
4685 */
4686 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
4687
4688 /*
4689 * If the PCI Configuration Command Register "Parity Error Response
4690 * Control" Bit was clear (0), then set the microcode variable
4691 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
4692 * to ignore DMA parity errors.
4693 */
4694 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
4695 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4696 word |= CONTROL_FLAG_IGNORE_PERR;
4697 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4698 }
4699
4700 /*
4701 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
4702 * threshold of 128 bytes. This register is only accessible to the host.
4703 */
4704 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
4705 START_CTL_EMFU | READ_CMD_MRM);
4706
4707 /*
4708 * Microcode operating variables for WDTR, SDTR, and command tag
4709 * queuing will be set in slave_configure() based on what a
4710 * device reports it is capable of in Inquiry byte 7.
4711 *
4712 * If SCSI Bus Resets have been disabled, then directly set
4713 * SDTR and WDTR from the EEPROM configuration. This will allow
4714 * the BIOS and warm boot to work without a SCSI bus hang on
4715 * the Inquiry caused by host and target mismatched DTR values.
4716 * Without the SCSI Bus Reset, before an Inquiry a device can't
4717 * be assumed to be in Asynchronous, Narrow mode.
4718 */
4719 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
4720 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
4721 asc_dvc->wdtr_able);
4722 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
4723 asc_dvc->sdtr_able);
4724 }
4725
4726 /*
4727 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
4728 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
4729 * bitmask. These values determine the maximum SDTR speed negotiated
4730 * with a device.
4731 *
4732 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
4733 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
4734 * without determining here whether the device supports SDTR.
4735 *
4736 * 4-bit speed SDTR speed name
4737 * =========== ===============
4738 * 0000b (0x0) SDTR disabled
4739 * 0001b (0x1) 5 Mhz
4740 * 0010b (0x2) 10 Mhz
4741 * 0011b (0x3) 20 Mhz (Ultra)
4742 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
4743 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
4744 * 0110b (0x6) Undefined
4745 * .
4746 * 1111b (0xF) Undefined
4747 */
4748 word = 0;
4749 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4750 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
4751 /* Set Ultra speed for TID 'tid'. */
4752 word |= (0x3 << (4 * (tid % 4)));
4753 } else {
4754 /* Set Fast speed for TID 'tid'. */
4755 word |= (0x2 << (4 * (tid % 4)));
4756 }
4757 if (tid == 3) { /* Check if done with sdtr_speed1. */
4758 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
4759 word = 0;
4760 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
4761 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
4762 word = 0;
4763 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
4764 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
4765 word = 0;
4766 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
4767 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
4768 /* End of loop. */
4769 }
4770 }
4771
4772 /*
4773 * Set microcode operating variable for the disconnect per TID bitmask.
4774 */
4775 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
4776 asc_dvc->cfg->disc_enable);
4777
4778 /*
4779 * Set SCSI_CFG0 Microcode Default Value.
4780 *
4781 * The microcode will set the SCSI_CFG0 register using this value
4782 * after it is started below.
4783 */
4784 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
4785 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
4786 asc_dvc->chip_scsi_id);
4787
4788 /*
4789 * Determine SCSI_CFG1 Microcode Default Value.
4790 *
4791 * The microcode will set the SCSI_CFG1 register using this value
4792 * after it is started below.
4793 */
4794
4795 /* Read current SCSI_CFG1 Register value. */
4796 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
4797
4798 /*
4799 * If all three connectors are in use, return an error.
4800 */
4801 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
4802 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
4803 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
4804 return ADV_ERROR;
4805 }
4806
4807 /*
4808 * If the internal narrow cable is reversed all of the SCSI_CTRL
4809 * register signals will be set. Check for and return an error if
4810 * this condition is found.
4811 */
4812 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
4813 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
4814 return ADV_ERROR;
4815 }
4816
4817 /*
4818 * If this is a differential board and a single-ended device
4819 * is attached to one of the connectors, return an error.
4820 */
4821 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
4822 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
4823 return ADV_ERROR;
4824 }
4825
4826 /*
4827 * If automatic termination control is enabled, then set the
4828 * termination value based on a table listed in a_condor.h.
4829 *
4830 * If manual termination was specified with an EEPROM setting
4831 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
4832 * is ready to be 'ored' into SCSI_CFG1.
4833 */
4834 if (asc_dvc->cfg->termination == 0) {
4835 /*
4836 * The software always controls termination by setting TERM_CTL_SEL.
4837 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
4838 */
4839 asc_dvc->cfg->termination |= TERM_CTL_SEL;
4840
4841 switch (scsi_cfg1 & CABLE_DETECT) {
4842 /* TERM_CTL_H: on, TERM_CTL_L: on */
4843 case 0x3:
4844 case 0x7:
4845 case 0xB:
4846 case 0xD:
4847 case 0xE:
4848 case 0xF:
4849 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
4850 break;
4851
4852 /* TERM_CTL_H: on, TERM_CTL_L: off */
4853 case 0x1:
4854 case 0x5:
4855 case 0x9:
4856 case 0xA:
4857 case 0xC:
4858 asc_dvc->cfg->termination |= TERM_CTL_H;
4859 break;
4860
4861 /* TERM_CTL_H: off, TERM_CTL_L: off */
4862 case 0x2:
4863 case 0x6:
4864 break;
4865 }
4866 }
4867
4868 /*
4869 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
4870 */
4871 scsi_cfg1 &= ~TERM_CTL;
4872
4873 /*
4874 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
4875 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
4876 * referenced, because the hardware internally inverts
4877 * the Termination High and Low bits if TERM_POL is set.
4878 */
4879 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
4880
4881 /*
4882 * Set SCSI_CFG1 Microcode Default Value
4883 *
4884 * Set filter value and possibly modified termination control
4885 * bits in the Microcode SCSI_CFG1 Register Value.
4886 *
4887 * The microcode will set the SCSI_CFG1 register using this value
4888 * after it is started below.
4889 */
4890 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
4891 FLTR_DISABLE | scsi_cfg1);
4892
4893 /*
4894 * Set MEM_CFG Microcode Default Value
4895 *
4896 * The microcode will set the MEM_CFG register using this value
4897 * after it is started below.
4898 *
4899 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
4900 * are defined.
4901 *
4902 * ASC-3550 has 8KB internal memory.
4903 */
4904 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
4905 BIOS_EN | RAM_SZ_8KB);
4906
4907 /*
4908 * Set SEL_MASK Microcode Default Value
4909 *
4910 * The microcode will set the SEL_MASK register using this value
4911 * after it is started below.
4912 */
4913 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
4914 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
4915
4916 AdvBuildCarrierFreelist(asc_dvc);
4917
4918 /*
4919 * Set-up the Host->RISC Initiator Command Queue (ICQ).
4920 */
4921
4922 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
4923 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4924 return ADV_ERROR;
4925 }
4926 asc_dvc->carr_freelist = (ADV_CARR_T *)
4927 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
4928
4929 /*
4930 * The first command issued will be placed in the stopper carrier.
4931 */
4932 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
4933
4934 /*
4935 * Set RISC ICQ physical address start value.
4936 */
4937 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
4938
4939 /*
4940 * Set-up the RISC->Host Initiator Response Queue (IRQ).
4941 */
4942 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
4943 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4944 return ADV_ERROR;
4945 }
4946 asc_dvc->carr_freelist = (ADV_CARR_T *)
4947 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
4948
4949 /*
4950 * The first command completed by the RISC will be placed in
4951 * the stopper.
4952 *
4953 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
4954 * completed the RISC will set the ASC_RQ_STOPPER bit.
4955 */
4956 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
4957
4958 /*
4959 * Set RISC IRQ physical address start value.
4960 */
4961 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
4962 asc_dvc->carr_pending_cnt = 0;
4963
4964 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
4965 (ADV_INTR_ENABLE_HOST_INTR |
4966 ADV_INTR_ENABLE_GLOBAL_INTR));
4967
4968 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
4969 AdvWriteWordRegister(iop_base, IOPW_PC, word);
4970
4971 /* finally, finally, gentlemen, start your engine */
4972 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
4973
4974 /*
4975 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
4976 * Resets should be performed. The RISC has to be running
4977 * to issue a SCSI Bus Reset.
4978 */
4979 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
4980 /*
4981 * If the BIOS Signature is present in memory, restore the
4982 * BIOS Handshake Configuration Table and do not perform
4983 * a SCSI Bus Reset.
4984 */
4985 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
4986 0x55AA) {
4987 /*
4988 * Restore per TID negotiated values.
4989 */
4990 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4991 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4992 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
4993 tagqng_able);
4994 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4995 AdvWriteByteLram(iop_base,
4996 ASC_MC_NUMBER_OF_MAX_CMD + tid,
4997 max_cmd[tid]);
4998 }
4999 } else {
5000 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5001 warn_code = ASC_WARN_BUSRESET_ERROR;
5002 }
5003 }
5004 }
5005
5006 return warn_code;
5007 }
5008
5009 /*
5010 * Initialize the ASC-38C0800.
5011 *
5012 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
5013 *
5014 * For a non-fatal error return a warning code. If there are no warnings
5015 * then 0 is returned.
5016 *
5017 * Needed after initialization for error recovery.
5018 */
5019 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
5020 {
5021 const struct firmware *fw;
5022 const char fwname[] = "advansys/38C0800.bin";
5023 AdvPortAddr iop_base;
5024 ushort warn_code;
5025 int begin_addr;
5026 int end_addr;
5027 ushort code_sum;
5028 int word;
5029 int i;
5030 int err;
5031 unsigned long chksum;
5032 ushort scsi_cfg1;
5033 uchar byte;
5034 uchar tid;
5035 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
5036 ushort wdtr_able, sdtr_able, tagqng_able;
5037 uchar max_cmd[ADV_MAX_TID + 1];
5038
5039 /* If there is already an error, don't continue. */
5040 if (asc_dvc->err_code != 0)
5041 return ADV_ERROR;
5042
5043 /*
5044 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
5045 */
5046 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
5047 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5048 return ADV_ERROR;
5049 }
5050
5051 warn_code = 0;
5052 iop_base = asc_dvc->iop_base;
5053
5054 /*
5055 * Save the RISC memory BIOS region before writing the microcode.
5056 * The BIOS may already be loaded and using its RISC LRAM region
5057 * so its region must be saved and restored.
5058 *
5059 * Note: This code makes the assumption, which is currently true,
5060 * that a chip reset does not clear RISC LRAM.
5061 */
5062 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5063 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5064 bios_mem[i]);
5065 }
5066
5067 /*
5068 * Save current per TID negotiated values.
5069 */
5070 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5071 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5072 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5073 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5074 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5075 max_cmd[tid]);
5076 }
5077
5078 /*
5079 * RAM BIST (RAM Built-In Self Test)
5080 *
5081 * Address : I/O base + offset 0x38h register (byte).
5082 * Function: Bit 7-6(RW) : RAM mode
5083 * Normal Mode : 0x00
5084 * Pre-test Mode : 0x40
5085 * RAM Test Mode : 0x80
5086 * Bit 5 : unused
5087 * Bit 4(RO) : Done bit
5088 * Bit 3-0(RO) : Status
5089 * Host Error : 0x08
5090 * Int_RAM Error : 0x04
5091 * RISC Error : 0x02
5092 * SCSI Error : 0x01
5093 * No Error : 0x00
5094 *
5095 * Note: RAM BIST code should be put right here, before loading the
5096 * microcode and after saving the RISC memory BIOS region.
5097 */
5098
5099 /*
5100 * LRAM Pre-test
5101 *
5102 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5103 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5104 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5105 * to NORMAL_MODE, return an error too.
5106 */
5107 for (i = 0; i < 2; i++) {
5108 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5109 mdelay(10); /* Wait for 10ms before reading back. */
5110 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5111 if ((byte & RAM_TEST_DONE) == 0
5112 || (byte & 0x0F) != PRE_TEST_VALUE) {
5113 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5114 return ADV_ERROR;
5115 }
5116
5117 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5118 mdelay(10); /* Wait for 10ms before reading back. */
5119 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5120 != NORMAL_VALUE) {
5121 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5122 return ADV_ERROR;
5123 }
5124 }
5125
5126 /*
5127 * LRAM Test - It takes about 1.5 ms to run through the test.
5128 *
5129 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5130 * If Done bit not set or Status not 0, save register byte, set the
5131 * err_code, and return an error.
5132 */
5133 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5134 mdelay(10); /* Wait for 10ms before checking status. */
5135
5136 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5137 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5138 /* Get here if Done bit not set or Status not 0. */
5139 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5140 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5141 return ADV_ERROR;
5142 }
5143
5144 /* We need to reset back to normal mode after LRAM test passes. */
5145 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5146
5147 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5148 if (err) {
5149 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5150 fwname, err);
5151 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5152 return err;
5153 }
5154 if (fw->size < 4) {
5155 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5156 fw->size, fwname);
5157 release_firmware(fw);
5158 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5159 return -EINVAL;
5160 }
5161 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5162 (fw->data[1] << 8) | fw->data[0];
5163 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5164 fw->size - 4, ADV_38C0800_MEMSIZE,
5165 chksum);
5166 release_firmware(fw);
5167 if (asc_dvc->err_code)
5168 return ADV_ERROR;
5169
5170 /*
5171 * Restore the RISC memory BIOS region.
5172 */
5173 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5174 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5175 bios_mem[i]);
5176 }
5177
5178 /*
5179 * Calculate and write the microcode code checksum to the microcode
5180 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5181 */
5182 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5183 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5184 code_sum = 0;
5185 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5186 for (word = begin_addr; word < end_addr; word += 2) {
5187 code_sum += AdvReadWordAutoIncLram(iop_base);
5188 }
5189 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5190
5191 /*
5192 * Read microcode version and date.
5193 */
5194 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5195 asc_dvc->cfg->mcode_date);
5196 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5197 asc_dvc->cfg->mcode_version);
5198
5199 /*
5200 * Set the chip type to indicate the ASC38C0800.
5201 */
5202 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
5203
5204 /*
5205 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5206 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5207 * cable detection and then we are able to read C_DET[3:0].
5208 *
5209 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5210 * Microcode Default Value' section below.
5211 */
5212 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5213 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5214 scsi_cfg1 | DIS_TERM_DRV);
5215
5216 /*
5217 * If the PCI Configuration Command Register "Parity Error Response
5218 * Control" Bit was clear (0), then set the microcode variable
5219 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5220 * to ignore DMA parity errors.
5221 */
5222 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5223 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5224 word |= CONTROL_FLAG_IGNORE_PERR;
5225 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5226 }
5227
5228 /*
5229 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
5230 * bits for the default FIFO threshold.
5231 *
5232 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
5233 *
5234 * For DMA Errata #4 set the BC_THRESH_ENB bit.
5235 */
5236 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5237 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
5238 READ_CMD_MRM);
5239
5240 /*
5241 * Microcode operating variables for WDTR, SDTR, and command tag
5242 * queuing will be set in slave_configure() based on what a
5243 * device reports it is capable of in Inquiry byte 7.
5244 *
5245 * If SCSI Bus Resets have been disabled, then directly set
5246 * SDTR and WDTR from the EEPROM configuration. This will allow
5247 * the BIOS and warm boot to work without a SCSI bus hang on
5248 * the Inquiry caused by host and target mismatched DTR values.
5249 * Without the SCSI Bus Reset, before an Inquiry a device can't
5250 * be assumed to be in Asynchronous, Narrow mode.
5251 */
5252 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5253 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5254 asc_dvc->wdtr_able);
5255 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5256 asc_dvc->sdtr_able);
5257 }
5258
5259 /*
5260 * Set microcode operating variables for DISC and SDTR_SPEED1,
5261 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5262 * configuration values.
5263 *
5264 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5265 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5266 * without determining here whether the device supports SDTR.
5267 */
5268 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5269 asc_dvc->cfg->disc_enable);
5270 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5271 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5272 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5273 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5274
5275 /*
5276 * Set SCSI_CFG0 Microcode Default Value.
5277 *
5278 * The microcode will set the SCSI_CFG0 register using this value
5279 * after it is started below.
5280 */
5281 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5282 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5283 asc_dvc->chip_scsi_id);
5284
5285 /*
5286 * Determine SCSI_CFG1 Microcode Default Value.
5287 *
5288 * The microcode will set the SCSI_CFG1 register using this value
5289 * after it is started below.
5290 */
5291
5292 /* Read current SCSI_CFG1 Register value. */
5293 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5294
5295 /*
5296 * If the internal narrow cable is reversed all of the SCSI_CTRL
5297 * register signals will be set. Check for and return an error if
5298 * this condition is found.
5299 */
5300 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5301 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5302 return ADV_ERROR;
5303 }
5304
5305 /*
5306 * All kind of combinations of devices attached to one of four
5307 * connectors are acceptable except HVD device attached. For example,
5308 * LVD device can be attached to SE connector while SE device attached
5309 * to LVD connector. If LVD device attached to SE connector, it only
5310 * runs up to Ultra speed.
5311 *
5312 * If an HVD device is attached to one of LVD connectors, return an
5313 * error. However, there is no way to detect HVD device attached to
5314 * SE connectors.
5315 */
5316 if (scsi_cfg1 & HVD) {
5317 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
5318 return ADV_ERROR;
5319 }
5320
5321 /*
5322 * If either SE or LVD automatic termination control is enabled, then
5323 * set the termination value based on a table listed in a_condor.h.
5324 *
5325 * If manual termination was specified with an EEPROM setting then
5326 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
5327 * to be 'ored' into SCSI_CFG1.
5328 */
5329 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5330 /* SE automatic termination control is enabled. */
5331 switch (scsi_cfg1 & C_DET_SE) {
5332 /* TERM_SE_HI: on, TERM_SE_LO: on */
5333 case 0x1:
5334 case 0x2:
5335 case 0x3:
5336 asc_dvc->cfg->termination |= TERM_SE;
5337 break;
5338
5339 /* TERM_SE_HI: on, TERM_SE_LO: off */
5340 case 0x0:
5341 asc_dvc->cfg->termination |= TERM_SE_HI;
5342 break;
5343 }
5344 }
5345
5346 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
5347 /* LVD automatic termination control is enabled. */
5348 switch (scsi_cfg1 & C_DET_LVD) {
5349 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
5350 case 0x4:
5351 case 0x8:
5352 case 0xC:
5353 asc_dvc->cfg->termination |= TERM_LVD;
5354 break;
5355
5356 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
5357 case 0x0:
5358 break;
5359 }
5360 }
5361
5362 /*
5363 * Clear any set TERM_SE and TERM_LVD bits.
5364 */
5365 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
5366
5367 /*
5368 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
5369 */
5370 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
5371
5372 /*
5373 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
5374 * bits and set possibly modified termination control bits in the
5375 * Microcode SCSI_CFG1 Register Value.
5376 */
5377 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
5378
5379 /*
5380 * Set SCSI_CFG1 Microcode Default Value
5381 *
5382 * Set possibly modified termination control and reset DIS_TERM_DRV
5383 * bits in the Microcode SCSI_CFG1 Register Value.
5384 *
5385 * The microcode will set the SCSI_CFG1 register using this value
5386 * after it is started below.
5387 */
5388 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5389
5390 /*
5391 * Set MEM_CFG Microcode Default Value
5392 *
5393 * The microcode will set the MEM_CFG register using this value
5394 * after it is started below.
5395 *
5396 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5397 * are defined.
5398 *
5399 * ASC-38C0800 has 16KB internal memory.
5400 */
5401 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5402 BIOS_EN | RAM_SZ_16KB);
5403
5404 /*
5405 * Set SEL_MASK Microcode Default Value
5406 *
5407 * The microcode will set the SEL_MASK register using this value
5408 * after it is started below.
5409 */
5410 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5411 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5412
5413 AdvBuildCarrierFreelist(asc_dvc);
5414
5415 /*
5416 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5417 */
5418
5419 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
5420 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5421 return ADV_ERROR;
5422 }
5423 asc_dvc->carr_freelist = (ADV_CARR_T *)
5424 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
5425
5426 /*
5427 * The first command issued will be placed in the stopper carrier.
5428 */
5429 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5430
5431 /*
5432 * Set RISC ICQ physical address start value.
5433 * carr_pa is LE, must be native before write
5434 */
5435 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5436
5437 /*
5438 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5439 */
5440 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
5441 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5442 return ADV_ERROR;
5443 }
5444 asc_dvc->carr_freelist = (ADV_CARR_T *)
5445 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
5446
5447 /*
5448 * The first command completed by the RISC will be placed in
5449 * the stopper.
5450 *
5451 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
5452 * completed the RISC will set the ASC_RQ_STOPPER bit.
5453 */
5454 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5455
5456 /*
5457 * Set RISC IRQ physical address start value.
5458 *
5459 * carr_pa is LE, must be native before write *
5460 */
5461 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5462 asc_dvc->carr_pending_cnt = 0;
5463
5464 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5465 (ADV_INTR_ENABLE_HOST_INTR |
5466 ADV_INTR_ENABLE_GLOBAL_INTR));
5467
5468 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5469 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5470
5471 /* finally, finally, gentlemen, start your engine */
5472 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5473
5474 /*
5475 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5476 * Resets should be performed. The RISC has to be running
5477 * to issue a SCSI Bus Reset.
5478 */
5479 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5480 /*
5481 * If the BIOS Signature is present in memory, restore the
5482 * BIOS Handshake Configuration Table and do not perform
5483 * a SCSI Bus Reset.
5484 */
5485 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5486 0x55AA) {
5487 /*
5488 * Restore per TID negotiated values.
5489 */
5490 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5491 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5492 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5493 tagqng_able);
5494 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5495 AdvWriteByteLram(iop_base,
5496 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5497 max_cmd[tid]);
5498 }
5499 } else {
5500 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5501 warn_code = ASC_WARN_BUSRESET_ERROR;
5502 }
5503 }
5504 }
5505
5506 return warn_code;
5507 }
5508
5509 /*
5510 * Initialize the ASC-38C1600.
5511 *
5512 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
5513 *
5514 * For a non-fatal error return a warning code. If there are no warnings
5515 * then 0 is returned.
5516 *
5517 * Needed after initialization for error recovery.
5518 */
5519 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
5520 {
5521 const struct firmware *fw;
5522 const char fwname[] = "advansys/38C1600.bin";
5523 AdvPortAddr iop_base;
5524 ushort warn_code;
5525 int begin_addr;
5526 int end_addr;
5527 ushort code_sum;
5528 long word;
5529 int i;
5530 int err;
5531 unsigned long chksum;
5532 ushort scsi_cfg1;
5533 uchar byte;
5534 uchar tid;
5535 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
5536 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
5537 uchar max_cmd[ASC_MAX_TID + 1];
5538
5539 /* If there is already an error, don't continue. */
5540 if (asc_dvc->err_code != 0) {
5541 return ADV_ERROR;
5542 }
5543
5544 /*
5545 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
5546 */
5547 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
5548 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5549 return ADV_ERROR;
5550 }
5551
5552 warn_code = 0;
5553 iop_base = asc_dvc->iop_base;
5554
5555 /*
5556 * Save the RISC memory BIOS region before writing the microcode.
5557 * The BIOS may already be loaded and using its RISC LRAM region
5558 * so its region must be saved and restored.
5559 *
5560 * Note: This code makes the assumption, which is currently true,
5561 * that a chip reset does not clear RISC LRAM.
5562 */
5563 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5564 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5565 bios_mem[i]);
5566 }
5567
5568 /*
5569 * Save current per TID negotiated values.
5570 */
5571 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5572 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5573 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5574 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5575 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5576 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5577 max_cmd[tid]);
5578 }
5579
5580 /*
5581 * RAM BIST (Built-In Self Test)
5582 *
5583 * Address : I/O base + offset 0x38h register (byte).
5584 * Function: Bit 7-6(RW) : RAM mode
5585 * Normal Mode : 0x00
5586 * Pre-test Mode : 0x40
5587 * RAM Test Mode : 0x80
5588 * Bit 5 : unused
5589 * Bit 4(RO) : Done bit
5590 * Bit 3-0(RO) : Status
5591 * Host Error : 0x08
5592 * Int_RAM Error : 0x04
5593 * RISC Error : 0x02
5594 * SCSI Error : 0x01
5595 * No Error : 0x00
5596 *
5597 * Note: RAM BIST code should be put right here, before loading the
5598 * microcode and after saving the RISC memory BIOS region.
5599 */
5600
5601 /*
5602 * LRAM Pre-test
5603 *
5604 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5605 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5606 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5607 * to NORMAL_MODE, return an error too.
5608 */
5609 for (i = 0; i < 2; i++) {
5610 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5611 mdelay(10); /* Wait for 10ms before reading back. */
5612 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5613 if ((byte & RAM_TEST_DONE) == 0
5614 || (byte & 0x0F) != PRE_TEST_VALUE) {
5615 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5616 return ADV_ERROR;
5617 }
5618
5619 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5620 mdelay(10); /* Wait for 10ms before reading back. */
5621 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5622 != NORMAL_VALUE) {
5623 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5624 return ADV_ERROR;
5625 }
5626 }
5627
5628 /*
5629 * LRAM Test - It takes about 1.5 ms to run through the test.
5630 *
5631 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5632 * If Done bit not set or Status not 0, save register byte, set the
5633 * err_code, and return an error.
5634 */
5635 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5636 mdelay(10); /* Wait for 10ms before checking status. */
5637
5638 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5639 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5640 /* Get here if Done bit not set or Status not 0. */
5641 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5642 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5643 return ADV_ERROR;
5644 }
5645
5646 /* We need to reset back to normal mode after LRAM test passes. */
5647 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5648
5649 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5650 if (err) {
5651 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5652 fwname, err);
5653 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5654 return err;
5655 }
5656 if (fw->size < 4) {
5657 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5658 fw->size, fwname);
5659 release_firmware(fw);
5660 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5661 return -EINVAL;
5662 }
5663 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5664 (fw->data[1] << 8) | fw->data[0];
5665 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5666 fw->size - 4, ADV_38C1600_MEMSIZE,
5667 chksum);
5668 release_firmware(fw);
5669 if (asc_dvc->err_code)
5670 return ADV_ERROR;
5671
5672 /*
5673 * Restore the RISC memory BIOS region.
5674 */
5675 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5676 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5677 bios_mem[i]);
5678 }
5679
5680 /*
5681 * Calculate and write the microcode code checksum to the microcode
5682 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5683 */
5684 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5685 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5686 code_sum = 0;
5687 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5688 for (word = begin_addr; word < end_addr; word += 2) {
5689 code_sum += AdvReadWordAutoIncLram(iop_base);
5690 }
5691 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5692
5693 /*
5694 * Read microcode version and date.
5695 */
5696 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5697 asc_dvc->cfg->mcode_date);
5698 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5699 asc_dvc->cfg->mcode_version);
5700
5701 /*
5702 * Set the chip type to indicate the ASC38C1600.
5703 */
5704 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
5705
5706 /*
5707 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5708 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5709 * cable detection and then we are able to read C_DET[3:0].
5710 *
5711 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5712 * Microcode Default Value' section below.
5713 */
5714 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5715 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5716 scsi_cfg1 | DIS_TERM_DRV);
5717
5718 /*
5719 * If the PCI Configuration Command Register "Parity Error Response
5720 * Control" Bit was clear (0), then set the microcode variable
5721 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5722 * to ignore DMA parity errors.
5723 */
5724 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5725 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5726 word |= CONTROL_FLAG_IGNORE_PERR;
5727 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5728 }
5729
5730 /*
5731 * If the BIOS control flag AIPP (Asynchronous Information
5732 * Phase Protection) disable bit is not set, then set the firmware
5733 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
5734 * AIPP checking and encoding.
5735 */
5736 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
5737 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5738 word |= CONTROL_FLAG_ENABLE_AIPP;
5739 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5740 }
5741
5742 /*
5743 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
5744 * and START_CTL_TH [3:2].
5745 */
5746 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5747 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
5748
5749 /*
5750 * Microcode operating variables for WDTR, SDTR, and command tag
5751 * queuing will be set in slave_configure() based on what a
5752 * device reports it is capable of in Inquiry byte 7.
5753 *
5754 * If SCSI Bus Resets have been disabled, then directly set
5755 * SDTR and WDTR from the EEPROM configuration. This will allow
5756 * the BIOS and warm boot to work without a SCSI bus hang on
5757 * the Inquiry caused by host and target mismatched DTR values.
5758 * Without the SCSI Bus Reset, before an Inquiry a device can't
5759 * be assumed to be in Asynchronous, Narrow mode.
5760 */
5761 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5762 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5763 asc_dvc->wdtr_able);
5764 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5765 asc_dvc->sdtr_able);
5766 }
5767
5768 /*
5769 * Set microcode operating variables for DISC and SDTR_SPEED1,
5770 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5771 * configuration values.
5772 *
5773 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5774 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5775 * without determining here whether the device supports SDTR.
5776 */
5777 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5778 asc_dvc->cfg->disc_enable);
5779 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5780 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5781 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5782 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5783
5784 /*
5785 * Set SCSI_CFG0 Microcode Default Value.
5786 *
5787 * The microcode will set the SCSI_CFG0 register using this value
5788 * after it is started below.
5789 */
5790 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5791 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5792 asc_dvc->chip_scsi_id);
5793
5794 /*
5795 * Calculate SCSI_CFG1 Microcode Default Value.
5796 *
5797 * The microcode will set the SCSI_CFG1 register using this value
5798 * after it is started below.
5799 *
5800 * Each ASC-38C1600 function has only two cable detect bits.
5801 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
5802 */
5803 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5804
5805 /*
5806 * If the cable is reversed all of the SCSI_CTRL register signals
5807 * will be set. Check for and return an error if this condition is
5808 * found.
5809 */
5810 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5811 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5812 return ADV_ERROR;
5813 }
5814
5815 /*
5816 * Each ASC-38C1600 function has two connectors. Only an HVD device
5817 * can not be connected to either connector. An LVD device or SE device
5818 * may be connected to either connecor. If an SE device is connected,
5819 * then at most Ultra speed (20 Mhz) can be used on both connectors.
5820 *
5821 * If an HVD device is attached, return an error.
5822 */
5823 if (scsi_cfg1 & HVD) {
5824 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
5825 return ADV_ERROR;
5826 }
5827
5828 /*
5829 * Each function in the ASC-38C1600 uses only the SE cable detect and
5830 * termination because there are two connectors for each function. Each
5831 * function may use either LVD or SE mode. Corresponding the SE automatic
5832 * termination control EEPROM bits are used for each function. Each
5833 * function has its own EEPROM. If SE automatic control is enabled for
5834 * the function, then set the termination value based on a table listed
5835 * in a_condor.h.
5836 *
5837 * If manual termination is specified in the EEPROM for the function,
5838 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
5839 * ready to be 'ored' into SCSI_CFG1.
5840 */
5841 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5842 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
5843 /* SE automatic termination control is enabled. */
5844 switch (scsi_cfg1 & C_DET_SE) {
5845 /* TERM_SE_HI: on, TERM_SE_LO: on */
5846 case 0x1:
5847 case 0x2:
5848 case 0x3:
5849 asc_dvc->cfg->termination |= TERM_SE;
5850 break;
5851
5852 case 0x0:
5853 if (PCI_FUNC(pdev->devfn) == 0) {
5854 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
5855 } else {
5856 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
5857 asc_dvc->cfg->termination |= TERM_SE_HI;
5858 }
5859 break;
5860 }
5861 }
5862
5863 /*
5864 * Clear any set TERM_SE bits.
5865 */
5866 scsi_cfg1 &= ~TERM_SE;
5867
5868 /*
5869 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
5870 */
5871 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
5872
5873 /*
5874 * Clear Big Endian and Terminator Polarity bits and set possibly
5875 * modified termination control bits in the Microcode SCSI_CFG1
5876 * Register Value.
5877 *
5878 * Big Endian bit is not used even on big endian machines.
5879 */
5880 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
5881
5882 /*
5883 * Set SCSI_CFG1 Microcode Default Value
5884 *
5885 * Set possibly modified termination control bits in the Microcode
5886 * SCSI_CFG1 Register Value.
5887 *
5888 * The microcode will set the SCSI_CFG1 register using this value
5889 * after it is started below.
5890 */
5891 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5892
5893 /*
5894 * Set MEM_CFG Microcode Default Value
5895 *
5896 * The microcode will set the MEM_CFG register using this value
5897 * after it is started below.
5898 *
5899 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5900 * are defined.
5901 *
5902 * ASC-38C1600 has 32KB internal memory.
5903 *
5904 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
5905 * out a special 16K Adv Library and Microcode version. After the issue
5906 * resolved, we should turn back to the 32K support. Both a_condor.h and
5907 * mcode.sas files also need to be updated.
5908 *
5909 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5910 * BIOS_EN | RAM_SZ_32KB);
5911 */
5912 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5913 BIOS_EN | RAM_SZ_16KB);
5914
5915 /*
5916 * Set SEL_MASK Microcode Default Value
5917 *
5918 * The microcode will set the SEL_MASK register using this value
5919 * after it is started below.
5920 */
5921 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5922 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5923
5924 AdvBuildCarrierFreelist(asc_dvc);
5925
5926 /*
5927 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5928 */
5929 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
5930 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5931 return ADV_ERROR;
5932 }
5933 asc_dvc->carr_freelist = (ADV_CARR_T *)
5934 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
5935
5936 /*
5937 * The first command issued will be placed in the stopper carrier.
5938 */
5939 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5940
5941 /*
5942 * Set RISC ICQ physical address start value. Initialize the
5943 * COMMA register to the same value otherwise the RISC will
5944 * prematurely detect a command is available.
5945 */
5946 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5947 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
5948 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
5949
5950 /*
5951 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5952 */
5953 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
5954 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5955 return ADV_ERROR;
5956 }
5957 asc_dvc->carr_freelist = (ADV_CARR_T *)
5958 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
5959
5960 /*
5961 * The first command completed by the RISC will be placed in
5962 * the stopper.
5963 *
5964 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
5965 * completed the RISC will set the ASC_RQ_STOPPER bit.
5966 */
5967 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5968
5969 /*
5970 * Set RISC IRQ physical address start value.
5971 */
5972 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5973 asc_dvc->carr_pending_cnt = 0;
5974
5975 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5976 (ADV_INTR_ENABLE_HOST_INTR |
5977 ADV_INTR_ENABLE_GLOBAL_INTR));
5978 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5979 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5980
5981 /* finally, finally, gentlemen, start your engine */
5982 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5983
5984 /*
5985 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5986 * Resets should be performed. The RISC has to be running
5987 * to issue a SCSI Bus Reset.
5988 */
5989 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5990 /*
5991 * If the BIOS Signature is present in memory, restore the
5992 * per TID microcode operating variables.
5993 */
5994 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5995 0x55AA) {
5996 /*
5997 * Restore per TID negotiated values.
5998 */
5999 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6000 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6001 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
6002 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
6003 tagqng_able);
6004 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
6005 AdvWriteByteLram(iop_base,
6006 ASC_MC_NUMBER_OF_MAX_CMD + tid,
6007 max_cmd[tid]);
6008 }
6009 } else {
6010 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
6011 warn_code = ASC_WARN_BUSRESET_ERROR;
6012 }
6013 }
6014 }
6015
6016 return warn_code;
6017 }
6018
6019 /*
6020 * Reset chip and SCSI Bus.
6021 *
6022 * Return Value:
6023 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
6024 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
6025 */
6026 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
6027 {
6028 int status;
6029 ushort wdtr_able, sdtr_able, tagqng_able;
6030 ushort ppr_able = 0;
6031 uchar tid, max_cmd[ADV_MAX_TID + 1];
6032 AdvPortAddr iop_base;
6033 ushort bios_sig;
6034
6035 iop_base = asc_dvc->iop_base;
6036
6037 /*
6038 * Save current per TID negotiated values.
6039 */
6040 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6041 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6042 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
6043 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
6044 }
6045 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6046 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6047 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6048 max_cmd[tid]);
6049 }
6050
6051 /*
6052 * Force the AdvInitAsc3550/38C0800Driver() function to
6053 * perform a SCSI Bus Reset by clearing the BIOS signature word.
6054 * The initialization functions assumes a SCSI Bus Reset is not
6055 * needed if the BIOS signature word is present.
6056 */
6057 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
6058 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
6059
6060 /*
6061 * Stop chip and reset it.
6062 */
6063 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
6064 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
6065 mdelay(100);
6066 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
6067 ADV_CTRL_REG_CMD_WR_IO_REG);
6068
6069 /*
6070 * Reset Adv Library error code, if any, and try
6071 * re-initializing the chip.
6072 */
6073 asc_dvc->err_code = 0;
6074 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
6075 status = AdvInitAsc38C1600Driver(asc_dvc);
6076 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6077 status = AdvInitAsc38C0800Driver(asc_dvc);
6078 } else {
6079 status = AdvInitAsc3550Driver(asc_dvc);
6080 }
6081
6082 /* Translate initialization return value to status value. */
6083 if (status == 0) {
6084 status = ADV_TRUE;
6085 } else {
6086 status = ADV_FALSE;
6087 }
6088
6089 /*
6090 * Restore the BIOS signature word.
6091 */
6092 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
6093
6094 /*
6095 * Restore per TID negotiated values.
6096 */
6097 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6098 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6099 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
6100 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
6101 }
6102 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6103 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6104 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6105 max_cmd[tid]);
6106 }
6107
6108 return status;
6109 }
6110
6111 /*
6112 * adv_async_callback() - Adv Library asynchronous event callback function.
6113 */
6114 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
6115 {
6116 switch (code) {
6117 case ADV_ASYNC_SCSI_BUS_RESET_DET:
6118 /*
6119 * The firmware detected a SCSI Bus reset.
6120 */
6121 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
6122 break;
6123
6124 case ADV_ASYNC_RDMA_FAILURE:
6125 /*
6126 * Handle RDMA failure by resetting the SCSI Bus and
6127 * possibly the chip if it is unresponsive. Log the error
6128 * with a unique code.
6129 */
6130 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
6131 AdvResetChipAndSB(adv_dvc_varp);
6132 break;
6133
6134 case ADV_HOST_SCSI_BUS_RESET:
6135 /*
6136 * Host generated SCSI bus reset occurred.
6137 */
6138 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
6139 break;
6140
6141 default:
6142 ASC_DBG(0, "unknown code 0x%x\n", code);
6143 break;
6144 }
6145 }
6146
6147 /*
6148 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
6149 *
6150 * Callback function for the Wide SCSI Adv Library.
6151 */
6152 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
6153 {
6154 struct asc_board *boardp;
6155 adv_req_t *reqp;
6156 adv_sgblk_t *sgblkp;
6157 struct scsi_cmnd *scp;
6158 struct Scsi_Host *shost;
6159 ADV_DCNT resid_cnt;
6160
6161 ASC_DBG(1, "adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
6162 (ulong)adv_dvc_varp, (ulong)scsiqp);
6163 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
6164
6165 /*
6166 * Get the adv_req_t structure for the command that has been
6167 * completed. The adv_req_t structure actually contains the
6168 * completed ADV_SCSI_REQ_Q structure.
6169 */
6170 reqp = (adv_req_t *)ADV_U32_TO_VADDR(scsiqp->srb_ptr);
6171 ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
6172 if (reqp == NULL) {
6173 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
6174 return;
6175 }
6176
6177 /*
6178 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
6179 * command that has been completed.
6180 *
6181 * Note: The adv_req_t request structure and adv_sgblk_t structure,
6182 * if any, are dropped, because a board structure pointer can not be
6183 * determined.
6184 */
6185 scp = reqp->cmndp;
6186 ASC_DBG(1, "scp 0x%p\n", scp);
6187 if (scp == NULL) {
6188 ASC_PRINT
6189 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
6190 return;
6191 }
6192 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6193
6194 shost = scp->device->host;
6195 ASC_STATS(shost, callback);
6196 ASC_DBG(1, "shost 0x%p\n", shost);
6197
6198 boardp = shost_priv(shost);
6199 BUG_ON(adv_dvc_varp != &boardp->dvc_var.adv_dvc_var);
6200
6201 /*
6202 * 'done_status' contains the command's ending status.
6203 */
6204 switch (scsiqp->done_status) {
6205 case QD_NO_ERROR:
6206 ASC_DBG(2, "QD_NO_ERROR\n");
6207 scp->result = 0;
6208
6209 /*
6210 * Check for an underrun condition.
6211 *
6212 * If there was no error and an underrun condition, then
6213 * then return the number of underrun bytes.
6214 */
6215 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
6216 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 &&
6217 resid_cnt <= scsi_bufflen(scp)) {
6218 ASC_DBG(1, "underrun condition %lu bytes\n",
6219 (ulong)resid_cnt);
6220 scsi_set_resid(scp, resid_cnt);
6221 }
6222 break;
6223
6224 case QD_WITH_ERROR:
6225 ASC_DBG(2, "QD_WITH_ERROR\n");
6226 switch (scsiqp->host_status) {
6227 case QHSTA_NO_ERROR:
6228 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
6229 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
6230 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
6231 SCSI_SENSE_BUFFERSIZE);
6232 /*
6233 * Note: The 'status_byte()' macro used by
6234 * target drivers defined in scsi.h shifts the
6235 * status byte returned by host drivers right
6236 * by 1 bit. This is why target drivers also
6237 * use right shifted status byte definitions.
6238 * For instance target drivers use
6239 * CHECK_CONDITION, defined to 0x1, instead of
6240 * the SCSI defined check condition value of
6241 * 0x2. Host drivers are supposed to return
6242 * the status byte as it is defined by SCSI.
6243 */
6244 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6245 STATUS_BYTE(scsiqp->scsi_status);
6246 } else {
6247 scp->result = STATUS_BYTE(scsiqp->scsi_status);
6248 }
6249 break;
6250
6251 default:
6252 /* Some other QHSTA error occurred. */
6253 ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
6254 scp->result = HOST_BYTE(DID_BAD_TARGET);
6255 break;
6256 }
6257 break;
6258
6259 case QD_ABORTED_BY_HOST:
6260 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
6261 scp->result =
6262 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
6263 break;
6264
6265 default:
6266 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
6267 scp->result =
6268 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
6269 break;
6270 }
6271
6272 /*
6273 * If the 'init_tidmask' bit isn't already set for the target and the
6274 * current request finished normally, then set the bit for the target
6275 * to indicate that a device is present.
6276 */
6277 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6278 scsiqp->done_status == QD_NO_ERROR &&
6279 scsiqp->host_status == QHSTA_NO_ERROR) {
6280 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6281 }
6282
6283 asc_scsi_done(scp);
6284
6285 /*
6286 * Free all 'adv_sgblk_t' structures allocated for the request.
6287 */
6288 while ((sgblkp = reqp->sgblkp) != NULL) {
6289 /* Remove 'sgblkp' from the request list. */
6290 reqp->sgblkp = sgblkp->next_sgblkp;
6291
6292 /* Add 'sgblkp' to the board free list. */
6293 sgblkp->next_sgblkp = boardp->adv_sgblkp;
6294 boardp->adv_sgblkp = sgblkp;
6295 }
6296
6297 /*
6298 * Free the adv_req_t structure used with the command by adding
6299 * it back to the board free list.
6300 */
6301 reqp->next_reqp = boardp->adv_reqp;
6302 boardp->adv_reqp = reqp;
6303
6304 ASC_DBG(1, "done\n");
6305 }
6306
6307 /*
6308 * Adv Library Interrupt Service Routine
6309 *
6310 * This function is called by a driver's interrupt service routine.
6311 * The function disables and re-enables interrupts.
6312 *
6313 * When a microcode idle command is completed, the ADV_DVC_VAR
6314 * 'idle_cmd_done' field is set to ADV_TRUE.
6315 *
6316 * Note: AdvISR() can be called when interrupts are disabled or even
6317 * when there is no hardware interrupt condition present. It will
6318 * always check for completed idle commands and microcode requests.
6319 * This is an important feature that shouldn't be changed because it
6320 * allows commands to be completed from polling mode loops.
6321 *
6322 * Return:
6323 * ADV_TRUE(1) - interrupt was pending
6324 * ADV_FALSE(0) - no interrupt was pending
6325 */
6326 static int AdvISR(ADV_DVC_VAR *asc_dvc)
6327 {
6328 AdvPortAddr iop_base;
6329 uchar int_stat;
6330 ushort target_bit;
6331 ADV_CARR_T *free_carrp;
6332 ADV_VADDR irq_next_vpa;
6333 ADV_SCSI_REQ_Q *scsiq;
6334
6335 iop_base = asc_dvc->iop_base;
6336
6337 /* Reading the register clears the interrupt. */
6338 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
6339
6340 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
6341 ADV_INTR_STATUS_INTRC)) == 0) {
6342 return ADV_FALSE;
6343 }
6344
6345 /*
6346 * Notify the driver of an asynchronous microcode condition by
6347 * calling the adv_async_callback function. The function
6348 * is passed the microcode ASC_MC_INTRB_CODE byte value.
6349 */
6350 if (int_stat & ADV_INTR_STATUS_INTRB) {
6351 uchar intrb_code;
6352
6353 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
6354
6355 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
6356 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6357 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
6358 asc_dvc->carr_pending_cnt != 0) {
6359 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
6360 ADV_TICKLE_A);
6361 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6362 AdvWriteByteRegister(iop_base,
6363 IOPB_TICKLE,
6364 ADV_TICKLE_NOP);
6365 }
6366 }
6367 }
6368
6369 adv_async_callback(asc_dvc, intrb_code);
6370 }
6371
6372 /*
6373 * Check if the IRQ stopper carrier contains a completed request.
6374 */
6375 while (((irq_next_vpa =
6376 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
6377 /*
6378 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
6379 * The RISC will have set 'areq_vpa' to a virtual address.
6380 *
6381 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
6382 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
6383 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
6384 * in AdvExeScsiQueue().
6385 */
6386 scsiq = (ADV_SCSI_REQ_Q *)
6387 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
6388
6389 /*
6390 * Request finished with good status and the queue was not
6391 * DMAed to host memory by the firmware. Set all status fields
6392 * to indicate good status.
6393 */
6394 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
6395 scsiq->done_status = QD_NO_ERROR;
6396 scsiq->host_status = scsiq->scsi_status = 0;
6397 scsiq->data_cnt = 0L;
6398 }
6399
6400 /*
6401 * Advance the stopper pointer to the next carrier
6402 * ignoring the lower four bits. Free the previous
6403 * stopper carrier.
6404 */
6405 free_carrp = asc_dvc->irq_sp;
6406 asc_dvc->irq_sp = (ADV_CARR_T *)
6407 ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
6408
6409 free_carrp->next_vpa =
6410 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
6411 asc_dvc->carr_freelist = free_carrp;
6412 asc_dvc->carr_pending_cnt--;
6413
6414 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
6415
6416 /*
6417 * Clear request microcode control flag.
6418 */
6419 scsiq->cntl = 0;
6420
6421 /*
6422 * Notify the driver of the completed request by passing
6423 * the ADV_SCSI_REQ_Q pointer to its callback function.
6424 */
6425 scsiq->a_flag |= ADV_SCSIQ_DONE;
6426 adv_isr_callback(asc_dvc, scsiq);
6427 /*
6428 * Note: After the driver callback function is called, 'scsiq'
6429 * can no longer be referenced.
6430 *
6431 * Fall through and continue processing other completed
6432 * requests...
6433 */
6434 }
6435 return ADV_TRUE;
6436 }
6437
6438 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
6439 {
6440 if (asc_dvc->err_code == 0) {
6441 asc_dvc->err_code = err_code;
6442 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
6443 err_code);
6444 }
6445 return err_code;
6446 }
6447
6448 static void AscAckInterrupt(PortAddr iop_base)
6449 {
6450 uchar host_flag;
6451 uchar risc_flag;
6452 ushort loop;
6453
6454 loop = 0;
6455 do {
6456 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
6457 if (loop++ > 0x7FFF) {
6458 break;
6459 }
6460 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
6461 host_flag =
6462 AscReadLramByte(iop_base,
6463 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
6464 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
6465 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
6466 AscSetChipStatus(iop_base, CIW_INT_ACK);
6467 loop = 0;
6468 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
6469 AscSetChipStatus(iop_base, CIW_INT_ACK);
6470 if (loop++ > 3) {
6471 break;
6472 }
6473 }
6474 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
6475 }
6476
6477 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
6478 {
6479 const uchar *period_table;
6480 int max_index;
6481 int min_index;
6482 int i;
6483
6484 period_table = asc_dvc->sdtr_period_tbl;
6485 max_index = (int)asc_dvc->max_sdtr_index;
6486 min_index = (int)asc_dvc->min_sdtr_index;
6487 if ((syn_time <= period_table[max_index])) {
6488 for (i = min_index; i < (max_index - 1); i++) {
6489 if (syn_time <= period_table[i]) {
6490 return (uchar)i;
6491 }
6492 }
6493 return (uchar)max_index;
6494 } else {
6495 return (uchar)(max_index + 1);
6496 }
6497 }
6498
6499 static uchar
6500 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
6501 {
6502 EXT_MSG sdtr_buf;
6503 uchar sdtr_period_index;
6504 PortAddr iop_base;
6505
6506 iop_base = asc_dvc->iop_base;
6507 sdtr_buf.msg_type = EXTENDED_MESSAGE;
6508 sdtr_buf.msg_len = MS_SDTR_LEN;
6509 sdtr_buf.msg_req = EXTENDED_SDTR;
6510 sdtr_buf.xfer_period = sdtr_period;
6511 sdtr_offset &= ASC_SYN_MAX_OFFSET;
6512 sdtr_buf.req_ack_offset = sdtr_offset;
6513 sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6514 if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
6515 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6516 (uchar *)&sdtr_buf,
6517 sizeof(EXT_MSG) >> 1);
6518 return ((sdtr_period_index << 4) | sdtr_offset);
6519 } else {
6520 sdtr_buf.req_ack_offset = 0;
6521 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6522 (uchar *)&sdtr_buf,
6523 sizeof(EXT_MSG) >> 1);
6524 return 0;
6525 }
6526 }
6527
6528 static uchar
6529 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
6530 {
6531 uchar byte;
6532 uchar sdtr_period_ix;
6533
6534 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6535 if (sdtr_period_ix > asc_dvc->max_sdtr_index)
6536 return 0xFF;
6537 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
6538 return byte;
6539 }
6540
6541 static int AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
6542 {
6543 ASC_SCSI_BIT_ID_TYPE org_id;
6544 int i;
6545 int sta = TRUE;
6546
6547 AscSetBank(iop_base, 1);
6548 org_id = AscReadChipDvcID(iop_base);
6549 for (i = 0; i <= ASC_MAX_TID; i++) {
6550 if (org_id == (0x01 << i))
6551 break;
6552 }
6553 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
6554 AscWriteChipDvcID(iop_base, id);
6555 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
6556 AscSetBank(iop_base, 0);
6557 AscSetChipSyn(iop_base, sdtr_data);
6558 if (AscGetChipSyn(iop_base) != sdtr_data) {
6559 sta = FALSE;
6560 }
6561 } else {
6562 sta = FALSE;
6563 }
6564 AscSetBank(iop_base, 1);
6565 AscWriteChipDvcID(iop_base, org_id);
6566 AscSetBank(iop_base, 0);
6567 return (sta);
6568 }
6569
6570 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
6571 {
6572 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
6573 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
6574 }
6575
6576 static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
6577 {
6578 EXT_MSG ext_msg;
6579 EXT_MSG out_msg;
6580 ushort halt_q_addr;
6581 int sdtr_accept;
6582 ushort int_halt_code;
6583 ASC_SCSI_BIT_ID_TYPE scsi_busy;
6584 ASC_SCSI_BIT_ID_TYPE target_id;
6585 PortAddr iop_base;
6586 uchar tag_code;
6587 uchar q_status;
6588 uchar halt_qp;
6589 uchar sdtr_data;
6590 uchar target_ix;
6591 uchar q_cntl, tid_no;
6592 uchar cur_dvc_qng;
6593 uchar asyn_sdtr;
6594 uchar scsi_status;
6595 struct asc_board *boardp;
6596
6597 BUG_ON(!asc_dvc->drv_ptr);
6598 boardp = asc_dvc->drv_ptr;
6599
6600 iop_base = asc_dvc->iop_base;
6601 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
6602
6603 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
6604 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
6605 target_ix = AscReadLramByte(iop_base,
6606 (ushort)(halt_q_addr +
6607 (ushort)ASC_SCSIQ_B_TARGET_IX));
6608 q_cntl = AscReadLramByte(iop_base,
6609 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6610 tid_no = ASC_TIX_TO_TID(target_ix);
6611 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
6612 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6613 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
6614 } else {
6615 asyn_sdtr = 0;
6616 }
6617 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
6618 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6619 AscSetChipSDTR(iop_base, 0, tid_no);
6620 boardp->sdtr_data[tid_no] = 0;
6621 }
6622 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6623 return (0);
6624 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
6625 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6626 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6627 boardp->sdtr_data[tid_no] = asyn_sdtr;
6628 }
6629 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6630 return (0);
6631 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
6632 AscMemWordCopyPtrFromLram(iop_base,
6633 ASCV_MSGIN_BEG,
6634 (uchar *)&ext_msg,
6635 sizeof(EXT_MSG) >> 1);
6636
6637 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6638 ext_msg.msg_req == EXTENDED_SDTR &&
6639 ext_msg.msg_len == MS_SDTR_LEN) {
6640 sdtr_accept = TRUE;
6641 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
6642
6643 sdtr_accept = FALSE;
6644 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
6645 }
6646 if ((ext_msg.xfer_period <
6647 asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
6648 || (ext_msg.xfer_period >
6649 asc_dvc->sdtr_period_tbl[asc_dvc->
6650 max_sdtr_index])) {
6651 sdtr_accept = FALSE;
6652 ext_msg.xfer_period =
6653 asc_dvc->sdtr_period_tbl[asc_dvc->
6654 min_sdtr_index];
6655 }
6656 if (sdtr_accept) {
6657 sdtr_data =
6658 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
6659 ext_msg.req_ack_offset);
6660 if ((sdtr_data == 0xFF)) {
6661
6662 q_cntl |= QC_MSG_OUT;
6663 asc_dvc->init_sdtr &= ~target_id;
6664 asc_dvc->sdtr_done &= ~target_id;
6665 AscSetChipSDTR(iop_base, asyn_sdtr,
6666 tid_no);
6667 boardp->sdtr_data[tid_no] = asyn_sdtr;
6668 }
6669 }
6670 if (ext_msg.req_ack_offset == 0) {
6671
6672 q_cntl &= ~QC_MSG_OUT;
6673 asc_dvc->init_sdtr &= ~target_id;
6674 asc_dvc->sdtr_done &= ~target_id;
6675 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6676 } else {
6677 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
6678 q_cntl &= ~QC_MSG_OUT;
6679 asc_dvc->sdtr_done |= target_id;
6680 asc_dvc->init_sdtr |= target_id;
6681 asc_dvc->pci_fix_asyn_xfer &=
6682 ~target_id;
6683 sdtr_data =
6684 AscCalSDTRData(asc_dvc,
6685 ext_msg.xfer_period,
6686 ext_msg.
6687 req_ack_offset);
6688 AscSetChipSDTR(iop_base, sdtr_data,
6689 tid_no);
6690 boardp->sdtr_data[tid_no] = sdtr_data;
6691 } else {
6692 q_cntl |= QC_MSG_OUT;
6693 AscMsgOutSDTR(asc_dvc,
6694 ext_msg.xfer_period,
6695 ext_msg.req_ack_offset);
6696 asc_dvc->pci_fix_asyn_xfer &=
6697 ~target_id;
6698 sdtr_data =
6699 AscCalSDTRData(asc_dvc,
6700 ext_msg.xfer_period,
6701 ext_msg.
6702 req_ack_offset);
6703 AscSetChipSDTR(iop_base, sdtr_data,
6704 tid_no);
6705 boardp->sdtr_data[tid_no] = sdtr_data;
6706 asc_dvc->sdtr_done |= target_id;
6707 asc_dvc->init_sdtr |= target_id;
6708 }
6709 }
6710
6711 AscWriteLramByte(iop_base,
6712 (ushort)(halt_q_addr +
6713 (ushort)ASC_SCSIQ_B_CNTL),
6714 q_cntl);
6715 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6716 return (0);
6717 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6718 ext_msg.msg_req == EXTENDED_WDTR &&
6719 ext_msg.msg_len == MS_WDTR_LEN) {
6720
6721 ext_msg.wdtr_width = 0;
6722 AscMemWordCopyPtrToLram(iop_base,
6723 ASCV_MSGOUT_BEG,
6724 (uchar *)&ext_msg,
6725 sizeof(EXT_MSG) >> 1);
6726 q_cntl |= QC_MSG_OUT;
6727 AscWriteLramByte(iop_base,
6728 (ushort)(halt_q_addr +
6729 (ushort)ASC_SCSIQ_B_CNTL),
6730 q_cntl);
6731 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6732 return (0);
6733 } else {
6734
6735 ext_msg.msg_type = MESSAGE_REJECT;
6736 AscMemWordCopyPtrToLram(iop_base,
6737 ASCV_MSGOUT_BEG,
6738 (uchar *)&ext_msg,
6739 sizeof(EXT_MSG) >> 1);
6740 q_cntl |= QC_MSG_OUT;
6741 AscWriteLramByte(iop_base,
6742 (ushort)(halt_q_addr +
6743 (ushort)ASC_SCSIQ_B_CNTL),
6744 q_cntl);
6745 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6746 return (0);
6747 }
6748 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
6749
6750 q_cntl |= QC_REQ_SENSE;
6751
6752 if ((asc_dvc->init_sdtr & target_id) != 0) {
6753
6754 asc_dvc->sdtr_done &= ~target_id;
6755
6756 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
6757 q_cntl |= QC_MSG_OUT;
6758 AscMsgOutSDTR(asc_dvc,
6759 asc_dvc->
6760 sdtr_period_tbl[(sdtr_data >> 4) &
6761 (uchar)(asc_dvc->
6762 max_sdtr_index -
6763 1)],
6764 (uchar)(sdtr_data & (uchar)
6765 ASC_SYN_MAX_OFFSET));
6766 }
6767
6768 AscWriteLramByte(iop_base,
6769 (ushort)(halt_q_addr +
6770 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6771
6772 tag_code = AscReadLramByte(iop_base,
6773 (ushort)(halt_q_addr + (ushort)
6774 ASC_SCSIQ_B_TAG_CODE));
6775 tag_code &= 0xDC;
6776 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
6777 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
6778 ) {
6779
6780 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
6781 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
6782
6783 }
6784 AscWriteLramByte(iop_base,
6785 (ushort)(halt_q_addr +
6786 (ushort)ASC_SCSIQ_B_TAG_CODE),
6787 tag_code);
6788
6789 q_status = AscReadLramByte(iop_base,
6790 (ushort)(halt_q_addr + (ushort)
6791 ASC_SCSIQ_B_STATUS));
6792 q_status |= (QS_READY | QS_BUSY);
6793 AscWriteLramByte(iop_base,
6794 (ushort)(halt_q_addr +
6795 (ushort)ASC_SCSIQ_B_STATUS),
6796 q_status);
6797
6798 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
6799 scsi_busy &= ~target_id;
6800 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6801
6802 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6803 return (0);
6804 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
6805
6806 AscMemWordCopyPtrFromLram(iop_base,
6807 ASCV_MSGOUT_BEG,
6808 (uchar *)&out_msg,
6809 sizeof(EXT_MSG) >> 1);
6810
6811 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
6812 (out_msg.msg_len == MS_SDTR_LEN) &&
6813 (out_msg.msg_req == EXTENDED_SDTR)) {
6814
6815 asc_dvc->init_sdtr &= ~target_id;
6816 asc_dvc->sdtr_done &= ~target_id;
6817 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6818 boardp->sdtr_data[tid_no] = asyn_sdtr;
6819 }
6820 q_cntl &= ~QC_MSG_OUT;
6821 AscWriteLramByte(iop_base,
6822 (ushort)(halt_q_addr +
6823 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6824 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6825 return (0);
6826 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
6827
6828 scsi_status = AscReadLramByte(iop_base,
6829 (ushort)((ushort)halt_q_addr +
6830 (ushort)
6831 ASC_SCSIQ_SCSI_STATUS));
6832 cur_dvc_qng =
6833 AscReadLramByte(iop_base,
6834 (ushort)((ushort)ASC_QADR_BEG +
6835 (ushort)target_ix));
6836 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
6837
6838 scsi_busy = AscReadLramByte(iop_base,
6839 (ushort)ASCV_SCSIBUSY_B);
6840 scsi_busy |= target_id;
6841 AscWriteLramByte(iop_base,
6842 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6843 asc_dvc->queue_full_or_busy |= target_id;
6844
6845 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
6846 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
6847 cur_dvc_qng -= 1;
6848 asc_dvc->max_dvc_qng[tid_no] =
6849 cur_dvc_qng;
6850
6851 AscWriteLramByte(iop_base,
6852 (ushort)((ushort)
6853 ASCV_MAX_DVC_QNG_BEG
6854 + (ushort)
6855 tid_no),
6856 cur_dvc_qng);
6857
6858 /*
6859 * Set the device queue depth to the
6860 * number of active requests when the
6861 * QUEUE FULL condition was encountered.
6862 */
6863 boardp->queue_full |= target_id;
6864 boardp->queue_full_cnt[tid_no] =
6865 cur_dvc_qng;
6866 }
6867 }
6868 }
6869 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6870 return (0);
6871 }
6872 #if CC_VERY_LONG_SG_LIST
6873 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
6874 uchar q_no;
6875 ushort q_addr;
6876 uchar sg_wk_q_no;
6877 uchar first_sg_wk_q_no;
6878 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
6879 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
6880 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
6881 ushort sg_list_dwords;
6882 ushort sg_entry_cnt;
6883 uchar next_qp;
6884 int i;
6885
6886 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
6887 if (q_no == ASC_QLINK_END)
6888 return 0;
6889
6890 q_addr = ASC_QNO_TO_QADDR(q_no);
6891
6892 /*
6893 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
6894 * structure pointer using a macro provided by the driver.
6895 * The ASC_SCSI_REQ pointer provides a pointer to the
6896 * host ASC_SG_HEAD structure.
6897 */
6898 /* Read request's SRB pointer. */
6899 scsiq = (ASC_SCSI_Q *)
6900 ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
6901 (ushort)
6902 (q_addr +
6903 ASC_SCSIQ_D_SRBPTR))));
6904
6905 /*
6906 * Get request's first and working SG queue.
6907 */
6908 sg_wk_q_no = AscReadLramByte(iop_base,
6909 (ushort)(q_addr +
6910 ASC_SCSIQ_B_SG_WK_QP));
6911
6912 first_sg_wk_q_no = AscReadLramByte(iop_base,
6913 (ushort)(q_addr +
6914 ASC_SCSIQ_B_FIRST_SG_WK_QP));
6915
6916 /*
6917 * Reset request's working SG queue back to the
6918 * first SG queue.
6919 */
6920 AscWriteLramByte(iop_base,
6921 (ushort)(q_addr +
6922 (ushort)ASC_SCSIQ_B_SG_WK_QP),
6923 first_sg_wk_q_no);
6924
6925 sg_head = scsiq->sg_head;
6926
6927 /*
6928 * Set sg_entry_cnt to the number of SG elements
6929 * that will be completed on this interrupt.
6930 *
6931 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
6932 * SG elements. The data_cnt and data_addr fields which
6933 * add 1 to the SG element capacity are not used when
6934 * restarting SG handling after a halt.
6935 */
6936 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
6937 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
6938
6939 /*
6940 * Keep track of remaining number of SG elements that
6941 * will need to be handled on the next interrupt.
6942 */
6943 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
6944 } else {
6945 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
6946 scsiq->remain_sg_entry_cnt = 0;
6947 }
6948
6949 /*
6950 * Copy SG elements into the list of allocated SG queues.
6951 *
6952 * Last index completed is saved in scsiq->next_sg_index.
6953 */
6954 next_qp = first_sg_wk_q_no;
6955 q_addr = ASC_QNO_TO_QADDR(next_qp);
6956 scsi_sg_q.sg_head_qp = q_no;
6957 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
6958 for (i = 0; i < sg_head->queue_cnt; i++) {
6959 scsi_sg_q.seq_no = i + 1;
6960 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
6961 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
6962 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
6963 /*
6964 * After very first SG queue RISC FW uses next
6965 * SG queue first element then checks sg_list_cnt
6966 * against zero and then decrements, so set
6967 * sg_list_cnt 1 less than number of SG elements
6968 * in each SG queue.
6969 */
6970 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
6971 scsi_sg_q.sg_cur_list_cnt =
6972 ASC_SG_LIST_PER_Q - 1;
6973 } else {
6974 /*
6975 * This is the last SG queue in the list of
6976 * allocated SG queues. If there are more
6977 * SG elements than will fit in the allocated
6978 * queues, then set the QCSG_SG_XFER_MORE flag.
6979 */
6980 if (scsiq->remain_sg_entry_cnt != 0) {
6981 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
6982 } else {
6983 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
6984 }
6985 /* equals sg_entry_cnt * 2 */
6986 sg_list_dwords = sg_entry_cnt << 1;
6987 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
6988 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
6989 sg_entry_cnt = 0;
6990 }
6991
6992 scsi_sg_q.q_no = next_qp;
6993 AscMemWordCopyPtrToLram(iop_base,
6994 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
6995 (uchar *)&scsi_sg_q,
6996 sizeof(ASC_SG_LIST_Q) >> 1);
6997
6998 AscMemDWordCopyPtrToLram(iop_base,
6999 q_addr + ASC_SGQ_LIST_BEG,
7000 (uchar *)&sg_head->
7001 sg_list[scsiq->next_sg_index],
7002 sg_list_dwords);
7003
7004 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
7005
7006 /*
7007 * If the just completed SG queue contained the
7008 * last SG element, then no more SG queues need
7009 * to be written.
7010 */
7011 if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
7012 break;
7013 }
7014
7015 next_qp = AscReadLramByte(iop_base,
7016 (ushort)(q_addr +
7017 ASC_SCSIQ_B_FWD));
7018 q_addr = ASC_QNO_TO_QADDR(next_qp);
7019 }
7020
7021 /*
7022 * Clear the halt condition so the RISC will be restarted
7023 * after the return.
7024 */
7025 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
7026 return (0);
7027 }
7028 #endif /* CC_VERY_LONG_SG_LIST */
7029 return (0);
7030 }
7031
7032 /*
7033 * void
7034 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
7035 *
7036 * Calling/Exit State:
7037 * none
7038 *
7039 * Description:
7040 * Input an ASC_QDONE_INFO structure from the chip
7041 */
7042 static void
7043 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
7044 {
7045 int i;
7046 ushort word;
7047
7048 AscSetChipLramAddr(iop_base, s_addr);
7049 for (i = 0; i < 2 * words; i += 2) {
7050 if (i == 10) {
7051 continue;
7052 }
7053 word = inpw(iop_base + IOP_RAM_DATA);
7054 inbuf[i] = word & 0xff;
7055 inbuf[i + 1] = (word >> 8) & 0xff;
7056 }
7057 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
7058 }
7059
7060 static uchar
7061 _AscCopyLramScsiDoneQ(PortAddr iop_base,
7062 ushort q_addr,
7063 ASC_QDONE_INFO *scsiq, ASC_DCNT max_dma_count)
7064 {
7065 ushort _val;
7066 uchar sg_queue_cnt;
7067
7068 DvcGetQinfo(iop_base,
7069 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
7070 (uchar *)scsiq,
7071 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
7072
7073 _val = AscReadLramWord(iop_base,
7074 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
7075 scsiq->q_status = (uchar)_val;
7076 scsiq->q_no = (uchar)(_val >> 8);
7077 _val = AscReadLramWord(iop_base,
7078 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
7079 scsiq->cntl = (uchar)_val;
7080 sg_queue_cnt = (uchar)(_val >> 8);
7081 _val = AscReadLramWord(iop_base,
7082 (ushort)(q_addr +
7083 (ushort)ASC_SCSIQ_B_SENSE_LEN));
7084 scsiq->sense_len = (uchar)_val;
7085 scsiq->extra_bytes = (uchar)(_val >> 8);
7086
7087 /*
7088 * Read high word of remain bytes from alternate location.
7089 */
7090 scsiq->remain_bytes = (((ADV_DCNT)AscReadLramWord(iop_base,
7091 (ushort)(q_addr +
7092 (ushort)
7093 ASC_SCSIQ_W_ALT_DC1)))
7094 << 16);
7095 /*
7096 * Read low word of remain bytes from original location.
7097 */
7098 scsiq->remain_bytes += AscReadLramWord(iop_base,
7099 (ushort)(q_addr + (ushort)
7100 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
7101
7102 scsiq->remain_bytes &= max_dma_count;
7103 return sg_queue_cnt;
7104 }
7105
7106 /*
7107 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
7108 *
7109 * Interrupt callback function for the Narrow SCSI Asc Library.
7110 */
7111 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
7112 {
7113 struct asc_board *boardp;
7114 struct scsi_cmnd *scp;
7115 struct Scsi_Host *shost;
7116
7117 ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
7118 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
7119
7120 scp = advansys_srb_to_ptr(asc_dvc_varp, qdonep->d2.srb_ptr);
7121 if (!scp)
7122 return;
7123
7124 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
7125
7126 shost = scp->device->host;
7127 ASC_STATS(shost, callback);
7128 ASC_DBG(1, "shost 0x%p\n", shost);
7129
7130 boardp = shost_priv(shost);
7131 BUG_ON(asc_dvc_varp != &boardp->dvc_var.asc_dvc_var);
7132
7133 dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
7134 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7135 /*
7136 * 'qdonep' contains the command's ending status.
7137 */
7138 switch (qdonep->d3.done_stat) {
7139 case QD_NO_ERROR:
7140 ASC_DBG(2, "QD_NO_ERROR\n");
7141 scp->result = 0;
7142
7143 /*
7144 * Check for an underrun condition.
7145 *
7146 * If there was no error and an underrun condition, then
7147 * return the number of underrun bytes.
7148 */
7149 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 &&
7150 qdonep->remain_bytes <= scsi_bufflen(scp)) {
7151 ASC_DBG(1, "underrun condition %u bytes\n",
7152 (unsigned)qdonep->remain_bytes);
7153 scsi_set_resid(scp, qdonep->remain_bytes);
7154 }
7155 break;
7156
7157 case QD_WITH_ERROR:
7158 ASC_DBG(2, "QD_WITH_ERROR\n");
7159 switch (qdonep->d3.host_stat) {
7160 case QHSTA_NO_ERROR:
7161 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
7162 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
7163 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
7164 SCSI_SENSE_BUFFERSIZE);
7165 /*
7166 * Note: The 'status_byte()' macro used by
7167 * target drivers defined in scsi.h shifts the
7168 * status byte returned by host drivers right
7169 * by 1 bit. This is why target drivers also
7170 * use right shifted status byte definitions.
7171 * For instance target drivers use
7172 * CHECK_CONDITION, defined to 0x1, instead of
7173 * the SCSI defined check condition value of
7174 * 0x2. Host drivers are supposed to return
7175 * the status byte as it is defined by SCSI.
7176 */
7177 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
7178 STATUS_BYTE(qdonep->d3.scsi_stat);
7179 } else {
7180 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
7181 }
7182 break;
7183
7184 default:
7185 /* QHSTA error occurred */
7186 ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
7187 scp->result = HOST_BYTE(DID_BAD_TARGET);
7188 break;
7189 }
7190 break;
7191
7192 case QD_ABORTED_BY_HOST:
7193 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
7194 scp->result =
7195 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
7196 scsi_msg) |
7197 STATUS_BYTE(qdonep->d3.scsi_stat);
7198 break;
7199
7200 default:
7201 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
7202 scp->result =
7203 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
7204 scsi_msg) |
7205 STATUS_BYTE(qdonep->d3.scsi_stat);
7206 break;
7207 }
7208
7209 /*
7210 * If the 'init_tidmask' bit isn't already set for the target and the
7211 * current request finished normally, then set the bit for the target
7212 * to indicate that a device is present.
7213 */
7214 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
7215 qdonep->d3.done_stat == QD_NO_ERROR &&
7216 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
7217 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
7218 }
7219
7220 asc_scsi_done(scp);
7221 }
7222
7223 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
7224 {
7225 uchar next_qp;
7226 uchar n_q_used;
7227 uchar sg_list_qp;
7228 uchar sg_queue_cnt;
7229 uchar q_cnt;
7230 uchar done_q_tail;
7231 uchar tid_no;
7232 ASC_SCSI_BIT_ID_TYPE scsi_busy;
7233 ASC_SCSI_BIT_ID_TYPE target_id;
7234 PortAddr iop_base;
7235 ushort q_addr;
7236 ushort sg_q_addr;
7237 uchar cur_target_qng;
7238 ASC_QDONE_INFO scsiq_buf;
7239 ASC_QDONE_INFO *scsiq;
7240 int false_overrun;
7241
7242 iop_base = asc_dvc->iop_base;
7243 n_q_used = 1;
7244 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
7245 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
7246 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
7247 next_qp = AscReadLramByte(iop_base,
7248 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
7249 if (next_qp != ASC_QLINK_END) {
7250 AscPutVarDoneQTail(iop_base, next_qp);
7251 q_addr = ASC_QNO_TO_QADDR(next_qp);
7252 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
7253 asc_dvc->max_dma_count);
7254 AscWriteLramByte(iop_base,
7255 (ushort)(q_addr +
7256 (ushort)ASC_SCSIQ_B_STATUS),
7257 (uchar)(scsiq->
7258 q_status & (uchar)~(QS_READY |
7259 QS_ABORTED)));
7260 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
7261 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
7262 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
7263 sg_q_addr = q_addr;
7264 sg_list_qp = next_qp;
7265 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
7266 sg_list_qp = AscReadLramByte(iop_base,
7267 (ushort)(sg_q_addr
7268 + (ushort)
7269 ASC_SCSIQ_B_FWD));
7270 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
7271 if (sg_list_qp == ASC_QLINK_END) {
7272 AscSetLibErrorCode(asc_dvc,
7273 ASCQ_ERR_SG_Q_LINKS);
7274 scsiq->d3.done_stat = QD_WITH_ERROR;
7275 scsiq->d3.host_stat =
7276 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
7277 goto FATAL_ERR_QDONE;
7278 }
7279 AscWriteLramByte(iop_base,
7280 (ushort)(sg_q_addr + (ushort)
7281 ASC_SCSIQ_B_STATUS),
7282 QS_FREE);
7283 }
7284 n_q_used = sg_queue_cnt + 1;
7285 AscPutVarDoneQTail(iop_base, sg_list_qp);
7286 }
7287 if (asc_dvc->queue_full_or_busy & target_id) {
7288 cur_target_qng = AscReadLramByte(iop_base,
7289 (ushort)((ushort)
7290 ASC_QADR_BEG
7291 + (ushort)
7292 scsiq->d2.
7293 target_ix));
7294 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
7295 scsi_busy = AscReadLramByte(iop_base, (ushort)
7296 ASCV_SCSIBUSY_B);
7297 scsi_busy &= ~target_id;
7298 AscWriteLramByte(iop_base,
7299 (ushort)ASCV_SCSIBUSY_B,
7300 scsi_busy);
7301 asc_dvc->queue_full_or_busy &= ~target_id;
7302 }
7303 }
7304 if (asc_dvc->cur_total_qng >= n_q_used) {
7305 asc_dvc->cur_total_qng -= n_q_used;
7306 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
7307 asc_dvc->cur_dvc_qng[tid_no]--;
7308 }
7309 } else {
7310 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
7311 scsiq->d3.done_stat = QD_WITH_ERROR;
7312 goto FATAL_ERR_QDONE;
7313 }
7314 if ((scsiq->d2.srb_ptr == 0UL) ||
7315 ((scsiq->q_status & QS_ABORTED) != 0)) {
7316 return (0x11);
7317 } else if (scsiq->q_status == QS_DONE) {
7318 false_overrun = FALSE;
7319 if (scsiq->extra_bytes != 0) {
7320 scsiq->remain_bytes +=
7321 (ADV_DCNT)scsiq->extra_bytes;
7322 }
7323 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
7324 if (scsiq->d3.host_stat ==
7325 QHSTA_M_DATA_OVER_RUN) {
7326 if ((scsiq->
7327 cntl & (QC_DATA_IN | QC_DATA_OUT))
7328 == 0) {
7329 scsiq->d3.done_stat =
7330 QD_NO_ERROR;
7331 scsiq->d3.host_stat =
7332 QHSTA_NO_ERROR;
7333 } else if (false_overrun) {
7334 scsiq->d3.done_stat =
7335 QD_NO_ERROR;
7336 scsiq->d3.host_stat =
7337 QHSTA_NO_ERROR;
7338 }
7339 } else if (scsiq->d3.host_stat ==
7340 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
7341 AscStopChip(iop_base);
7342 AscSetChipControl(iop_base,
7343 (uchar)(CC_SCSI_RESET
7344 | CC_HALT));
7345 udelay(60);
7346 AscSetChipControl(iop_base, CC_HALT);
7347 AscSetChipStatus(iop_base,
7348 CIW_CLR_SCSI_RESET_INT);
7349 AscSetChipStatus(iop_base, 0);
7350 AscSetChipControl(iop_base, 0);
7351 }
7352 }
7353 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7354 asc_isr_callback(asc_dvc, scsiq);
7355 } else {
7356 if ((AscReadLramByte(iop_base,
7357 (ushort)(q_addr + (ushort)
7358 ASC_SCSIQ_CDB_BEG))
7359 == START_STOP)) {
7360 asc_dvc->unit_not_ready &= ~target_id;
7361 if (scsiq->d3.done_stat != QD_NO_ERROR) {
7362 asc_dvc->start_motor &=
7363 ~target_id;
7364 }
7365 }
7366 }
7367 return (1);
7368 } else {
7369 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
7370 FATAL_ERR_QDONE:
7371 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7372 asc_isr_callback(asc_dvc, scsiq);
7373 }
7374 return (0x80);
7375 }
7376 }
7377 return (0);
7378 }
7379
7380 static int AscISR(ASC_DVC_VAR *asc_dvc)
7381 {
7382 ASC_CS_TYPE chipstat;
7383 PortAddr iop_base;
7384 ushort saved_ram_addr;
7385 uchar ctrl_reg;
7386 uchar saved_ctrl_reg;
7387 int int_pending;
7388 int status;
7389 uchar host_flag;
7390
7391 iop_base = asc_dvc->iop_base;
7392 int_pending = FALSE;
7393
7394 if (AscIsIntPending(iop_base) == 0)
7395 return int_pending;
7396
7397 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
7398 return ERR;
7399 }
7400 if (asc_dvc->in_critical_cnt != 0) {
7401 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
7402 return ERR;
7403 }
7404 if (asc_dvc->is_in_int) {
7405 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
7406 return ERR;
7407 }
7408 asc_dvc->is_in_int = TRUE;
7409 ctrl_reg = AscGetChipControl(iop_base);
7410 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
7411 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
7412 chipstat = AscGetChipStatus(iop_base);
7413 if (chipstat & CSW_SCSI_RESET_LATCH) {
7414 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
7415 int i = 10;
7416 int_pending = TRUE;
7417 asc_dvc->sdtr_done = 0;
7418 saved_ctrl_reg &= (uchar)(~CC_HALT);
7419 while ((AscGetChipStatus(iop_base) &
7420 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
7421 mdelay(100);
7422 }
7423 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
7424 AscSetChipControl(iop_base, CC_HALT);
7425 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
7426 AscSetChipStatus(iop_base, 0);
7427 chipstat = AscGetChipStatus(iop_base);
7428 }
7429 }
7430 saved_ram_addr = AscGetChipLramAddr(iop_base);
7431 host_flag = AscReadLramByte(iop_base,
7432 ASCV_HOST_FLAG_B) &
7433 (uchar)(~ASC_HOST_FLAG_IN_ISR);
7434 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
7435 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
7436 if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
7437 AscAckInterrupt(iop_base);
7438 int_pending = TRUE;
7439 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
7440 if (AscIsrChipHalted(asc_dvc) == ERR) {
7441 goto ISR_REPORT_QDONE_FATAL_ERROR;
7442 } else {
7443 saved_ctrl_reg &= (uchar)(~CC_HALT);
7444 }
7445 } else {
7446 ISR_REPORT_QDONE_FATAL_ERROR:
7447 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
7448 while (((status =
7449 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
7450 }
7451 } else {
7452 do {
7453 if ((status =
7454 AscIsrQDone(asc_dvc)) == 1) {
7455 break;
7456 }
7457 } while (status == 0x11);
7458 }
7459 if ((status & 0x80) != 0)
7460 int_pending = ERR;
7461 }
7462 }
7463 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
7464 AscSetChipLramAddr(iop_base, saved_ram_addr);
7465 AscSetChipControl(iop_base, saved_ctrl_reg);
7466 asc_dvc->is_in_int = FALSE;
7467 return int_pending;
7468 }
7469
7470 /*
7471 * advansys_reset()
7472 *
7473 * Reset the bus associated with the command 'scp'.
7474 *
7475 * This function runs its own thread. Interrupts must be blocked but
7476 * sleeping is allowed and no locking other than for host structures is
7477 * required. Returns SUCCESS or FAILED.
7478 */
7479 static int advansys_reset(struct scsi_cmnd *scp)
7480 {
7481 struct Scsi_Host *shost = scp->device->host;
7482 struct asc_board *boardp = shost_priv(shost);
7483 unsigned long flags;
7484 int status;
7485 int ret = SUCCESS;
7486
7487 ASC_DBG(1, "0x%p\n", scp);
7488
7489 ASC_STATS(shost, reset);
7490
7491 scmd_printk(KERN_INFO, scp, "SCSI bus reset started...\n");
7492
7493 if (ASC_NARROW_BOARD(boardp)) {
7494 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7495
7496 /* Reset the chip and SCSI bus. */
7497 ASC_DBG(1, "before AscInitAsc1000Driver()\n");
7498 status = AscInitAsc1000Driver(asc_dvc);
7499
7500 /* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */
7501 if (asc_dvc->err_code || !asc_dvc->overrun_dma) {
7502 scmd_printk(KERN_INFO, scp, "SCSI bus reset error: "
7503 "0x%x, status: 0x%x\n", asc_dvc->err_code,
7504 status);
7505 ret = FAILED;
7506 } else if (status) {
7507 scmd_printk(KERN_INFO, scp, "SCSI bus reset warning: "
7508 "0x%x\n", status);
7509 } else {
7510 scmd_printk(KERN_INFO, scp, "SCSI bus reset "
7511 "successful\n");
7512 }
7513
7514 ASC_DBG(1, "after AscInitAsc1000Driver()\n");
7515 spin_lock_irqsave(shost->host_lock, flags);
7516 } else {
7517 /*
7518 * If the suggest reset bus flags are set, then reset the bus.
7519 * Otherwise only reset the device.
7520 */
7521 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
7522
7523 /*
7524 * Reset the target's SCSI bus.
7525 */
7526 ASC_DBG(1, "before AdvResetChipAndSB()\n");
7527 switch (AdvResetChipAndSB(adv_dvc)) {
7528 case ASC_TRUE:
7529 scmd_printk(KERN_INFO, scp, "SCSI bus reset "
7530 "successful\n");
7531 break;
7532 case ASC_FALSE:
7533 default:
7534 scmd_printk(KERN_INFO, scp, "SCSI bus reset error\n");
7535 ret = FAILED;
7536 break;
7537 }
7538 spin_lock_irqsave(shost->host_lock, flags);
7539 AdvISR(adv_dvc);
7540 }
7541
7542 /* Save the time of the most recently completed reset. */
7543 boardp->last_reset = jiffies;
7544 spin_unlock_irqrestore(shost->host_lock, flags);
7545
7546 ASC_DBG(1, "ret %d\n", ret);
7547
7548 return ret;
7549 }
7550
7551 /*
7552 * advansys_biosparam()
7553 *
7554 * Translate disk drive geometry if the "BIOS greater than 1 GB"
7555 * support is enabled for a drive.
7556 *
7557 * ip (information pointer) is an int array with the following definition:
7558 * ip[0]: heads
7559 * ip[1]: sectors
7560 * ip[2]: cylinders
7561 */
7562 static int
7563 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
7564 sector_t capacity, int ip[])
7565 {
7566 struct asc_board *boardp = shost_priv(sdev->host);
7567
7568 ASC_DBG(1, "begin\n");
7569 ASC_STATS(sdev->host, biosparam);
7570 if (ASC_NARROW_BOARD(boardp)) {
7571 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
7572 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
7573 ip[0] = 255;
7574 ip[1] = 63;
7575 } else {
7576 ip[0] = 64;
7577 ip[1] = 32;
7578 }
7579 } else {
7580 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
7581 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
7582 ip[0] = 255;
7583 ip[1] = 63;
7584 } else {
7585 ip[0] = 64;
7586 ip[1] = 32;
7587 }
7588 }
7589 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
7590 ASC_DBG(1, "end\n");
7591 return 0;
7592 }
7593
7594 /*
7595 * First-level interrupt handler.
7596 *
7597 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
7598 */
7599 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
7600 {
7601 struct Scsi_Host *shost = dev_id;
7602 struct asc_board *boardp = shost_priv(shost);
7603 irqreturn_t result = IRQ_NONE;
7604
7605 ASC_DBG(2, "boardp 0x%p\n", boardp);
7606 spin_lock(shost->host_lock);
7607 if (ASC_NARROW_BOARD(boardp)) {
7608 if (AscIsIntPending(shost->io_port)) {
7609 result = IRQ_HANDLED;
7610 ASC_STATS(shost, interrupt);
7611 ASC_DBG(1, "before AscISR()\n");
7612 AscISR(&boardp->dvc_var.asc_dvc_var);
7613 }
7614 } else {
7615 ASC_DBG(1, "before AdvISR()\n");
7616 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
7617 result = IRQ_HANDLED;
7618 ASC_STATS(shost, interrupt);
7619 }
7620 }
7621 spin_unlock(shost->host_lock);
7622
7623 ASC_DBG(1, "end\n");
7624 return result;
7625 }
7626
7627 static int AscHostReqRiscHalt(PortAddr iop_base)
7628 {
7629 int count = 0;
7630 int sta = 0;
7631 uchar saved_stop_code;
7632
7633 if (AscIsChipHalted(iop_base))
7634 return (1);
7635 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
7636 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
7637 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
7638 do {
7639 if (AscIsChipHalted(iop_base)) {
7640 sta = 1;
7641 break;
7642 }
7643 mdelay(100);
7644 } while (count++ < 20);
7645 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
7646 return (sta);
7647 }
7648
7649 static int
7650 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
7651 {
7652 int sta = FALSE;
7653
7654 if (AscHostReqRiscHalt(iop_base)) {
7655 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
7656 AscStartChip(iop_base);
7657 }
7658 return sta;
7659 }
7660
7661 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
7662 {
7663 char type = sdev->type;
7664 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
7665
7666 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
7667 return;
7668 if (asc_dvc->init_sdtr & tid_bits)
7669 return;
7670
7671 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
7672 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
7673
7674 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
7675 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
7676 (type == TYPE_ROM) || (type == TYPE_TAPE))
7677 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
7678
7679 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
7680 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
7681 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
7682 }
7683
7684 static void
7685 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
7686 {
7687 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
7688 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
7689
7690 if (sdev->lun == 0) {
7691 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
7692 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
7693 asc_dvc->init_sdtr |= tid_bit;
7694 } else {
7695 asc_dvc->init_sdtr &= ~tid_bit;
7696 }
7697
7698 if (orig_init_sdtr != asc_dvc->init_sdtr)
7699 AscAsyncFix(asc_dvc, sdev);
7700 }
7701
7702 if (sdev->tagged_supported) {
7703 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
7704 if (sdev->lun == 0) {
7705 asc_dvc->cfg->can_tagged_qng |= tid_bit;
7706 asc_dvc->use_tagged_qng |= tid_bit;
7707 }
7708 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
7709 asc_dvc->max_dvc_qng[sdev->id]);
7710 }
7711 } else {
7712 if (sdev->lun == 0) {
7713 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
7714 asc_dvc->use_tagged_qng &= ~tid_bit;
7715 }
7716 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
7717 }
7718
7719 if ((sdev->lun == 0) &&
7720 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
7721 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
7722 asc_dvc->cfg->disc_enable);
7723 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
7724 asc_dvc->use_tagged_qng);
7725 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
7726 asc_dvc->cfg->can_tagged_qng);
7727
7728 asc_dvc->max_dvc_qng[sdev->id] =
7729 asc_dvc->cfg->max_tag_qng[sdev->id];
7730 AscWriteLramByte(asc_dvc->iop_base,
7731 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
7732 asc_dvc->max_dvc_qng[sdev->id]);
7733 }
7734 }
7735
7736 /*
7737 * Wide Transfers
7738 *
7739 * If the EEPROM enabled WDTR for the device and the device supports wide
7740 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
7741 * write the new value to the microcode.
7742 */
7743 static void
7744 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
7745 {
7746 unsigned short cfg_word;
7747 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7748 if ((cfg_word & tidmask) != 0)
7749 return;
7750
7751 cfg_word |= tidmask;
7752 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7753
7754 /*
7755 * Clear the microcode SDTR and WDTR negotiation done indicators for
7756 * the target to cause it to negotiate with the new setting set above.
7757 * WDTR when accepted causes the target to enter asynchronous mode, so
7758 * SDTR must be negotiated.
7759 */
7760 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7761 cfg_word &= ~tidmask;
7762 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7763 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7764 cfg_word &= ~tidmask;
7765 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7766 }
7767
7768 /*
7769 * Synchronous Transfers
7770 *
7771 * If the EEPROM enabled SDTR for the device and the device
7772 * supports synchronous transfers, then turn on the device's
7773 * 'sdtr_able' bit. Write the new value to the microcode.
7774 */
7775 static void
7776 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
7777 {
7778 unsigned short cfg_word;
7779 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7780 if ((cfg_word & tidmask) != 0)
7781 return;
7782
7783 cfg_word |= tidmask;
7784 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7785
7786 /*
7787 * Clear the microcode "SDTR negotiation" done indicator for the
7788 * target to cause it to negotiate with the new setting set above.
7789 */
7790 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7791 cfg_word &= ~tidmask;
7792 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7793 }
7794
7795 /*
7796 * PPR (Parallel Protocol Request) Capable
7797 *
7798 * If the device supports DT mode, then it must be PPR capable.
7799 * The PPR message will be used in place of the SDTR and WDTR
7800 * messages to negotiate synchronous speed and offset, transfer
7801 * width, and protocol options.
7802 */
7803 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
7804 AdvPortAddr iop_base, unsigned short tidmask)
7805 {
7806 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7807 adv_dvc->ppr_able |= tidmask;
7808 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7809 }
7810
7811 static void
7812 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
7813 {
7814 AdvPortAddr iop_base = adv_dvc->iop_base;
7815 unsigned short tidmask = 1 << sdev->id;
7816
7817 if (sdev->lun == 0) {
7818 /*
7819 * Handle WDTR, SDTR, and Tag Queuing. If the feature
7820 * is enabled in the EEPROM and the device supports the
7821 * feature, then enable it in the microcode.
7822 */
7823
7824 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
7825 advansys_wide_enable_wdtr(iop_base, tidmask);
7826 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
7827 advansys_wide_enable_sdtr(iop_base, tidmask);
7828 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
7829 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
7830
7831 /*
7832 * Tag Queuing is disabled for the BIOS which runs in polled
7833 * mode and would see no benefit from Tag Queuing. Also by
7834 * disabling Tag Queuing in the BIOS devices with Tag Queuing
7835 * bugs will at least work with the BIOS.
7836 */
7837 if ((adv_dvc->tagqng_able & tidmask) &&
7838 sdev->tagged_supported) {
7839 unsigned short cfg_word;
7840 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
7841 cfg_word |= tidmask;
7842 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7843 cfg_word);
7844 AdvWriteByteLram(iop_base,
7845 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
7846 adv_dvc->max_dvc_qng);
7847 }
7848 }
7849
7850 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported) {
7851 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
7852 adv_dvc->max_dvc_qng);
7853 } else {
7854 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
7855 }
7856 }
7857
7858 /*
7859 * Set the number of commands to queue per device for the
7860 * specified host adapter.
7861 */
7862 static int advansys_slave_configure(struct scsi_device *sdev)
7863 {
7864 struct asc_board *boardp = shost_priv(sdev->host);
7865
7866 if (ASC_NARROW_BOARD(boardp))
7867 advansys_narrow_slave_configure(sdev,
7868 &boardp->dvc_var.asc_dvc_var);
7869 else
7870 advansys_wide_slave_configure(sdev,
7871 &boardp->dvc_var.adv_dvc_var);
7872
7873 return 0;
7874 }
7875
7876 static __le32 advansys_get_sense_buffer_dma(struct scsi_cmnd *scp)
7877 {
7878 struct asc_board *board = shost_priv(scp->device->host);
7879 scp->SCp.dma_handle = dma_map_single(board->dev, scp->sense_buffer,
7880 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7881 dma_cache_sync(board->dev, scp->sense_buffer,
7882 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7883 return cpu_to_le32(scp->SCp.dma_handle);
7884 }
7885
7886 static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
7887 struct asc_scsi_q *asc_scsi_q)
7888 {
7889 struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7890 int use_sg;
7891
7892 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
7893
7894 /*
7895 * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
7896 */
7897 asc_scsi_q->q2.srb_ptr = advansys_ptr_to_srb(asc_dvc, scp);
7898 if (asc_scsi_q->q2.srb_ptr == BAD_SRB) {
7899 scp->result = HOST_BYTE(DID_SOFT_ERROR);
7900 return ASC_ERROR;
7901 }
7902
7903 /*
7904 * Build the ASC_SCSI_Q request.
7905 */
7906 asc_scsi_q->cdbptr = &scp->cmnd[0];
7907 asc_scsi_q->q2.cdb_len = scp->cmd_len;
7908 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
7909 asc_scsi_q->q1.target_lun = scp->device->lun;
7910 asc_scsi_q->q2.target_ix =
7911 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
7912 asc_scsi_q->q1.sense_addr = advansys_get_sense_buffer_dma(scp);
7913 asc_scsi_q->q1.sense_len = SCSI_SENSE_BUFFERSIZE;
7914
7915 /*
7916 * If there are any outstanding requests for the current target,
7917 * then every 255th request send an ORDERED request. This heuristic
7918 * tries to retain the benefit of request sorting while preventing
7919 * request starvation. 255 is the max number of tags or pending commands
7920 * a device may have outstanding.
7921 *
7922 * The request count is incremented below for every successfully
7923 * started request.
7924 *
7925 */
7926 if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) &&
7927 (boardp->reqcnt[scp->device->id] % 255) == 0) {
7928 asc_scsi_q->q2.tag_code = MSG_ORDERED_TAG;
7929 } else {
7930 asc_scsi_q->q2.tag_code = MSG_SIMPLE_TAG;
7931 }
7932
7933 /* Build ASC_SCSI_Q */
7934 use_sg = scsi_dma_map(scp);
7935 if (use_sg != 0) {
7936 int sgcnt;
7937 struct scatterlist *slp;
7938 struct asc_sg_head *asc_sg_head;
7939
7940 if (use_sg > scp->device->host->sg_tablesize) {
7941 scmd_printk(KERN_ERR, scp, "use_sg %d > "
7942 "sg_tablesize %d\n", use_sg,
7943 scp->device->host->sg_tablesize);
7944 scsi_dma_unmap(scp);
7945 scp->result = HOST_BYTE(DID_ERROR);
7946 return ASC_ERROR;
7947 }
7948
7949 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
7950 use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
7951 if (!asc_sg_head) {
7952 scsi_dma_unmap(scp);
7953 scp->result = HOST_BYTE(DID_SOFT_ERROR);
7954 return ASC_ERROR;
7955 }
7956
7957 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
7958 asc_scsi_q->sg_head = asc_sg_head;
7959 asc_scsi_q->q1.data_cnt = 0;
7960 asc_scsi_q->q1.data_addr = 0;
7961 /* This is a byte value, otherwise it would need to be swapped. */
7962 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
7963 ASC_STATS_ADD(scp->device->host, xfer_elem,
7964 asc_sg_head->entry_cnt);
7965
7966 /*
7967 * Convert scatter-gather list into ASC_SG_HEAD list.
7968 */
7969 scsi_for_each_sg(scp, slp, use_sg, sgcnt) {
7970 asc_sg_head->sg_list[sgcnt].addr =
7971 cpu_to_le32(sg_dma_address(slp));
7972 asc_sg_head->sg_list[sgcnt].bytes =
7973 cpu_to_le32(sg_dma_len(slp));
7974 ASC_STATS_ADD(scp->device->host, xfer_sect,
7975 DIV_ROUND_UP(sg_dma_len(slp), 512));
7976 }
7977 }
7978
7979 ASC_STATS(scp->device->host, xfer_cnt);
7980
7981 ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q);
7982 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
7983
7984 return ASC_NOERROR;
7985 }
7986
7987 /*
7988 * Build scatter-gather list for Adv Library (Wide Board).
7989 *
7990 * Additional ADV_SG_BLOCK structures will need to be allocated
7991 * if the total number of scatter-gather elements exceeds
7992 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
7993 * assumed to be physically contiguous.
7994 *
7995 * Return:
7996 * ADV_SUCCESS(1) - SG List successfully created
7997 * ADV_ERROR(-1) - SG List creation failed
7998 */
7999 static int
8000 adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp, struct scsi_cmnd *scp,
8001 int use_sg)
8002 {
8003 adv_sgblk_t *sgblkp;
8004 ADV_SCSI_REQ_Q *scsiqp;
8005 struct scatterlist *slp;
8006 int sg_elem_cnt;
8007 ADV_SG_BLOCK *sg_block, *prev_sg_block;
8008 ADV_PADDR sg_block_paddr;
8009 int i;
8010
8011 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
8012 slp = scsi_sglist(scp);
8013 sg_elem_cnt = use_sg;
8014 prev_sg_block = NULL;
8015 reqp->sgblkp = NULL;
8016
8017 for (;;) {
8018 /*
8019 * Allocate a 'adv_sgblk_t' structure from the board free
8020 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
8021 * (15) scatter-gather elements.
8022 */
8023 if ((sgblkp = boardp->adv_sgblkp) == NULL) {
8024 ASC_DBG(1, "no free adv_sgblk_t\n");
8025 ASC_STATS(scp->device->host, adv_build_nosg);
8026
8027 /*
8028 * Allocation failed. Free 'adv_sgblk_t' structures
8029 * already allocated for the request.
8030 */
8031 while ((sgblkp = reqp->sgblkp) != NULL) {
8032 /* Remove 'sgblkp' from the request list. */
8033 reqp->sgblkp = sgblkp->next_sgblkp;
8034
8035 /* Add 'sgblkp' to the board free list. */
8036 sgblkp->next_sgblkp = boardp->adv_sgblkp;
8037 boardp->adv_sgblkp = sgblkp;
8038 }
8039 return ASC_BUSY;
8040 }
8041
8042 /* Complete 'adv_sgblk_t' board allocation. */
8043 boardp->adv_sgblkp = sgblkp->next_sgblkp;
8044 sgblkp->next_sgblkp = NULL;
8045
8046 /*
8047 * Get 8 byte aligned virtual and physical addresses
8048 * for the allocated ADV_SG_BLOCK structure.
8049 */
8050 sg_block = (ADV_SG_BLOCK *)ADV_8BALIGN(&sgblkp->sg_block);
8051 sg_block_paddr = virt_to_bus(sg_block);
8052
8053 /*
8054 * Check if this is the first 'adv_sgblk_t' for the
8055 * request.
8056 */
8057 if (reqp->sgblkp == NULL) {
8058 /* Request's first scatter-gather block. */
8059 reqp->sgblkp = sgblkp;
8060
8061 /*
8062 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
8063 * address pointers.
8064 */
8065 scsiqp->sg_list_ptr = sg_block;
8066 scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
8067 } else {
8068 /* Request's second or later scatter-gather block. */
8069 sgblkp->next_sgblkp = reqp->sgblkp;
8070 reqp->sgblkp = sgblkp;
8071
8072 /*
8073 * Point the previous ADV_SG_BLOCK structure to
8074 * the newly allocated ADV_SG_BLOCK structure.
8075 */
8076 prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
8077 }
8078
8079 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
8080 sg_block->sg_list[i].sg_addr =
8081 cpu_to_le32(sg_dma_address(slp));
8082 sg_block->sg_list[i].sg_count =
8083 cpu_to_le32(sg_dma_len(slp));
8084 ASC_STATS_ADD(scp->device->host, xfer_sect,
8085 DIV_ROUND_UP(sg_dma_len(slp), 512));
8086
8087 if (--sg_elem_cnt == 0) { /* Last ADV_SG_BLOCK and scatter-gather entry. */
8088 sg_block->sg_cnt = i + 1;
8089 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
8090 return ADV_SUCCESS;
8091 }
8092 slp++;
8093 }
8094 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
8095 prev_sg_block = sg_block;
8096 }
8097 }
8098
8099 /*
8100 * Build a request structure for the Adv Library (Wide Board).
8101 *
8102 * If an adv_req_t can not be allocated to issue the request,
8103 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
8104 *
8105 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
8106 * microcode for DMA addresses or math operations are byte swapped
8107 * to little-endian order.
8108 */
8109 static int
8110 adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
8111 ADV_SCSI_REQ_Q **adv_scsiqpp)
8112 {
8113 adv_req_t *reqp;
8114 ADV_SCSI_REQ_Q *scsiqp;
8115 int i;
8116 int ret;
8117 int use_sg;
8118
8119 /*
8120 * Allocate an adv_req_t structure from the board to execute
8121 * the command.
8122 */
8123 if (boardp->adv_reqp == NULL) {
8124 ASC_DBG(1, "no free adv_req_t\n");
8125 ASC_STATS(scp->device->host, adv_build_noreq);
8126 return ASC_BUSY;
8127 } else {
8128 reqp = boardp->adv_reqp;
8129 boardp->adv_reqp = reqp->next_reqp;
8130 reqp->next_reqp = NULL;
8131 }
8132
8133 /*
8134 * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
8135 */
8136 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
8137
8138 /*
8139 * Initialize the structure.
8140 */
8141 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
8142
8143 /*
8144 * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
8145 */
8146 scsiqp->srb_ptr = ADV_VADDR_TO_U32(reqp);
8147
8148 /*
8149 * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
8150 */
8151 reqp->cmndp = scp;
8152
8153 /*
8154 * Build the ADV_SCSI_REQ_Q request.
8155 */
8156
8157 /* Set CDB length and copy it to the request structure. */
8158 scsiqp->cdb_len = scp->cmd_len;
8159 /* Copy first 12 CDB bytes to cdb[]. */
8160 for (i = 0; i < scp->cmd_len && i < 12; i++) {
8161 scsiqp->cdb[i] = scp->cmnd[i];
8162 }
8163 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
8164 for (; i < scp->cmd_len; i++) {
8165 scsiqp->cdb16[i - 12] = scp->cmnd[i];
8166 }
8167
8168 scsiqp->target_id = scp->device->id;
8169 scsiqp->target_lun = scp->device->lun;
8170
8171 scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
8172 scsiqp->sense_len = SCSI_SENSE_BUFFERSIZE;
8173
8174 /* Build ADV_SCSI_REQ_Q */
8175
8176 use_sg = scsi_dma_map(scp);
8177 if (use_sg == 0) {
8178 /* Zero-length transfer */
8179 reqp->sgblkp = NULL;
8180 scsiqp->data_cnt = 0;
8181 scsiqp->vdata_addr = NULL;
8182
8183 scsiqp->data_addr = 0;
8184 scsiqp->sg_list_ptr = NULL;
8185 scsiqp->sg_real_addr = 0;
8186 } else {
8187 if (use_sg > ADV_MAX_SG_LIST) {
8188 scmd_printk(KERN_ERR, scp, "use_sg %d > "
8189 "ADV_MAX_SG_LIST %d\n", use_sg,
8190 scp->device->host->sg_tablesize);
8191 scsi_dma_unmap(scp);
8192 scp->result = HOST_BYTE(DID_ERROR);
8193
8194 /*
8195 * Free the 'adv_req_t' structure by adding it back
8196 * to the board free list.
8197 */
8198 reqp->next_reqp = boardp->adv_reqp;
8199 boardp->adv_reqp = reqp;
8200
8201 return ASC_ERROR;
8202 }
8203
8204 scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp));
8205
8206 ret = adv_get_sglist(boardp, reqp, scp, use_sg);
8207 if (ret != ADV_SUCCESS) {
8208 /*
8209 * Free the adv_req_t structure by adding it back to
8210 * the board free list.
8211 */
8212 reqp->next_reqp = boardp->adv_reqp;
8213 boardp->adv_reqp = reqp;
8214
8215 return ret;
8216 }
8217
8218 ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg);
8219 }
8220
8221 ASC_STATS(scp->device->host, xfer_cnt);
8222
8223 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
8224 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
8225
8226 *adv_scsiqpp = scsiqp;
8227
8228 return ASC_NOERROR;
8229 }
8230
8231 static int AscSgListToQueue(int sg_list)
8232 {
8233 int n_sg_list_qs;
8234
8235 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
8236 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
8237 n_sg_list_qs++;
8238 return n_sg_list_qs + 1;
8239 }
8240
8241 static uint
8242 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
8243 {
8244 uint cur_used_qs;
8245 uint cur_free_qs;
8246 ASC_SCSI_BIT_ID_TYPE target_id;
8247 uchar tid_no;
8248
8249 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
8250 tid_no = ASC_TIX_TO_TID(target_ix);
8251 if ((asc_dvc->unit_not_ready & target_id) ||
8252 (asc_dvc->queue_full_or_busy & target_id)) {
8253 return 0;
8254 }
8255 if (n_qs == 1) {
8256 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8257 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
8258 } else {
8259 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8260 (uint) ASC_MIN_FREE_Q;
8261 }
8262 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
8263 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
8264 if (asc_dvc->cur_dvc_qng[tid_no] >=
8265 asc_dvc->max_dvc_qng[tid_no]) {
8266 return 0;
8267 }
8268 return cur_free_qs;
8269 }
8270 if (n_qs > 1) {
8271 if ((n_qs > asc_dvc->last_q_shortage)
8272 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
8273 asc_dvc->last_q_shortage = n_qs;
8274 }
8275 }
8276 return 0;
8277 }
8278
8279 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
8280 {
8281 ushort q_addr;
8282 uchar next_qp;
8283 uchar q_status;
8284
8285 q_addr = ASC_QNO_TO_QADDR(free_q_head);
8286 q_status = (uchar)AscReadLramByte(iop_base,
8287 (ushort)(q_addr +
8288 ASC_SCSIQ_B_STATUS));
8289 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
8290 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
8291 return next_qp;
8292 return ASC_QLINK_END;
8293 }
8294
8295 static uchar
8296 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
8297 {
8298 uchar i;
8299
8300 for (i = 0; i < n_free_q; i++) {
8301 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
8302 if (free_q_head == ASC_QLINK_END)
8303 break;
8304 }
8305 return free_q_head;
8306 }
8307
8308 /*
8309 * void
8310 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8311 *
8312 * Calling/Exit State:
8313 * none
8314 *
8315 * Description:
8316 * Output an ASC_SCSI_Q structure to the chip
8317 */
8318 static void
8319 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8320 {
8321 int i;
8322
8323 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
8324 AscSetChipLramAddr(iop_base, s_addr);
8325 for (i = 0; i < 2 * words; i += 2) {
8326 if (i == 4 || i == 20) {
8327 continue;
8328 }
8329 outpw(iop_base + IOP_RAM_DATA,
8330 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
8331 }
8332 }
8333
8334 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8335 {
8336 ushort q_addr;
8337 uchar tid_no;
8338 uchar sdtr_data;
8339 uchar syn_period_ix;
8340 uchar syn_offset;
8341 PortAddr iop_base;
8342
8343 iop_base = asc_dvc->iop_base;
8344 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
8345 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
8346 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
8347 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8348 syn_period_ix =
8349 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
8350 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
8351 AscMsgOutSDTR(asc_dvc,
8352 asc_dvc->sdtr_period_tbl[syn_period_ix],
8353 syn_offset);
8354 scsiq->q1.cntl |= QC_MSG_OUT;
8355 }
8356 q_addr = ASC_QNO_TO_QADDR(q_no);
8357 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
8358 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
8359 }
8360 scsiq->q1.status = QS_FREE;
8361 AscMemWordCopyPtrToLram(iop_base,
8362 q_addr + ASC_SCSIQ_CDB_BEG,
8363 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
8364
8365 DvcPutScsiQ(iop_base,
8366 q_addr + ASC_SCSIQ_CPY_BEG,
8367 (uchar *)&scsiq->q1.cntl,
8368 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
8369 AscWriteLramWord(iop_base,
8370 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
8371 (ushort)(((ushort)scsiq->q1.
8372 q_no << 8) | (ushort)QS_READY));
8373 return 1;
8374 }
8375
8376 static int
8377 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8378 {
8379 int sta;
8380 int i;
8381 ASC_SG_HEAD *sg_head;
8382 ASC_SG_LIST_Q scsi_sg_q;
8383 ASC_DCNT saved_data_addr;
8384 ASC_DCNT saved_data_cnt;
8385 PortAddr iop_base;
8386 ushort sg_list_dwords;
8387 ushort sg_index;
8388 ushort sg_entry_cnt;
8389 ushort q_addr;
8390 uchar next_qp;
8391
8392 iop_base = asc_dvc->iop_base;
8393 sg_head = scsiq->sg_head;
8394 saved_data_addr = scsiq->q1.data_addr;
8395 saved_data_cnt = scsiq->q1.data_cnt;
8396 scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
8397 scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
8398 #if CC_VERY_LONG_SG_LIST
8399 /*
8400 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
8401 * then not all SG elements will fit in the allocated queues.
8402 * The rest of the SG elements will be copied when the RISC
8403 * completes the SG elements that fit and halts.
8404 */
8405 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8406 /*
8407 * Set sg_entry_cnt to be the number of SG elements that
8408 * will fit in the allocated SG queues. It is minus 1, because
8409 * the first SG element is handled above. ASC_MAX_SG_LIST is
8410 * already inflated by 1 to account for this. For example it
8411 * may be 50 which is 1 + 7 queues * 7 SG elements.
8412 */
8413 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
8414
8415 /*
8416 * Keep track of remaining number of SG elements that will
8417 * need to be handled from a_isr.c.
8418 */
8419 scsiq->remain_sg_entry_cnt =
8420 sg_head->entry_cnt - ASC_MAX_SG_LIST;
8421 } else {
8422 #endif /* CC_VERY_LONG_SG_LIST */
8423 /*
8424 * Set sg_entry_cnt to be the number of SG elements that
8425 * will fit in the allocated SG queues. It is minus 1, because
8426 * the first SG element is handled above.
8427 */
8428 sg_entry_cnt = sg_head->entry_cnt - 1;
8429 #if CC_VERY_LONG_SG_LIST
8430 }
8431 #endif /* CC_VERY_LONG_SG_LIST */
8432 if (sg_entry_cnt != 0) {
8433 scsiq->q1.cntl |= QC_SG_HEAD;
8434 q_addr = ASC_QNO_TO_QADDR(q_no);
8435 sg_index = 1;
8436 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
8437 scsi_sg_q.sg_head_qp = q_no;
8438 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
8439 for (i = 0; i < sg_head->queue_cnt; i++) {
8440 scsi_sg_q.seq_no = i + 1;
8441 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
8442 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
8443 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
8444 if (i == 0) {
8445 scsi_sg_q.sg_list_cnt =
8446 ASC_SG_LIST_PER_Q;
8447 scsi_sg_q.sg_cur_list_cnt =
8448 ASC_SG_LIST_PER_Q;
8449 } else {
8450 scsi_sg_q.sg_list_cnt =
8451 ASC_SG_LIST_PER_Q - 1;
8452 scsi_sg_q.sg_cur_list_cnt =
8453 ASC_SG_LIST_PER_Q - 1;
8454 }
8455 } else {
8456 #if CC_VERY_LONG_SG_LIST
8457 /*
8458 * This is the last SG queue in the list of
8459 * allocated SG queues. If there are more
8460 * SG elements than will fit in the allocated
8461 * queues, then set the QCSG_SG_XFER_MORE flag.
8462 */
8463 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8464 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
8465 } else {
8466 #endif /* CC_VERY_LONG_SG_LIST */
8467 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
8468 #if CC_VERY_LONG_SG_LIST
8469 }
8470 #endif /* CC_VERY_LONG_SG_LIST */
8471 sg_list_dwords = sg_entry_cnt << 1;
8472 if (i == 0) {
8473 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
8474 scsi_sg_q.sg_cur_list_cnt =
8475 sg_entry_cnt;
8476 } else {
8477 scsi_sg_q.sg_list_cnt =
8478 sg_entry_cnt - 1;
8479 scsi_sg_q.sg_cur_list_cnt =
8480 sg_entry_cnt - 1;
8481 }
8482 sg_entry_cnt = 0;
8483 }
8484 next_qp = AscReadLramByte(iop_base,
8485 (ushort)(q_addr +
8486 ASC_SCSIQ_B_FWD));
8487 scsi_sg_q.q_no = next_qp;
8488 q_addr = ASC_QNO_TO_QADDR(next_qp);
8489 AscMemWordCopyPtrToLram(iop_base,
8490 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
8491 (uchar *)&scsi_sg_q,
8492 sizeof(ASC_SG_LIST_Q) >> 1);
8493 AscMemDWordCopyPtrToLram(iop_base,
8494 q_addr + ASC_SGQ_LIST_BEG,
8495 (uchar *)&sg_head->
8496 sg_list[sg_index],
8497 sg_list_dwords);
8498 sg_index += ASC_SG_LIST_PER_Q;
8499 scsiq->next_sg_index = sg_index;
8500 }
8501 } else {
8502 scsiq->q1.cntl &= ~QC_SG_HEAD;
8503 }
8504 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
8505 scsiq->q1.data_addr = saved_data_addr;
8506 scsiq->q1.data_cnt = saved_data_cnt;
8507 return (sta);
8508 }
8509
8510 static int
8511 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
8512 {
8513 PortAddr iop_base;
8514 uchar free_q_head;
8515 uchar next_qp;
8516 uchar tid_no;
8517 uchar target_ix;
8518 int sta;
8519
8520 iop_base = asc_dvc->iop_base;
8521 target_ix = scsiq->q2.target_ix;
8522 tid_no = ASC_TIX_TO_TID(target_ix);
8523 sta = 0;
8524 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
8525 if (n_q_required > 1) {
8526 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
8527 (uchar)n_q_required);
8528 if (next_qp != ASC_QLINK_END) {
8529 asc_dvc->last_q_shortage = 0;
8530 scsiq->sg_head->queue_cnt = n_q_required - 1;
8531 scsiq->q1.q_no = free_q_head;
8532 sta = AscPutReadySgListQueue(asc_dvc, scsiq,
8533 free_q_head);
8534 }
8535 } else if (n_q_required == 1) {
8536 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
8537 if (next_qp != ASC_QLINK_END) {
8538 scsiq->q1.q_no = free_q_head;
8539 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
8540 }
8541 }
8542 if (sta == 1) {
8543 AscPutVarFreeQHead(iop_base, next_qp);
8544 asc_dvc->cur_total_qng += n_q_required;
8545 asc_dvc->cur_dvc_qng[tid_no]++;
8546 }
8547 return sta;
8548 }
8549
8550 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
8551 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
8552 INQUIRY,
8553 REQUEST_SENSE,
8554 READ_CAPACITY,
8555 READ_TOC,
8556 MODE_SELECT,
8557 MODE_SENSE,
8558 MODE_SELECT_10,
8559 MODE_SENSE_10,
8560 0xFF,
8561 0xFF,
8562 0xFF,
8563 0xFF,
8564 0xFF,
8565 0xFF,
8566 0xFF,
8567 0xFF
8568 };
8569
8570 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
8571 {
8572 PortAddr iop_base;
8573 int sta;
8574 int n_q_required;
8575 int disable_syn_offset_one_fix;
8576 int i;
8577 ASC_PADDR addr;
8578 ushort sg_entry_cnt = 0;
8579 ushort sg_entry_cnt_minus_one = 0;
8580 uchar target_ix;
8581 uchar tid_no;
8582 uchar sdtr_data;
8583 uchar extra_bytes;
8584 uchar scsi_cmd;
8585 uchar disable_cmd;
8586 ASC_SG_HEAD *sg_head;
8587 ASC_DCNT data_cnt;
8588
8589 iop_base = asc_dvc->iop_base;
8590 sg_head = scsiq->sg_head;
8591 if (asc_dvc->err_code != 0)
8592 return (ERR);
8593 scsiq->q1.q_no = 0;
8594 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
8595 scsiq->q1.extra_bytes = 0;
8596 }
8597 sta = 0;
8598 target_ix = scsiq->q2.target_ix;
8599 tid_no = ASC_TIX_TO_TID(target_ix);
8600 n_q_required = 1;
8601 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
8602 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
8603 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
8604 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8605 AscMsgOutSDTR(asc_dvc,
8606 asc_dvc->
8607 sdtr_period_tbl[(sdtr_data >> 4) &
8608 (uchar)(asc_dvc->
8609 max_sdtr_index -
8610 1)],
8611 (uchar)(sdtr_data & (uchar)
8612 ASC_SYN_MAX_OFFSET));
8613 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
8614 }
8615 }
8616 if (asc_dvc->in_critical_cnt != 0) {
8617 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
8618 return (ERR);
8619 }
8620 asc_dvc->in_critical_cnt++;
8621 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8622 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
8623 asc_dvc->in_critical_cnt--;
8624 return (ERR);
8625 }
8626 #if !CC_VERY_LONG_SG_LIST
8627 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8628 asc_dvc->in_critical_cnt--;
8629 return (ERR);
8630 }
8631 #endif /* !CC_VERY_LONG_SG_LIST */
8632 if (sg_entry_cnt == 1) {
8633 scsiq->q1.data_addr =
8634 (ADV_PADDR)sg_head->sg_list[0].addr;
8635 scsiq->q1.data_cnt =
8636 (ADV_DCNT)sg_head->sg_list[0].bytes;
8637 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
8638 }
8639 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
8640 }
8641 scsi_cmd = scsiq->cdbptr[0];
8642 disable_syn_offset_one_fix = FALSE;
8643 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
8644 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
8645 if (scsiq->q1.cntl & QC_SG_HEAD) {
8646 data_cnt = 0;
8647 for (i = 0; i < sg_entry_cnt; i++) {
8648 data_cnt +=
8649 (ADV_DCNT)le32_to_cpu(sg_head->sg_list[i].
8650 bytes);
8651 }
8652 } else {
8653 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
8654 }
8655 if (data_cnt != 0UL) {
8656 if (data_cnt < 512UL) {
8657 disable_syn_offset_one_fix = TRUE;
8658 } else {
8659 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
8660 i++) {
8661 disable_cmd =
8662 _syn_offset_one_disable_cmd[i];
8663 if (disable_cmd == 0xFF) {
8664 break;
8665 }
8666 if (scsi_cmd == disable_cmd) {
8667 disable_syn_offset_one_fix =
8668 TRUE;
8669 break;
8670 }
8671 }
8672 }
8673 }
8674 }
8675 if (disable_syn_offset_one_fix) {
8676 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
8677 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
8678 ASC_TAG_FLAG_DISABLE_DISCONNECT);
8679 } else {
8680 scsiq->q2.tag_code &= 0x27;
8681 }
8682 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8683 if (asc_dvc->bug_fix_cntl) {
8684 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8685 if ((scsi_cmd == READ_6) ||
8686 (scsi_cmd == READ_10)) {
8687 addr =
8688 (ADV_PADDR)le32_to_cpu(sg_head->
8689 sg_list
8690 [sg_entry_cnt_minus_one].
8691 addr) +
8692 (ADV_DCNT)le32_to_cpu(sg_head->
8693 sg_list
8694 [sg_entry_cnt_minus_one].
8695 bytes);
8696 extra_bytes =
8697 (uchar)((ushort)addr & 0x0003);
8698 if ((extra_bytes != 0)
8699 &&
8700 ((scsiq->q2.
8701 tag_code &
8702 ASC_TAG_FLAG_EXTRA_BYTES)
8703 == 0)) {
8704 scsiq->q2.tag_code |=
8705 ASC_TAG_FLAG_EXTRA_BYTES;
8706 scsiq->q1.extra_bytes =
8707 extra_bytes;
8708 data_cnt =
8709 le32_to_cpu(sg_head->
8710 sg_list
8711 [sg_entry_cnt_minus_one].
8712 bytes);
8713 data_cnt -=
8714 (ASC_DCNT) extra_bytes;
8715 sg_head->
8716 sg_list
8717 [sg_entry_cnt_minus_one].
8718 bytes =
8719 cpu_to_le32(data_cnt);
8720 }
8721 }
8722 }
8723 }
8724 sg_head->entry_to_copy = sg_head->entry_cnt;
8725 #if CC_VERY_LONG_SG_LIST
8726 /*
8727 * Set the sg_entry_cnt to the maximum possible. The rest of
8728 * the SG elements will be copied when the RISC completes the
8729 * SG elements that fit and halts.
8730 */
8731 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8732 sg_entry_cnt = ASC_MAX_SG_LIST;
8733 }
8734 #endif /* CC_VERY_LONG_SG_LIST */
8735 n_q_required = AscSgListToQueue(sg_entry_cnt);
8736 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
8737 (uint) n_q_required)
8738 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8739 if ((sta =
8740 AscSendScsiQueue(asc_dvc, scsiq,
8741 n_q_required)) == 1) {
8742 asc_dvc->in_critical_cnt--;
8743 return (sta);
8744 }
8745 }
8746 } else {
8747 if (asc_dvc->bug_fix_cntl) {
8748 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8749 if ((scsi_cmd == READ_6) ||
8750 (scsi_cmd == READ_10)) {
8751 addr =
8752 le32_to_cpu(scsiq->q1.data_addr) +
8753 le32_to_cpu(scsiq->q1.data_cnt);
8754 extra_bytes =
8755 (uchar)((ushort)addr & 0x0003);
8756 if ((extra_bytes != 0)
8757 &&
8758 ((scsiq->q2.
8759 tag_code &
8760 ASC_TAG_FLAG_EXTRA_BYTES)
8761 == 0)) {
8762 data_cnt =
8763 le32_to_cpu(scsiq->q1.
8764 data_cnt);
8765 if (((ushort)data_cnt & 0x01FF)
8766 == 0) {
8767 scsiq->q2.tag_code |=
8768 ASC_TAG_FLAG_EXTRA_BYTES;
8769 data_cnt -= (ASC_DCNT)
8770 extra_bytes;
8771 scsiq->q1.data_cnt =
8772 cpu_to_le32
8773 (data_cnt);
8774 scsiq->q1.extra_bytes =
8775 extra_bytes;
8776 }
8777 }
8778 }
8779 }
8780 }
8781 n_q_required = 1;
8782 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
8783 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8784 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
8785 n_q_required)) == 1) {
8786 asc_dvc->in_critical_cnt--;
8787 return (sta);
8788 }
8789 }
8790 }
8791 asc_dvc->in_critical_cnt--;
8792 return (sta);
8793 }
8794
8795 /*
8796 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
8797 *
8798 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
8799 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
8800 * RISC to notify it a new command is ready to be executed.
8801 *
8802 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
8803 * set to SCSI_MAX_RETRY.
8804 *
8805 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
8806 * for DMA addresses or math operations are byte swapped to little-endian
8807 * order.
8808 *
8809 * Return:
8810 * ADV_SUCCESS(1) - The request was successfully queued.
8811 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
8812 * request completes.
8813 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
8814 * host IC error.
8815 */
8816 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq)
8817 {
8818 AdvPortAddr iop_base;
8819 ADV_PADDR req_paddr;
8820 ADV_CARR_T *new_carrp;
8821
8822 /*
8823 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
8824 */
8825 if (scsiq->target_id > ADV_MAX_TID) {
8826 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
8827 scsiq->done_status = QD_WITH_ERROR;
8828 return ADV_ERROR;
8829 }
8830
8831 iop_base = asc_dvc->iop_base;
8832
8833 /*
8834 * Allocate a carrier ensuring at least one carrier always
8835 * remains on the freelist and initialize fields.
8836 */
8837 if ((new_carrp = asc_dvc->carr_freelist) == NULL) {
8838 return ADV_BUSY;
8839 }
8840 asc_dvc->carr_freelist = (ADV_CARR_T *)
8841 ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
8842 asc_dvc->carr_pending_cnt++;
8843
8844 /*
8845 * Set the carrier to be a stopper by setting 'next_vpa'
8846 * to the stopper value. The current stopper will be changed
8847 * below to point to the new stopper.
8848 */
8849 new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
8850
8851 /*
8852 * Clear the ADV_SCSI_REQ_Q done flag.
8853 */
8854 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
8855
8856 req_paddr = virt_to_bus(scsiq);
8857 BUG_ON(req_paddr & 31);
8858 /* Wait for assertion before making little-endian */
8859 req_paddr = cpu_to_le32(req_paddr);
8860
8861 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
8862 scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
8863 scsiq->scsiq_rptr = req_paddr;
8864
8865 scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
8866 /*
8867 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
8868 * order during initialization.
8869 */
8870 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
8871
8872 /*
8873 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
8874 * the microcode. The newly allocated stopper will become the new
8875 * stopper.
8876 */
8877 asc_dvc->icq_sp->areq_vpa = req_paddr;
8878
8879 /*
8880 * Set the 'next_vpa' pointer for the old stopper to be the
8881 * physical address of the new stopper. The RISC can only
8882 * follow physical addresses.
8883 */
8884 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
8885
8886 /*
8887 * Set the host adapter stopper pointer to point to the new carrier.
8888 */
8889 asc_dvc->icq_sp = new_carrp;
8890
8891 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8892 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8893 /*
8894 * Tickle the RISC to tell it to read its Command Queue Head pointer.
8895 */
8896 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
8897 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8898 /*
8899 * Clear the tickle value. In the ASC-3550 the RISC flag
8900 * command 'clr_tickle_a' does not work unless the host
8901 * value is cleared.
8902 */
8903 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8904 ADV_TICKLE_NOP);
8905 }
8906 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8907 /*
8908 * Notify the RISC a carrier is ready by writing the physical
8909 * address of the new carrier stopper to the COMMA register.
8910 */
8911 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
8912 le32_to_cpu(new_carrp->carr_pa));
8913 }
8914
8915 return ADV_SUCCESS;
8916 }
8917
8918 /*
8919 * Execute a single 'Scsi_Cmnd'.
8920 */
8921 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
8922 {
8923 int ret, err_code;
8924 struct asc_board *boardp = shost_priv(scp->device->host);
8925
8926 ASC_DBG(1, "scp 0x%p\n", scp);
8927
8928 if (ASC_NARROW_BOARD(boardp)) {
8929 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
8930 struct asc_scsi_q asc_scsi_q;
8931
8932 /* asc_build_req() can not return ASC_BUSY. */
8933 ret = asc_build_req(boardp, scp, &asc_scsi_q);
8934 if (ret == ASC_ERROR) {
8935 ASC_STATS(scp->device->host, build_error);
8936 return ASC_ERROR;
8937 }
8938
8939 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
8940 kfree(asc_scsi_q.sg_head);
8941 err_code = asc_dvc->err_code;
8942 } else {
8943 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
8944 ADV_SCSI_REQ_Q *adv_scsiqp;
8945
8946 switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
8947 case ASC_NOERROR:
8948 ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
8949 break;
8950 case ASC_BUSY:
8951 ASC_DBG(1, "adv_build_req ASC_BUSY\n");
8952 /*
8953 * The asc_stats fields 'adv_build_noreq' and
8954 * 'adv_build_nosg' count wide board busy conditions.
8955 * They are updated in adv_build_req and
8956 * adv_get_sglist, respectively.
8957 */
8958 return ASC_BUSY;
8959 case ASC_ERROR:
8960 default:
8961 ASC_DBG(1, "adv_build_req ASC_ERROR\n");
8962 ASC_STATS(scp->device->host, build_error);
8963 return ASC_ERROR;
8964 }
8965
8966 ret = AdvExeScsiQueue(adv_dvc, adv_scsiqp);
8967 err_code = adv_dvc->err_code;
8968 }
8969
8970 switch (ret) {
8971 case ASC_NOERROR:
8972 ASC_STATS(scp->device->host, exe_noerror);
8973 /*
8974 * Increment monotonically increasing per device
8975 * successful request counter. Wrapping doesn't matter.
8976 */
8977 boardp->reqcnt[scp->device->id]++;
8978 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
8979 break;
8980 case ASC_BUSY:
8981 ASC_STATS(scp->device->host, exe_busy);
8982 break;
8983 case ASC_ERROR:
8984 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, "
8985 "err_code 0x%x\n", err_code);
8986 ASC_STATS(scp->device->host, exe_error);
8987 scp->result = HOST_BYTE(DID_ERROR);
8988 break;
8989 default:
8990 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, "
8991 "err_code 0x%x\n", err_code);
8992 ASC_STATS(scp->device->host, exe_unknown);
8993 scp->result = HOST_BYTE(DID_ERROR);
8994 break;
8995 }
8996
8997 ASC_DBG(1, "end\n");
8998 return ret;
8999 }
9000
9001 /*
9002 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
9003 *
9004 * This function always returns 0. Command return status is saved
9005 * in the 'scp' result field.
9006 */
9007 static int
9008 advansys_queuecommand_lck(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
9009 {
9010 struct Scsi_Host *shost = scp->device->host;
9011 int asc_res, result = 0;
9012
9013 ASC_STATS(shost, queuecommand);
9014 scp->scsi_done = done;
9015
9016 asc_res = asc_execute_scsi_cmnd(scp);
9017
9018 switch (asc_res) {
9019 case ASC_NOERROR:
9020 break;
9021 case ASC_BUSY:
9022 result = SCSI_MLQUEUE_HOST_BUSY;
9023 break;
9024 case ASC_ERROR:
9025 default:
9026 asc_scsi_done(scp);
9027 break;
9028 }
9029
9030 return result;
9031 }
9032
9033 static DEF_SCSI_QCMD(advansys_queuecommand)
9034
9035 static ushort AscGetEisaChipCfg(PortAddr iop_base)
9036 {
9037 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
9038 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
9039 return inpw(eisa_cfg_iop);
9040 }
9041
9042 /*
9043 * Return the BIOS address of the adapter at the specified
9044 * I/O port and with the specified bus type.
9045 */
9046 static unsigned short AscGetChipBiosAddress(PortAddr iop_base,
9047 unsigned short bus_type)
9048 {
9049 unsigned short cfg_lsw;
9050 unsigned short bios_addr;
9051
9052 /*
9053 * The PCI BIOS is re-located by the motherboard BIOS. Because
9054 * of this the driver can not determine where a PCI BIOS is
9055 * loaded and executes.
9056 */
9057 if (bus_type & ASC_IS_PCI)
9058 return 0;
9059
9060 if ((bus_type & ASC_IS_EISA) != 0) {
9061 cfg_lsw = AscGetEisaChipCfg(iop_base);
9062 cfg_lsw &= 0x000F;
9063 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
9064 return bios_addr;
9065 }
9066
9067 cfg_lsw = AscGetChipCfgLsw(iop_base);
9068
9069 /*
9070 * ISA PnP uses the top bit as the 32K BIOS flag
9071 */
9072 if (bus_type == ASC_IS_ISAPNP)
9073 cfg_lsw &= 0x7FFF;
9074 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
9075 return bios_addr;
9076 }
9077
9078 static uchar AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
9079 {
9080 ushort cfg_lsw;
9081
9082 if (AscGetChipScsiID(iop_base) == new_host_id) {
9083 return (new_host_id);
9084 }
9085 cfg_lsw = AscGetChipCfgLsw(iop_base);
9086 cfg_lsw &= 0xF8FF;
9087 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
9088 AscSetChipCfgLsw(iop_base, cfg_lsw);
9089 return (AscGetChipScsiID(iop_base));
9090 }
9091
9092 static unsigned char AscGetChipScsiCtrl(PortAddr iop_base)
9093 {
9094 unsigned char sc;
9095
9096 AscSetBank(iop_base, 1);
9097 sc = inp(iop_base + IOP_REG_SC);
9098 AscSetBank(iop_base, 0);
9099 return sc;
9100 }
9101
9102 static unsigned char AscGetChipVersion(PortAddr iop_base,
9103 unsigned short bus_type)
9104 {
9105 if (bus_type & ASC_IS_EISA) {
9106 PortAddr eisa_iop;
9107 unsigned char revision;
9108 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
9109 (PortAddr) ASC_EISA_REV_IOP_MASK;
9110 revision = inp(eisa_iop);
9111 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
9112 }
9113 return AscGetChipVerNo(iop_base);
9114 }
9115
9116 #ifdef CONFIG_ISA
9117 static void AscEnableIsaDma(uchar dma_channel)
9118 {
9119 if (dma_channel < 4) {
9120 outp(0x000B, (ushort)(0xC0 | dma_channel));
9121 outp(0x000A, dma_channel);
9122 } else if (dma_channel < 8) {
9123 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
9124 outp(0x00D4, (ushort)(dma_channel - 4));
9125 }
9126 }
9127 #endif /* CONFIG_ISA */
9128
9129 static int AscStopQueueExe(PortAddr iop_base)
9130 {
9131 int count = 0;
9132
9133 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
9134 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
9135 ASC_STOP_REQ_RISC_STOP);
9136 do {
9137 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
9138 ASC_STOP_ACK_RISC_STOP) {
9139 return (1);
9140 }
9141 mdelay(100);
9142 } while (count++ < 20);
9143 }
9144 return (0);
9145 }
9146
9147 static ASC_DCNT AscGetMaxDmaCount(ushort bus_type)
9148 {
9149 if (bus_type & ASC_IS_ISA)
9150 return ASC_MAX_ISA_DMA_COUNT;
9151 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
9152 return ASC_MAX_VL_DMA_COUNT;
9153 return ASC_MAX_PCI_DMA_COUNT;
9154 }
9155
9156 #ifdef CONFIG_ISA
9157 static ushort AscGetIsaDmaChannel(PortAddr iop_base)
9158 {
9159 ushort channel;
9160
9161 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
9162 if (channel == 0x03)
9163 return (0);
9164 else if (channel == 0x00)
9165 return (7);
9166 return (channel + 4);
9167 }
9168
9169 static ushort AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
9170 {
9171 ushort cfg_lsw;
9172 uchar value;
9173
9174 if ((dma_channel >= 5) && (dma_channel <= 7)) {
9175 if (dma_channel == 7)
9176 value = 0x00;
9177 else
9178 value = dma_channel - 4;
9179 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
9180 cfg_lsw |= value;
9181 AscSetChipCfgLsw(iop_base, cfg_lsw);
9182 return (AscGetIsaDmaChannel(iop_base));
9183 }
9184 return 0;
9185 }
9186
9187 static uchar AscGetIsaDmaSpeed(PortAddr iop_base)
9188 {
9189 uchar speed_value;
9190
9191 AscSetBank(iop_base, 1);
9192 speed_value = AscReadChipDmaSpeed(iop_base);
9193 speed_value &= 0x07;
9194 AscSetBank(iop_base, 0);
9195 return speed_value;
9196 }
9197
9198 static uchar AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
9199 {
9200 speed_value &= 0x07;
9201 AscSetBank(iop_base, 1);
9202 AscWriteChipDmaSpeed(iop_base, speed_value);
9203 AscSetBank(iop_base, 0);
9204 return AscGetIsaDmaSpeed(iop_base);
9205 }
9206 #endif /* CONFIG_ISA */
9207
9208 static ushort AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
9209 {
9210 int i;
9211 PortAddr iop_base;
9212 ushort warn_code;
9213 uchar chip_version;
9214
9215 iop_base = asc_dvc->iop_base;
9216 warn_code = 0;
9217 asc_dvc->err_code = 0;
9218 if ((asc_dvc->bus_type &
9219 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
9220 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
9221 }
9222 AscSetChipControl(iop_base, CC_HALT);
9223 AscSetChipStatus(iop_base, 0);
9224 asc_dvc->bug_fix_cntl = 0;
9225 asc_dvc->pci_fix_asyn_xfer = 0;
9226 asc_dvc->pci_fix_asyn_xfer_always = 0;
9227 /* asc_dvc->init_state initialized in AscInitGetConfig(). */
9228 asc_dvc->sdtr_done = 0;
9229 asc_dvc->cur_total_qng = 0;
9230 asc_dvc->is_in_int = 0;
9231 asc_dvc->in_critical_cnt = 0;
9232 asc_dvc->last_q_shortage = 0;
9233 asc_dvc->use_tagged_qng = 0;
9234 asc_dvc->no_scam = 0;
9235 asc_dvc->unit_not_ready = 0;
9236 asc_dvc->queue_full_or_busy = 0;
9237 asc_dvc->redo_scam = 0;
9238 asc_dvc->res2 = 0;
9239 asc_dvc->min_sdtr_index = 0;
9240 asc_dvc->cfg->can_tagged_qng = 0;
9241 asc_dvc->cfg->cmd_qng_enabled = 0;
9242 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
9243 asc_dvc->init_sdtr = 0;
9244 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
9245 asc_dvc->scsi_reset_wait = 3;
9246 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
9247 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
9248 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
9249 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
9250 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
9251 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
9252 asc_dvc->cfg->chip_version = chip_version;
9253 asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
9254 asc_dvc->max_sdtr_index = 7;
9255 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
9256 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
9257 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
9258 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
9259 asc_dvc->max_sdtr_index = 15;
9260 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
9261 AscSetExtraControl(iop_base,
9262 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9263 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
9264 AscSetExtraControl(iop_base,
9265 (SEC_ACTIVE_NEGATE |
9266 SEC_ENABLE_FILTER));
9267 }
9268 }
9269 if (asc_dvc->bus_type == ASC_IS_PCI) {
9270 AscSetExtraControl(iop_base,
9271 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9272 }
9273
9274 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
9275 #ifdef CONFIG_ISA
9276 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
9277 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
9278 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
9279 asc_dvc->bus_type = ASC_IS_ISAPNP;
9280 }
9281 asc_dvc->cfg->isa_dma_channel =
9282 (uchar)AscGetIsaDmaChannel(iop_base);
9283 }
9284 #endif /* CONFIG_ISA */
9285 for (i = 0; i <= ASC_MAX_TID; i++) {
9286 asc_dvc->cur_dvc_qng[i] = 0;
9287 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
9288 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
9289 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
9290 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
9291 }
9292 return warn_code;
9293 }
9294
9295 static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
9296 {
9297 int retry;
9298
9299 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
9300 unsigned char read_back;
9301 AscSetChipEEPCmd(iop_base, cmd_reg);
9302 mdelay(1);
9303 read_back = AscGetChipEEPCmd(iop_base);
9304 if (read_back == cmd_reg)
9305 return 1;
9306 }
9307 return 0;
9308 }
9309
9310 static void AscWaitEEPRead(void)
9311 {
9312 mdelay(1);
9313 }
9314
9315 static ushort AscReadEEPWord(PortAddr iop_base, uchar addr)
9316 {
9317 ushort read_wval;
9318 uchar cmd_reg;
9319
9320 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9321 AscWaitEEPRead();
9322 cmd_reg = addr | ASC_EEP_CMD_READ;
9323 AscWriteEEPCmdReg(iop_base, cmd_reg);
9324 AscWaitEEPRead();
9325 read_wval = AscGetChipEEPData(iop_base);
9326 AscWaitEEPRead();
9327 return read_wval;
9328 }
9329
9330 static ushort AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9331 ushort bus_type)
9332 {
9333 ushort wval;
9334 ushort sum;
9335 ushort *wbuf;
9336 int cfg_beg;
9337 int cfg_end;
9338 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9339 int s_addr;
9340
9341 wbuf = (ushort *)cfg_buf;
9342 sum = 0;
9343 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
9344 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9345 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9346 sum += *wbuf;
9347 }
9348 if (bus_type & ASC_IS_VL) {
9349 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9350 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9351 } else {
9352 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9353 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9354 }
9355 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9356 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
9357 if (s_addr <= uchar_end_in_config) {
9358 /*
9359 * Swap all char fields - must unswap bytes already swapped
9360 * by AscReadEEPWord().
9361 */
9362 *wbuf = le16_to_cpu(wval);
9363 } else {
9364 /* Don't swap word field at the end - cntl field. */
9365 *wbuf = wval;
9366 }
9367 sum += wval; /* Checksum treats all EEPROM data as words. */
9368 }
9369 /*
9370 * Read the checksum word which will be compared against 'sum'
9371 * by the caller. Word field already swapped.
9372 */
9373 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9374 return sum;
9375 }
9376
9377 static int AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
9378 {
9379 PortAddr iop_base;
9380 ushort q_addr;
9381 ushort saved_word;
9382 int sta;
9383
9384 iop_base = asc_dvc->iop_base;
9385 sta = 0;
9386 q_addr = ASC_QNO_TO_QADDR(241);
9387 saved_word = AscReadLramWord(iop_base, q_addr);
9388 AscSetChipLramAddr(iop_base, q_addr);
9389 AscSetChipLramData(iop_base, 0x55AA);
9390 mdelay(10);
9391 AscSetChipLramAddr(iop_base, q_addr);
9392 if (AscGetChipLramData(iop_base) == 0x55AA) {
9393 sta = 1;
9394 AscWriteLramWord(iop_base, q_addr, saved_word);
9395 }
9396 return (sta);
9397 }
9398
9399 static void AscWaitEEPWrite(void)
9400 {
9401 mdelay(20);
9402 }
9403
9404 static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
9405 {
9406 ushort read_back;
9407 int retry;
9408
9409 retry = 0;
9410 while (TRUE) {
9411 AscSetChipEEPData(iop_base, data_reg);
9412 mdelay(1);
9413 read_back = AscGetChipEEPData(iop_base);
9414 if (read_back == data_reg) {
9415 return (1);
9416 }
9417 if (retry++ > ASC_EEP_MAX_RETRY) {
9418 return (0);
9419 }
9420 }
9421 }
9422
9423 static ushort AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
9424 {
9425 ushort read_wval;
9426
9427 read_wval = AscReadEEPWord(iop_base, addr);
9428 if (read_wval != word_val) {
9429 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
9430 AscWaitEEPRead();
9431 AscWriteEEPDataReg(iop_base, word_val);
9432 AscWaitEEPRead();
9433 AscWriteEEPCmdReg(iop_base,
9434 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
9435 AscWaitEEPWrite();
9436 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9437 AscWaitEEPRead();
9438 return (AscReadEEPWord(iop_base, addr));
9439 }
9440 return (read_wval);
9441 }
9442
9443 static int AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9444 ushort bus_type)
9445 {
9446 int n_error;
9447 ushort *wbuf;
9448 ushort word;
9449 ushort sum;
9450 int s_addr;
9451 int cfg_beg;
9452 int cfg_end;
9453 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9454
9455 wbuf = (ushort *)cfg_buf;
9456 n_error = 0;
9457 sum = 0;
9458 /* Write two config words; AscWriteEEPWord() will swap bytes. */
9459 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9460 sum += *wbuf;
9461 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9462 n_error++;
9463 }
9464 }
9465 if (bus_type & ASC_IS_VL) {
9466 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9467 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9468 } else {
9469 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9470 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9471 }
9472 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9473 if (s_addr <= uchar_end_in_config) {
9474 /*
9475 * This is a char field. Swap char fields before they are
9476 * swapped again by AscWriteEEPWord().
9477 */
9478 word = cpu_to_le16(*wbuf);
9479 if (word !=
9480 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
9481 n_error++;
9482 }
9483 } else {
9484 /* Don't swap word field at the end - cntl field. */
9485 if (*wbuf !=
9486 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9487 n_error++;
9488 }
9489 }
9490 sum += *wbuf; /* Checksum calculated from word values. */
9491 }
9492 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
9493 *wbuf = sum;
9494 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
9495 n_error++;
9496 }
9497
9498 /* Read EEPROM back again. */
9499 wbuf = (ushort *)cfg_buf;
9500 /*
9501 * Read two config words; Byte-swapping done by AscReadEEPWord().
9502 */
9503 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9504 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
9505 n_error++;
9506 }
9507 }
9508 if (bus_type & ASC_IS_VL) {
9509 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9510 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9511 } else {
9512 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9513 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9514 }
9515 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9516 if (s_addr <= uchar_end_in_config) {
9517 /*
9518 * Swap all char fields. Must unswap bytes already swapped
9519 * by AscReadEEPWord().
9520 */
9521 word =
9522 le16_to_cpu(AscReadEEPWord
9523 (iop_base, (uchar)s_addr));
9524 } else {
9525 /* Don't swap word field at the end - cntl field. */
9526 word = AscReadEEPWord(iop_base, (uchar)s_addr);
9527 }
9528 if (*wbuf != word) {
9529 n_error++;
9530 }
9531 }
9532 /* Read checksum; Byte swapping not needed. */
9533 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
9534 n_error++;
9535 }
9536 return n_error;
9537 }
9538
9539 static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9540 ushort bus_type)
9541 {
9542 int retry;
9543 int n_error;
9544
9545 retry = 0;
9546 while (TRUE) {
9547 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
9548 bus_type)) == 0) {
9549 break;
9550 }
9551 if (++retry > ASC_EEP_MAX_RETRY) {
9552 break;
9553 }
9554 }
9555 return n_error;
9556 }
9557
9558 static ushort AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
9559 {
9560 ASCEEP_CONFIG eep_config_buf;
9561 ASCEEP_CONFIG *eep_config;
9562 PortAddr iop_base;
9563 ushort chksum;
9564 ushort warn_code;
9565 ushort cfg_msw, cfg_lsw;
9566 int i;
9567 int write_eep = 0;
9568
9569 iop_base = asc_dvc->iop_base;
9570 warn_code = 0;
9571 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
9572 AscStopQueueExe(iop_base);
9573 if ((AscStopChip(iop_base) == FALSE) ||
9574 (AscGetChipScsiCtrl(iop_base) != 0)) {
9575 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
9576 AscResetChipAndScsiBus(asc_dvc);
9577 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
9578 }
9579 if (AscIsChipHalted(iop_base) == FALSE) {
9580 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
9581 return (warn_code);
9582 }
9583 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
9584 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
9585 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
9586 return (warn_code);
9587 }
9588 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
9589 cfg_msw = AscGetChipCfgMsw(iop_base);
9590 cfg_lsw = AscGetChipCfgLsw(iop_base);
9591 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9592 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9593 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9594 AscSetChipCfgMsw(iop_base, cfg_msw);
9595 }
9596 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
9597 ASC_DBG(1, "chksum 0x%x\n", chksum);
9598 if (chksum == 0) {
9599 chksum = 0xaa55;
9600 }
9601 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9602 warn_code |= ASC_WARN_AUTO_CONFIG;
9603 if (asc_dvc->cfg->chip_version == 3) {
9604 if (eep_config->cfg_lsw != cfg_lsw) {
9605 warn_code |= ASC_WARN_EEPROM_RECOVER;
9606 eep_config->cfg_lsw =
9607 AscGetChipCfgLsw(iop_base);
9608 }
9609 if (eep_config->cfg_msw != cfg_msw) {
9610 warn_code |= ASC_WARN_EEPROM_RECOVER;
9611 eep_config->cfg_msw =
9612 AscGetChipCfgMsw(iop_base);
9613 }
9614 }
9615 }
9616 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9617 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
9618 ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum);
9619 if (chksum != eep_config->chksum) {
9620 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
9621 ASC_CHIP_VER_PCI_ULTRA_3050) {
9622 ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
9623 eep_config->init_sdtr = 0xFF;
9624 eep_config->disc_enable = 0xFF;
9625 eep_config->start_motor = 0xFF;
9626 eep_config->use_cmd_qng = 0;
9627 eep_config->max_total_qng = 0xF0;
9628 eep_config->max_tag_qng = 0x20;
9629 eep_config->cntl = 0xBFFF;
9630 ASC_EEP_SET_CHIP_ID(eep_config, 7);
9631 eep_config->no_scam = 0;
9632 eep_config->adapter_info[0] = 0;
9633 eep_config->adapter_info[1] = 0;
9634 eep_config->adapter_info[2] = 0;
9635 eep_config->adapter_info[3] = 0;
9636 eep_config->adapter_info[4] = 0;
9637 /* Indicate EEPROM-less board. */
9638 eep_config->adapter_info[5] = 0xBB;
9639 } else {
9640 ASC_PRINT
9641 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
9642 write_eep = 1;
9643 warn_code |= ASC_WARN_EEPROM_CHKSUM;
9644 }
9645 }
9646 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
9647 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
9648 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
9649 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
9650 asc_dvc->start_motor = eep_config->start_motor;
9651 asc_dvc->dvc_cntl = eep_config->cntl;
9652 asc_dvc->no_scam = eep_config->no_scam;
9653 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
9654 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
9655 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
9656 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
9657 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
9658 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
9659 if (!AscTestExternalLram(asc_dvc)) {
9660 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
9661 ASC_IS_PCI_ULTRA)) {
9662 eep_config->max_total_qng =
9663 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
9664 eep_config->max_tag_qng =
9665 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
9666 } else {
9667 eep_config->cfg_msw |= 0x0800;
9668 cfg_msw |= 0x0800;
9669 AscSetChipCfgMsw(iop_base, cfg_msw);
9670 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
9671 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
9672 }
9673 } else {
9674 }
9675 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
9676 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
9677 }
9678 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
9679 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
9680 }
9681 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
9682 eep_config->max_tag_qng = eep_config->max_total_qng;
9683 }
9684 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
9685 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
9686 }
9687 asc_dvc->max_total_qng = eep_config->max_total_qng;
9688 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
9689 eep_config->use_cmd_qng) {
9690 eep_config->disc_enable = eep_config->use_cmd_qng;
9691 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9692 }
9693 ASC_EEP_SET_CHIP_ID(eep_config,
9694 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
9695 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
9696 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
9697 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
9698 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
9699 }
9700
9701 for (i = 0; i <= ASC_MAX_TID; i++) {
9702 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
9703 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
9704 asc_dvc->cfg->sdtr_period_offset[i] =
9705 (uchar)(ASC_DEF_SDTR_OFFSET |
9706 (asc_dvc->min_sdtr_index << 4));
9707 }
9708 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
9709 if (write_eep) {
9710 if ((i = AscSetEEPConfig(iop_base, eep_config,
9711 asc_dvc->bus_type)) != 0) {
9712 ASC_PRINT1
9713 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
9714 i);
9715 } else {
9716 ASC_PRINT
9717 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
9718 }
9719 }
9720 return (warn_code);
9721 }
9722
9723 static int AscInitGetConfig(struct Scsi_Host *shost)
9724 {
9725 struct asc_board *board = shost_priv(shost);
9726 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
9727 unsigned short warn_code = 0;
9728
9729 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
9730 if (asc_dvc->err_code != 0)
9731 return asc_dvc->err_code;
9732
9733 if (AscFindSignature(asc_dvc->iop_base)) {
9734 warn_code |= AscInitAscDvcVar(asc_dvc);
9735 warn_code |= AscInitFromEEP(asc_dvc);
9736 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
9737 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
9738 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
9739 } else {
9740 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9741 }
9742
9743 switch (warn_code) {
9744 case 0: /* No error */
9745 break;
9746 case ASC_WARN_IO_PORT_ROTATE:
9747 shost_printk(KERN_WARNING, shost, "I/O port address "
9748 "modified\n");
9749 break;
9750 case ASC_WARN_AUTO_CONFIG:
9751 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9752 "enabled\n");
9753 break;
9754 case ASC_WARN_EEPROM_CHKSUM:
9755 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
9756 break;
9757 case ASC_WARN_IRQ_MODIFIED:
9758 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
9759 break;
9760 case ASC_WARN_CMD_QNG_CONFLICT:
9761 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o "
9762 "disconnects\n");
9763 break;
9764 default:
9765 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9766 warn_code);
9767 break;
9768 }
9769
9770 if (asc_dvc->err_code != 0)
9771 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9772 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
9773
9774 return asc_dvc->err_code;
9775 }
9776
9777 static int AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
9778 {
9779 struct asc_board *board = shost_priv(shost);
9780 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
9781 PortAddr iop_base = asc_dvc->iop_base;
9782 unsigned short cfg_msw;
9783 unsigned short warn_code = 0;
9784
9785 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
9786 if (asc_dvc->err_code != 0)
9787 return asc_dvc->err_code;
9788 if (!AscFindSignature(asc_dvc->iop_base)) {
9789 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9790 return asc_dvc->err_code;
9791 }
9792
9793 cfg_msw = AscGetChipCfgMsw(iop_base);
9794 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9795 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9796 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9797 AscSetChipCfgMsw(iop_base, cfg_msw);
9798 }
9799 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
9800 asc_dvc->cfg->cmd_qng_enabled) {
9801 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
9802 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9803 }
9804 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9805 warn_code |= ASC_WARN_AUTO_CONFIG;
9806 }
9807 #ifdef CONFIG_PCI
9808 if (asc_dvc->bus_type & ASC_IS_PCI) {
9809 cfg_msw &= 0xFFC0;
9810 AscSetChipCfgMsw(iop_base, cfg_msw);
9811 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
9812 } else {
9813 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
9814 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
9815 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
9816 asc_dvc->bug_fix_cntl |=
9817 ASC_BUG_FIX_ASYN_USE_SYN;
9818 }
9819 }
9820 } else
9821 #endif /* CONFIG_PCI */
9822 if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
9823 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
9824 == ASC_CHIP_VER_ASYN_BUG) {
9825 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
9826 }
9827 }
9828 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
9829 asc_dvc->cfg->chip_scsi_id) {
9830 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
9831 }
9832 #ifdef CONFIG_ISA
9833 if (asc_dvc->bus_type & ASC_IS_ISA) {
9834 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
9835 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
9836 }
9837 #endif /* CONFIG_ISA */
9838
9839 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
9840
9841 switch (warn_code) {
9842 case 0: /* No error. */
9843 break;
9844 case ASC_WARN_IO_PORT_ROTATE:
9845 shost_printk(KERN_WARNING, shost, "I/O port address "
9846 "modified\n");
9847 break;
9848 case ASC_WARN_AUTO_CONFIG:
9849 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9850 "enabled\n");
9851 break;
9852 case ASC_WARN_EEPROM_CHKSUM:
9853 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
9854 break;
9855 case ASC_WARN_IRQ_MODIFIED:
9856 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
9857 break;
9858 case ASC_WARN_CMD_QNG_CONFLICT:
9859 shost_printk(KERN_WARNING, shost, "tag queuing w/o "
9860 "disconnects\n");
9861 break;
9862 default:
9863 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9864 warn_code);
9865 break;
9866 }
9867
9868 if (asc_dvc->err_code != 0)
9869 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9870 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
9871
9872 return asc_dvc->err_code;
9873 }
9874
9875 /*
9876 * EEPROM Configuration.
9877 *
9878 * All drivers should use this structure to set the default EEPROM
9879 * configuration. The BIOS now uses this structure when it is built.
9880 * Additional structure information can be found in a_condor.h where
9881 * the structure is defined.
9882 *
9883 * The *_Field_IsChar structs are needed to correct for endianness.
9884 * These values are read from the board 16 bits at a time directly
9885 * into the structs. Because some fields are char, the values will be
9886 * in the wrong order. The *_Field_IsChar tells when to flip the
9887 * bytes. Data read and written to PCI memory is automatically swapped
9888 * on big-endian platforms so char fields read as words are actually being
9889 * unswapped on big-endian platforms.
9890 */
9891 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config = {
9892 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
9893 0x0000, /* cfg_msw */
9894 0xFFFF, /* disc_enable */
9895 0xFFFF, /* wdtr_able */
9896 0xFFFF, /* sdtr_able */
9897 0xFFFF, /* start_motor */
9898 0xFFFF, /* tagqng_able */
9899 0xFFFF, /* bios_scan */
9900 0, /* scam_tolerant */
9901 7, /* adapter_scsi_id */
9902 0, /* bios_boot_delay */
9903 3, /* scsi_reset_delay */
9904 0, /* bios_id_lun */
9905 0, /* termination */
9906 0, /* reserved1 */
9907 0xFFE7, /* bios_ctrl */
9908 0xFFFF, /* ultra_able */
9909 0, /* reserved2 */
9910 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
9911 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9912 0, /* dvc_cntl */
9913 0, /* bug_fix */
9914 0, /* serial_number_word1 */
9915 0, /* serial_number_word2 */
9916 0, /* serial_number_word3 */
9917 0, /* check_sum */
9918 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9919 , /* oem_name[16] */
9920 0, /* dvc_err_code */
9921 0, /* adv_err_code */
9922 0, /* adv_err_addr */
9923 0, /* saved_dvc_err_code */
9924 0, /* saved_adv_err_code */
9925 0, /* saved_adv_err_addr */
9926 0 /* num_of_err */
9927 };
9928
9929 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar = {
9930 0, /* cfg_lsw */
9931 0, /* cfg_msw */
9932 0, /* -disc_enable */
9933 0, /* wdtr_able */
9934 0, /* sdtr_able */
9935 0, /* start_motor */
9936 0, /* tagqng_able */
9937 0, /* bios_scan */
9938 0, /* scam_tolerant */
9939 1, /* adapter_scsi_id */
9940 1, /* bios_boot_delay */
9941 1, /* scsi_reset_delay */
9942 1, /* bios_id_lun */
9943 1, /* termination */
9944 1, /* reserved1 */
9945 0, /* bios_ctrl */
9946 0, /* ultra_able */
9947 0, /* reserved2 */
9948 1, /* max_host_qng */
9949 1, /* max_dvc_qng */
9950 0, /* dvc_cntl */
9951 0, /* bug_fix */
9952 0, /* serial_number_word1 */
9953 0, /* serial_number_word2 */
9954 0, /* serial_number_word3 */
9955 0, /* check_sum */
9956 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9957 , /* oem_name[16] */
9958 0, /* dvc_err_code */
9959 0, /* adv_err_code */
9960 0, /* adv_err_addr */
9961 0, /* saved_dvc_err_code */
9962 0, /* saved_adv_err_code */
9963 0, /* saved_adv_err_addr */
9964 0 /* num_of_err */
9965 };
9966
9967 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config = {
9968 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9969 0x0000, /* 01 cfg_msw */
9970 0xFFFF, /* 02 disc_enable */
9971 0xFFFF, /* 03 wdtr_able */
9972 0x4444, /* 04 sdtr_speed1 */
9973 0xFFFF, /* 05 start_motor */
9974 0xFFFF, /* 06 tagqng_able */
9975 0xFFFF, /* 07 bios_scan */
9976 0, /* 08 scam_tolerant */
9977 7, /* 09 adapter_scsi_id */
9978 0, /* bios_boot_delay */
9979 3, /* 10 scsi_reset_delay */
9980 0, /* bios_id_lun */
9981 0, /* 11 termination_se */
9982 0, /* termination_lvd */
9983 0xFFE7, /* 12 bios_ctrl */
9984 0x4444, /* 13 sdtr_speed2 */
9985 0x4444, /* 14 sdtr_speed3 */
9986 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9987 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9988 0, /* 16 dvc_cntl */
9989 0x4444, /* 17 sdtr_speed4 */
9990 0, /* 18 serial_number_word1 */
9991 0, /* 19 serial_number_word2 */
9992 0, /* 20 serial_number_word3 */
9993 0, /* 21 check_sum */
9994 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9995 , /* 22-29 oem_name[16] */
9996 0, /* 30 dvc_err_code */
9997 0, /* 31 adv_err_code */
9998 0, /* 32 adv_err_addr */
9999 0, /* 33 saved_dvc_err_code */
10000 0, /* 34 saved_adv_err_code */
10001 0, /* 35 saved_adv_err_addr */
10002 0, /* 36 reserved */
10003 0, /* 37 reserved */
10004 0, /* 38 reserved */
10005 0, /* 39 reserved */
10006 0, /* 40 reserved */
10007 0, /* 41 reserved */
10008 0, /* 42 reserved */
10009 0, /* 43 reserved */
10010 0, /* 44 reserved */
10011 0, /* 45 reserved */
10012 0, /* 46 reserved */
10013 0, /* 47 reserved */
10014 0, /* 48 reserved */
10015 0, /* 49 reserved */
10016 0, /* 50 reserved */
10017 0, /* 51 reserved */
10018 0, /* 52 reserved */
10019 0, /* 53 reserved */
10020 0, /* 54 reserved */
10021 0, /* 55 reserved */
10022 0, /* 56 cisptr_lsw */
10023 0, /* 57 cisprt_msw */
10024 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
10025 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
10026 0, /* 60 reserved */
10027 0, /* 61 reserved */
10028 0, /* 62 reserved */
10029 0 /* 63 reserved */
10030 };
10031
10032 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar = {
10033 0, /* 00 cfg_lsw */
10034 0, /* 01 cfg_msw */
10035 0, /* 02 disc_enable */
10036 0, /* 03 wdtr_able */
10037 0, /* 04 sdtr_speed1 */
10038 0, /* 05 start_motor */
10039 0, /* 06 tagqng_able */
10040 0, /* 07 bios_scan */
10041 0, /* 08 scam_tolerant */
10042 1, /* 09 adapter_scsi_id */
10043 1, /* bios_boot_delay */
10044 1, /* 10 scsi_reset_delay */
10045 1, /* bios_id_lun */
10046 1, /* 11 termination_se */
10047 1, /* termination_lvd */
10048 0, /* 12 bios_ctrl */
10049 0, /* 13 sdtr_speed2 */
10050 0, /* 14 sdtr_speed3 */
10051 1, /* 15 max_host_qng */
10052 1, /* max_dvc_qng */
10053 0, /* 16 dvc_cntl */
10054 0, /* 17 sdtr_speed4 */
10055 0, /* 18 serial_number_word1 */
10056 0, /* 19 serial_number_word2 */
10057 0, /* 20 serial_number_word3 */
10058 0, /* 21 check_sum */
10059 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
10060 , /* 22-29 oem_name[16] */
10061 0, /* 30 dvc_err_code */
10062 0, /* 31 adv_err_code */
10063 0, /* 32 adv_err_addr */
10064 0, /* 33 saved_dvc_err_code */
10065 0, /* 34 saved_adv_err_code */
10066 0, /* 35 saved_adv_err_addr */
10067 0, /* 36 reserved */
10068 0, /* 37 reserved */
10069 0, /* 38 reserved */
10070 0, /* 39 reserved */
10071 0, /* 40 reserved */
10072 0, /* 41 reserved */
10073 0, /* 42 reserved */
10074 0, /* 43 reserved */
10075 0, /* 44 reserved */
10076 0, /* 45 reserved */
10077 0, /* 46 reserved */
10078 0, /* 47 reserved */
10079 0, /* 48 reserved */
10080 0, /* 49 reserved */
10081 0, /* 50 reserved */
10082 0, /* 51 reserved */
10083 0, /* 52 reserved */
10084 0, /* 53 reserved */
10085 0, /* 54 reserved */
10086 0, /* 55 reserved */
10087 0, /* 56 cisptr_lsw */
10088 0, /* 57 cisprt_msw */
10089 0, /* 58 subsysvid */
10090 0, /* 59 subsysid */
10091 0, /* 60 reserved */
10092 0, /* 61 reserved */
10093 0, /* 62 reserved */
10094 0 /* 63 reserved */
10095 };
10096
10097 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config = {
10098 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
10099 0x0000, /* 01 cfg_msw */
10100 0xFFFF, /* 02 disc_enable */
10101 0xFFFF, /* 03 wdtr_able */
10102 0x5555, /* 04 sdtr_speed1 */
10103 0xFFFF, /* 05 start_motor */
10104 0xFFFF, /* 06 tagqng_able */
10105 0xFFFF, /* 07 bios_scan */
10106 0, /* 08 scam_tolerant */
10107 7, /* 09 adapter_scsi_id */
10108 0, /* bios_boot_delay */
10109 3, /* 10 scsi_reset_delay */
10110 0, /* bios_id_lun */
10111 0, /* 11 termination_se */
10112 0, /* termination_lvd */
10113 0xFFE7, /* 12 bios_ctrl */
10114 0x5555, /* 13 sdtr_speed2 */
10115 0x5555, /* 14 sdtr_speed3 */
10116 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
10117 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
10118 0, /* 16 dvc_cntl */
10119 0x5555, /* 17 sdtr_speed4 */
10120 0, /* 18 serial_number_word1 */
10121 0, /* 19 serial_number_word2 */
10122 0, /* 20 serial_number_word3 */
10123 0, /* 21 check_sum */
10124 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
10125 , /* 22-29 oem_name[16] */
10126 0, /* 30 dvc_err_code */
10127 0, /* 31 adv_err_code */
10128 0, /* 32 adv_err_addr */
10129 0, /* 33 saved_dvc_err_code */
10130 0, /* 34 saved_adv_err_code */
10131 0, /* 35 saved_adv_err_addr */
10132 0, /* 36 reserved */
10133 0, /* 37 reserved */
10134 0, /* 38 reserved */
10135 0, /* 39 reserved */
10136 0, /* 40 reserved */
10137 0, /* 41 reserved */
10138 0, /* 42 reserved */
10139 0, /* 43 reserved */
10140 0, /* 44 reserved */
10141 0, /* 45 reserved */
10142 0, /* 46 reserved */
10143 0, /* 47 reserved */
10144 0, /* 48 reserved */
10145 0, /* 49 reserved */
10146 0, /* 50 reserved */
10147 0, /* 51 reserved */
10148 0, /* 52 reserved */
10149 0, /* 53 reserved */
10150 0, /* 54 reserved */
10151 0, /* 55 reserved */
10152 0, /* 56 cisptr_lsw */
10153 0, /* 57 cisprt_msw */
10154 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
10155 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
10156 0, /* 60 reserved */
10157 0, /* 61 reserved */
10158 0, /* 62 reserved */
10159 0 /* 63 reserved */
10160 };
10161
10162 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar = {
10163 0, /* 00 cfg_lsw */
10164 0, /* 01 cfg_msw */
10165 0, /* 02 disc_enable */
10166 0, /* 03 wdtr_able */
10167 0, /* 04 sdtr_speed1 */
10168 0, /* 05 start_motor */
10169 0, /* 06 tagqng_able */
10170 0, /* 07 bios_scan */
10171 0, /* 08 scam_tolerant */
10172 1, /* 09 adapter_scsi_id */
10173 1, /* bios_boot_delay */
10174 1, /* 10 scsi_reset_delay */
10175 1, /* bios_id_lun */
10176 1, /* 11 termination_se */
10177 1, /* termination_lvd */
10178 0, /* 12 bios_ctrl */
10179 0, /* 13 sdtr_speed2 */
10180 0, /* 14 sdtr_speed3 */
10181 1, /* 15 max_host_qng */
10182 1, /* max_dvc_qng */
10183 0, /* 16 dvc_cntl */
10184 0, /* 17 sdtr_speed4 */
10185 0, /* 18 serial_number_word1 */
10186 0, /* 19 serial_number_word2 */
10187 0, /* 20 serial_number_word3 */
10188 0, /* 21 check_sum */
10189 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
10190 , /* 22-29 oem_name[16] */
10191 0, /* 30 dvc_err_code */
10192 0, /* 31 adv_err_code */
10193 0, /* 32 adv_err_addr */
10194 0, /* 33 saved_dvc_err_code */
10195 0, /* 34 saved_adv_err_code */
10196 0, /* 35 saved_adv_err_addr */
10197 0, /* 36 reserved */
10198 0, /* 37 reserved */
10199 0, /* 38 reserved */
10200 0, /* 39 reserved */
10201 0, /* 40 reserved */
10202 0, /* 41 reserved */
10203 0, /* 42 reserved */
10204 0, /* 43 reserved */
10205 0, /* 44 reserved */
10206 0, /* 45 reserved */
10207 0, /* 46 reserved */
10208 0, /* 47 reserved */
10209 0, /* 48 reserved */
10210 0, /* 49 reserved */
10211 0, /* 50 reserved */
10212 0, /* 51 reserved */
10213 0, /* 52 reserved */
10214 0, /* 53 reserved */
10215 0, /* 54 reserved */
10216 0, /* 55 reserved */
10217 0, /* 56 cisptr_lsw */
10218 0, /* 57 cisprt_msw */
10219 0, /* 58 subsysvid */
10220 0, /* 59 subsysid */
10221 0, /* 60 reserved */
10222 0, /* 61 reserved */
10223 0, /* 62 reserved */
10224 0 /* 63 reserved */
10225 };
10226
10227 #ifdef CONFIG_PCI
10228 /*
10229 * Wait for EEPROM command to complete
10230 */
10231 static void AdvWaitEEPCmd(AdvPortAddr iop_base)
10232 {
10233 int eep_delay_ms;
10234
10235 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
10236 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
10237 ASC_EEP_CMD_DONE) {
10238 break;
10239 }
10240 mdelay(1);
10241 }
10242 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
10243 0)
10244 BUG();
10245 }
10246
10247 /*
10248 * Read the EEPROM from specified location
10249 */
10250 static ushort AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
10251 {
10252 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10253 ASC_EEP_CMD_READ | eep_word_addr);
10254 AdvWaitEEPCmd(iop_base);
10255 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
10256 }
10257
10258 /*
10259 * Write the EEPROM from 'cfg_buf'.
10260 */
10261 static void AdvSet3550EEPConfig(AdvPortAddr iop_base,
10262 ADVEEP_3550_CONFIG *cfg_buf)
10263 {
10264 ushort *wbuf;
10265 ushort addr, chksum;
10266 ushort *charfields;
10267
10268 wbuf = (ushort *)cfg_buf;
10269 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
10270 chksum = 0;
10271
10272 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10273 AdvWaitEEPCmd(iop_base);
10274
10275 /*
10276 * Write EEPROM from word 0 to word 20.
10277 */
10278 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10279 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10280 ushort word;
10281
10282 if (*charfields++) {
10283 word = cpu_to_le16(*wbuf);
10284 } else {
10285 word = *wbuf;
10286 }
10287 chksum += *wbuf; /* Checksum is calculated from word values. */
10288 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10289 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10290 ASC_EEP_CMD_WRITE | addr);
10291 AdvWaitEEPCmd(iop_base);
10292 mdelay(ADV_EEP_DELAY_MS);
10293 }
10294
10295 /*
10296 * Write EEPROM checksum at word 21.
10297 */
10298 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10299 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10300 AdvWaitEEPCmd(iop_base);
10301 wbuf++;
10302 charfields++;
10303
10304 /*
10305 * Write EEPROM OEM name at words 22 to 29.
10306 */
10307 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10308 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10309 ushort word;
10310
10311 if (*charfields++) {
10312 word = cpu_to_le16(*wbuf);
10313 } else {
10314 word = *wbuf;
10315 }
10316 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10317 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10318 ASC_EEP_CMD_WRITE | addr);
10319 AdvWaitEEPCmd(iop_base);
10320 }
10321 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10322 AdvWaitEEPCmd(iop_base);
10323 }
10324
10325 /*
10326 * Write the EEPROM from 'cfg_buf'.
10327 */
10328 static void AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
10329 ADVEEP_38C0800_CONFIG *cfg_buf)
10330 {
10331 ushort *wbuf;
10332 ushort *charfields;
10333 ushort addr, chksum;
10334
10335 wbuf = (ushort *)cfg_buf;
10336 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10337 chksum = 0;
10338
10339 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10340 AdvWaitEEPCmd(iop_base);
10341
10342 /*
10343 * Write EEPROM from word 0 to word 20.
10344 */
10345 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10346 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10347 ushort word;
10348
10349 if (*charfields++) {
10350 word = cpu_to_le16(*wbuf);
10351 } else {
10352 word = *wbuf;
10353 }
10354 chksum += *wbuf; /* Checksum is calculated from word values. */
10355 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10356 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10357 ASC_EEP_CMD_WRITE | addr);
10358 AdvWaitEEPCmd(iop_base);
10359 mdelay(ADV_EEP_DELAY_MS);
10360 }
10361
10362 /*
10363 * Write EEPROM checksum at word 21.
10364 */
10365 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10366 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10367 AdvWaitEEPCmd(iop_base);
10368 wbuf++;
10369 charfields++;
10370
10371 /*
10372 * Write EEPROM OEM name at words 22 to 29.
10373 */
10374 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10375 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10376 ushort word;
10377
10378 if (*charfields++) {
10379 word = cpu_to_le16(*wbuf);
10380 } else {
10381 word = *wbuf;
10382 }
10383 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10384 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10385 ASC_EEP_CMD_WRITE | addr);
10386 AdvWaitEEPCmd(iop_base);
10387 }
10388 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10389 AdvWaitEEPCmd(iop_base);
10390 }
10391
10392 /*
10393 * Write the EEPROM from 'cfg_buf'.
10394 */
10395 static void AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
10396 ADVEEP_38C1600_CONFIG *cfg_buf)
10397 {
10398 ushort *wbuf;
10399 ushort *charfields;
10400 ushort addr, chksum;
10401
10402 wbuf = (ushort *)cfg_buf;
10403 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
10404 chksum = 0;
10405
10406 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10407 AdvWaitEEPCmd(iop_base);
10408
10409 /*
10410 * Write EEPROM from word 0 to word 20.
10411 */
10412 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10413 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10414 ushort word;
10415
10416 if (*charfields++) {
10417 word = cpu_to_le16(*wbuf);
10418 } else {
10419 word = *wbuf;
10420 }
10421 chksum += *wbuf; /* Checksum is calculated from word values. */
10422 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10423 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10424 ASC_EEP_CMD_WRITE | addr);
10425 AdvWaitEEPCmd(iop_base);
10426 mdelay(ADV_EEP_DELAY_MS);
10427 }
10428
10429 /*
10430 * Write EEPROM checksum at word 21.
10431 */
10432 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10433 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10434 AdvWaitEEPCmd(iop_base);
10435 wbuf++;
10436 charfields++;
10437
10438 /*
10439 * Write EEPROM OEM name at words 22 to 29.
10440 */
10441 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10442 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10443 ushort word;
10444
10445 if (*charfields++) {
10446 word = cpu_to_le16(*wbuf);
10447 } else {
10448 word = *wbuf;
10449 }
10450 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10451 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10452 ASC_EEP_CMD_WRITE | addr);
10453 AdvWaitEEPCmd(iop_base);
10454 }
10455 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10456 AdvWaitEEPCmd(iop_base);
10457 }
10458
10459 /*
10460 * Read EEPROM configuration into the specified buffer.
10461 *
10462 * Return a checksum based on the EEPROM configuration read.
10463 */
10464 static ushort AdvGet3550EEPConfig(AdvPortAddr iop_base,
10465 ADVEEP_3550_CONFIG *cfg_buf)
10466 {
10467 ushort wval, chksum;
10468 ushort *wbuf;
10469 int eep_addr;
10470 ushort *charfields;
10471
10472 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
10473 wbuf = (ushort *)cfg_buf;
10474 chksum = 0;
10475
10476 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10477 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10478 wval = AdvReadEEPWord(iop_base, eep_addr);
10479 chksum += wval; /* Checksum is calculated from word values. */
10480 if (*charfields++) {
10481 *wbuf = le16_to_cpu(wval);
10482 } else {
10483 *wbuf = wval;
10484 }
10485 }
10486 /* Read checksum word. */
10487 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10488 wbuf++;
10489 charfields++;
10490
10491 /* Read rest of EEPROM not covered by the checksum. */
10492 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10493 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10494 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10495 if (*charfields++) {
10496 *wbuf = le16_to_cpu(*wbuf);
10497 }
10498 }
10499 return chksum;
10500 }
10501
10502 /*
10503 * Read EEPROM configuration into the specified buffer.
10504 *
10505 * Return a checksum based on the EEPROM configuration read.
10506 */
10507 static ushort AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
10508 ADVEEP_38C0800_CONFIG *cfg_buf)
10509 {
10510 ushort wval, chksum;
10511 ushort *wbuf;
10512 int eep_addr;
10513 ushort *charfields;
10514
10515 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10516 wbuf = (ushort *)cfg_buf;
10517 chksum = 0;
10518
10519 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10520 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10521 wval = AdvReadEEPWord(iop_base, eep_addr);
10522 chksum += wval; /* Checksum is calculated from word values. */
10523 if (*charfields++) {
10524 *wbuf = le16_to_cpu(wval);
10525 } else {
10526 *wbuf = wval;
10527 }
10528 }
10529 /* Read checksum word. */
10530 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10531 wbuf++;
10532 charfields++;
10533
10534 /* Read rest of EEPROM not covered by the checksum. */
10535 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10536 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10537 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10538 if (*charfields++) {
10539 *wbuf = le16_to_cpu(*wbuf);
10540 }
10541 }
10542 return chksum;
10543 }
10544
10545 /*
10546 * Read EEPROM configuration into the specified buffer.
10547 *
10548 * Return a checksum based on the EEPROM configuration read.
10549 */
10550 static ushort AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
10551 ADVEEP_38C1600_CONFIG *cfg_buf)
10552 {
10553 ushort wval, chksum;
10554 ushort *wbuf;
10555 int eep_addr;
10556 ushort *charfields;
10557
10558 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
10559 wbuf = (ushort *)cfg_buf;
10560 chksum = 0;
10561
10562 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10563 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10564 wval = AdvReadEEPWord(iop_base, eep_addr);
10565 chksum += wval; /* Checksum is calculated from word values. */
10566 if (*charfields++) {
10567 *wbuf = le16_to_cpu(wval);
10568 } else {
10569 *wbuf = wval;
10570 }
10571 }
10572 /* Read checksum word. */
10573 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10574 wbuf++;
10575 charfields++;
10576
10577 /* Read rest of EEPROM not covered by the checksum. */
10578 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10579 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10580 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10581 if (*charfields++) {
10582 *wbuf = le16_to_cpu(*wbuf);
10583 }
10584 }
10585 return chksum;
10586 }
10587
10588 /*
10589 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10590 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10591 * all of this is done.
10592 *
10593 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10594 *
10595 * For a non-fatal error return a warning code. If there are no warnings
10596 * then 0 is returned.
10597 *
10598 * Note: Chip is stopped on entry.
10599 */
10600 static int AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
10601 {
10602 AdvPortAddr iop_base;
10603 ushort warn_code;
10604 ADVEEP_3550_CONFIG eep_config;
10605
10606 iop_base = asc_dvc->iop_base;
10607
10608 warn_code = 0;
10609
10610 /*
10611 * Read the board's EEPROM configuration.
10612 *
10613 * Set default values if a bad checksum is found.
10614 */
10615 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
10616 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10617
10618 /*
10619 * Set EEPROM default values.
10620 */
10621 memcpy(&eep_config, &Default_3550_EEPROM_Config,
10622 sizeof(ADVEEP_3550_CONFIG));
10623
10624 /*
10625 * Assume the 6 byte board serial number that was read from
10626 * EEPROM is correct even if the EEPROM checksum failed.
10627 */
10628 eep_config.serial_number_word3 =
10629 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10630
10631 eep_config.serial_number_word2 =
10632 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10633
10634 eep_config.serial_number_word1 =
10635 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10636
10637 AdvSet3550EEPConfig(iop_base, &eep_config);
10638 }
10639 /*
10640 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10641 * EEPROM configuration that was read.
10642 *
10643 * This is the mapping of EEPROM fields to Adv Library fields.
10644 */
10645 asc_dvc->wdtr_able = eep_config.wdtr_able;
10646 asc_dvc->sdtr_able = eep_config.sdtr_able;
10647 asc_dvc->ultra_able = eep_config.ultra_able;
10648 asc_dvc->tagqng_able = eep_config.tagqng_able;
10649 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10650 asc_dvc->max_host_qng = eep_config.max_host_qng;
10651 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10652 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10653 asc_dvc->start_motor = eep_config.start_motor;
10654 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10655 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10656 asc_dvc->no_scam = eep_config.scam_tolerant;
10657 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10658 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10659 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
10660
10661 /*
10662 * Set the host maximum queuing (max. 253, min. 16) and the per device
10663 * maximum queuing (max. 63, min. 4).
10664 */
10665 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10666 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10667 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10668 /* If the value is zero, assume it is uninitialized. */
10669 if (eep_config.max_host_qng == 0) {
10670 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10671 } else {
10672 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10673 }
10674 }
10675
10676 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10677 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10678 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10679 /* If the value is zero, assume it is uninitialized. */
10680 if (eep_config.max_dvc_qng == 0) {
10681 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10682 } else {
10683 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10684 }
10685 }
10686
10687 /*
10688 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10689 * set 'max_dvc_qng' to 'max_host_qng'.
10690 */
10691 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10692 eep_config.max_dvc_qng = eep_config.max_host_qng;
10693 }
10694
10695 /*
10696 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10697 * values based on possibly adjusted EEPROM values.
10698 */
10699 asc_dvc->max_host_qng = eep_config.max_host_qng;
10700 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10701
10702 /*
10703 * If the EEPROM 'termination' field is set to automatic (0), then set
10704 * the ADV_DVC_CFG 'termination' field to automatic also.
10705 *
10706 * If the termination is specified with a non-zero 'termination'
10707 * value check that a legal value is set and set the ADV_DVC_CFG
10708 * 'termination' field appropriately.
10709 */
10710 if (eep_config.termination == 0) {
10711 asc_dvc->cfg->termination = 0; /* auto termination */
10712 } else {
10713 /* Enable manual control with low off / high off. */
10714 if (eep_config.termination == 1) {
10715 asc_dvc->cfg->termination = TERM_CTL_SEL;
10716
10717 /* Enable manual control with low off / high on. */
10718 } else if (eep_config.termination == 2) {
10719 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
10720
10721 /* Enable manual control with low on / high on. */
10722 } else if (eep_config.termination == 3) {
10723 asc_dvc->cfg->termination =
10724 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
10725 } else {
10726 /*
10727 * The EEPROM 'termination' field contains a bad value. Use
10728 * automatic termination instead.
10729 */
10730 asc_dvc->cfg->termination = 0;
10731 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10732 }
10733 }
10734
10735 return warn_code;
10736 }
10737
10738 /*
10739 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10740 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10741 * all of this is done.
10742 *
10743 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10744 *
10745 * For a non-fatal error return a warning code. If there are no warnings
10746 * then 0 is returned.
10747 *
10748 * Note: Chip is stopped on entry.
10749 */
10750 static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
10751 {
10752 AdvPortAddr iop_base;
10753 ushort warn_code;
10754 ADVEEP_38C0800_CONFIG eep_config;
10755 uchar tid, termination;
10756 ushort sdtr_speed = 0;
10757
10758 iop_base = asc_dvc->iop_base;
10759
10760 warn_code = 0;
10761
10762 /*
10763 * Read the board's EEPROM configuration.
10764 *
10765 * Set default values if a bad checksum is found.
10766 */
10767 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
10768 eep_config.check_sum) {
10769 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10770
10771 /*
10772 * Set EEPROM default values.
10773 */
10774 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
10775 sizeof(ADVEEP_38C0800_CONFIG));
10776
10777 /*
10778 * Assume the 6 byte board serial number that was read from
10779 * EEPROM is correct even if the EEPROM checksum failed.
10780 */
10781 eep_config.serial_number_word3 =
10782 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10783
10784 eep_config.serial_number_word2 =
10785 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10786
10787 eep_config.serial_number_word1 =
10788 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10789
10790 AdvSet38C0800EEPConfig(iop_base, &eep_config);
10791 }
10792 /*
10793 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
10794 * EEPROM configuration that was read.
10795 *
10796 * This is the mapping of EEPROM fields to Adv Library fields.
10797 */
10798 asc_dvc->wdtr_able = eep_config.wdtr_able;
10799 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10800 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10801 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10802 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10803 asc_dvc->tagqng_able = eep_config.tagqng_able;
10804 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10805 asc_dvc->max_host_qng = eep_config.max_host_qng;
10806 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10807 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10808 asc_dvc->start_motor = eep_config.start_motor;
10809 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10810 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10811 asc_dvc->no_scam = eep_config.scam_tolerant;
10812 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10813 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10814 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
10815
10816 /*
10817 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10818 * are set, then set an 'sdtr_able' bit for it.
10819 */
10820 asc_dvc->sdtr_able = 0;
10821 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
10822 if (tid == 0) {
10823 sdtr_speed = asc_dvc->sdtr_speed1;
10824 } else if (tid == 4) {
10825 sdtr_speed = asc_dvc->sdtr_speed2;
10826 } else if (tid == 8) {
10827 sdtr_speed = asc_dvc->sdtr_speed3;
10828 } else if (tid == 12) {
10829 sdtr_speed = asc_dvc->sdtr_speed4;
10830 }
10831 if (sdtr_speed & ADV_MAX_TID) {
10832 asc_dvc->sdtr_able |= (1 << tid);
10833 }
10834 sdtr_speed >>= 4;
10835 }
10836
10837 /*
10838 * Set the host maximum queuing (max. 253, min. 16) and the per device
10839 * maximum queuing (max. 63, min. 4).
10840 */
10841 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10842 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10843 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10844 /* If the value is zero, assume it is uninitialized. */
10845 if (eep_config.max_host_qng == 0) {
10846 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10847 } else {
10848 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10849 }
10850 }
10851
10852 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10853 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10854 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10855 /* If the value is zero, assume it is uninitialized. */
10856 if (eep_config.max_dvc_qng == 0) {
10857 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10858 } else {
10859 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10860 }
10861 }
10862
10863 /*
10864 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10865 * set 'max_dvc_qng' to 'max_host_qng'.
10866 */
10867 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10868 eep_config.max_dvc_qng = eep_config.max_host_qng;
10869 }
10870
10871 /*
10872 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10873 * values based on possibly adjusted EEPROM values.
10874 */
10875 asc_dvc->max_host_qng = eep_config.max_host_qng;
10876 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10877
10878 /*
10879 * If the EEPROM 'termination' field is set to automatic (0), then set
10880 * the ADV_DVC_CFG 'termination' field to automatic also.
10881 *
10882 * If the termination is specified with a non-zero 'termination'
10883 * value check that a legal value is set and set the ADV_DVC_CFG
10884 * 'termination' field appropriately.
10885 */
10886 if (eep_config.termination_se == 0) {
10887 termination = 0; /* auto termination for SE */
10888 } else {
10889 /* Enable manual control with low off / high off. */
10890 if (eep_config.termination_se == 1) {
10891 termination = 0;
10892
10893 /* Enable manual control with low off / high on. */
10894 } else if (eep_config.termination_se == 2) {
10895 termination = TERM_SE_HI;
10896
10897 /* Enable manual control with low on / high on. */
10898 } else if (eep_config.termination_se == 3) {
10899 termination = TERM_SE;
10900 } else {
10901 /*
10902 * The EEPROM 'termination_se' field contains a bad value.
10903 * Use automatic termination instead.
10904 */
10905 termination = 0;
10906 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10907 }
10908 }
10909
10910 if (eep_config.termination_lvd == 0) {
10911 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10912 } else {
10913 /* Enable manual control with low off / high off. */
10914 if (eep_config.termination_lvd == 1) {
10915 asc_dvc->cfg->termination = termination;
10916
10917 /* Enable manual control with low off / high on. */
10918 } else if (eep_config.termination_lvd == 2) {
10919 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10920
10921 /* Enable manual control with low on / high on. */
10922 } else if (eep_config.termination_lvd == 3) {
10923 asc_dvc->cfg->termination = termination | TERM_LVD;
10924 } else {
10925 /*
10926 * The EEPROM 'termination_lvd' field contains a bad value.
10927 * Use automatic termination instead.
10928 */
10929 asc_dvc->cfg->termination = termination;
10930 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10931 }
10932 }
10933
10934 return warn_code;
10935 }
10936
10937 /*
10938 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
10939 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
10940 * all of this is done.
10941 *
10942 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
10943 *
10944 * For a non-fatal error return a warning code. If there are no warnings
10945 * then 0 is returned.
10946 *
10947 * Note: Chip is stopped on entry.
10948 */
10949 static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
10950 {
10951 AdvPortAddr iop_base;
10952 ushort warn_code;
10953 ADVEEP_38C1600_CONFIG eep_config;
10954 uchar tid, termination;
10955 ushort sdtr_speed = 0;
10956
10957 iop_base = asc_dvc->iop_base;
10958
10959 warn_code = 0;
10960
10961 /*
10962 * Read the board's EEPROM configuration.
10963 *
10964 * Set default values if a bad checksum is found.
10965 */
10966 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
10967 eep_config.check_sum) {
10968 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
10969 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10970
10971 /*
10972 * Set EEPROM default values.
10973 */
10974 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
10975 sizeof(ADVEEP_38C1600_CONFIG));
10976
10977 if (PCI_FUNC(pdev->devfn) != 0) {
10978 u8 ints;
10979 /*
10980 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
10981 * and old Mac system booting problem. The Expansion
10982 * ROM must be disabled in Function 1 for these systems
10983 */
10984 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
10985 /*
10986 * Clear the INTAB (bit 11) if the GPIO 0 input
10987 * indicates the Function 1 interrupt line is wired
10988 * to INTB.
10989 *
10990 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
10991 * 1 - Function 1 interrupt line wired to INT A.
10992 * 0 - Function 1 interrupt line wired to INT B.
10993 *
10994 * Note: Function 0 is always wired to INTA.
10995 * Put all 5 GPIO bits in input mode and then read
10996 * their input values.
10997 */
10998 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
10999 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
11000 if ((ints & 0x01) == 0)
11001 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
11002 }
11003
11004 /*
11005 * Assume the 6 byte board serial number that was read from
11006 * EEPROM is correct even if the EEPROM checksum failed.
11007 */
11008 eep_config.serial_number_word3 =
11009 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
11010 eep_config.serial_number_word2 =
11011 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
11012 eep_config.serial_number_word1 =
11013 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
11014
11015 AdvSet38C1600EEPConfig(iop_base, &eep_config);
11016 }
11017
11018 /*
11019 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
11020 * EEPROM configuration that was read.
11021 *
11022 * This is the mapping of EEPROM fields to Adv Library fields.
11023 */
11024 asc_dvc->wdtr_able = eep_config.wdtr_able;
11025 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
11026 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
11027 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
11028 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
11029 asc_dvc->ppr_able = 0;
11030 asc_dvc->tagqng_able = eep_config.tagqng_able;
11031 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
11032 asc_dvc->max_host_qng = eep_config.max_host_qng;
11033 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
11034 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
11035 asc_dvc->start_motor = eep_config.start_motor;
11036 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
11037 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
11038 asc_dvc->no_scam = eep_config.scam_tolerant;
11039
11040 /*
11041 * For every Target ID if any of its 'sdtr_speed[1234]' bits
11042 * are set, then set an 'sdtr_able' bit for it.
11043 */
11044 asc_dvc->sdtr_able = 0;
11045 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
11046 if (tid == 0) {
11047 sdtr_speed = asc_dvc->sdtr_speed1;
11048 } else if (tid == 4) {
11049 sdtr_speed = asc_dvc->sdtr_speed2;
11050 } else if (tid == 8) {
11051 sdtr_speed = asc_dvc->sdtr_speed3;
11052 } else if (tid == 12) {
11053 sdtr_speed = asc_dvc->sdtr_speed4;
11054 }
11055 if (sdtr_speed & ASC_MAX_TID) {
11056 asc_dvc->sdtr_able |= (1 << tid);
11057 }
11058 sdtr_speed >>= 4;
11059 }
11060
11061 /*
11062 * Set the host maximum queuing (max. 253, min. 16) and the per device
11063 * maximum queuing (max. 63, min. 4).
11064 */
11065 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
11066 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
11067 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
11068 /* If the value is zero, assume it is uninitialized. */
11069 if (eep_config.max_host_qng == 0) {
11070 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
11071 } else {
11072 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
11073 }
11074 }
11075
11076 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
11077 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
11078 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
11079 /* If the value is zero, assume it is uninitialized. */
11080 if (eep_config.max_dvc_qng == 0) {
11081 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
11082 } else {
11083 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
11084 }
11085 }
11086
11087 /*
11088 * If 'max_dvc_qng' is greater than 'max_host_qng', then
11089 * set 'max_dvc_qng' to 'max_host_qng'.
11090 */
11091 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
11092 eep_config.max_dvc_qng = eep_config.max_host_qng;
11093 }
11094
11095 /*
11096 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
11097 * values based on possibly adjusted EEPROM values.
11098 */
11099 asc_dvc->max_host_qng = eep_config.max_host_qng;
11100 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
11101
11102 /*
11103 * If the EEPROM 'termination' field is set to automatic (0), then set
11104 * the ASC_DVC_CFG 'termination' field to automatic also.
11105 *
11106 * If the termination is specified with a non-zero 'termination'
11107 * value check that a legal value is set and set the ASC_DVC_CFG
11108 * 'termination' field appropriately.
11109 */
11110 if (eep_config.termination_se == 0) {
11111 termination = 0; /* auto termination for SE */
11112 } else {
11113 /* Enable manual control with low off / high off. */
11114 if (eep_config.termination_se == 1) {
11115 termination = 0;
11116
11117 /* Enable manual control with low off / high on. */
11118 } else if (eep_config.termination_se == 2) {
11119 termination = TERM_SE_HI;
11120
11121 /* Enable manual control with low on / high on. */
11122 } else if (eep_config.termination_se == 3) {
11123 termination = TERM_SE;
11124 } else {
11125 /*
11126 * The EEPROM 'termination_se' field contains a bad value.
11127 * Use automatic termination instead.
11128 */
11129 termination = 0;
11130 warn_code |= ASC_WARN_EEPROM_TERMINATION;
11131 }
11132 }
11133
11134 if (eep_config.termination_lvd == 0) {
11135 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
11136 } else {
11137 /* Enable manual control with low off / high off. */
11138 if (eep_config.termination_lvd == 1) {
11139 asc_dvc->cfg->termination = termination;
11140
11141 /* Enable manual control with low off / high on. */
11142 } else if (eep_config.termination_lvd == 2) {
11143 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
11144
11145 /* Enable manual control with low on / high on. */
11146 } else if (eep_config.termination_lvd == 3) {
11147 asc_dvc->cfg->termination = termination | TERM_LVD;
11148 } else {
11149 /*
11150 * The EEPROM 'termination_lvd' field contains a bad value.
11151 * Use automatic termination instead.
11152 */
11153 asc_dvc->cfg->termination = termination;
11154 warn_code |= ASC_WARN_EEPROM_TERMINATION;
11155 }
11156 }
11157
11158 return warn_code;
11159 }
11160
11161 /*
11162 * Initialize the ADV_DVC_VAR structure.
11163 *
11164 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
11165 *
11166 * For a non-fatal error return a warning code. If there are no warnings
11167 * then 0 is returned.
11168 */
11169 static int AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
11170 {
11171 struct asc_board *board = shost_priv(shost);
11172 ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var;
11173 unsigned short warn_code = 0;
11174 AdvPortAddr iop_base = asc_dvc->iop_base;
11175 u16 cmd;
11176 int status;
11177
11178 asc_dvc->err_code = 0;
11179
11180 /*
11181 * Save the state of the PCI Configuration Command Register
11182 * "Parity Error Response Control" Bit. If the bit is clear (0),
11183 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
11184 * DMA parity errors.
11185 */
11186 asc_dvc->cfg->control_flag = 0;
11187 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
11188 if ((cmd & PCI_COMMAND_PARITY) == 0)
11189 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
11190
11191 asc_dvc->cfg->chip_version =
11192 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
11193
11194 ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
11195 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
11196 (ushort)ADV_CHIP_ID_BYTE);
11197
11198 ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
11199 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
11200 (ushort)ADV_CHIP_ID_WORD);
11201
11202 /*
11203 * Reset the chip to start and allow register writes.
11204 */
11205 if (AdvFindSignature(iop_base) == 0) {
11206 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11207 return ADV_ERROR;
11208 } else {
11209 /*
11210 * The caller must set 'chip_type' to a valid setting.
11211 */
11212 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
11213 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
11214 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
11215 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
11216 return ADV_ERROR;
11217 }
11218
11219 /*
11220 * Reset Chip.
11221 */
11222 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11223 ADV_CTRL_REG_CMD_RESET);
11224 mdelay(100);
11225 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11226 ADV_CTRL_REG_CMD_WR_IO_REG);
11227
11228 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
11229 status = AdvInitFrom38C1600EEP(asc_dvc);
11230 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11231 status = AdvInitFrom38C0800EEP(asc_dvc);
11232 } else {
11233 status = AdvInitFrom3550EEP(asc_dvc);
11234 }
11235 warn_code |= status;
11236 }
11237
11238 if (warn_code != 0)
11239 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code);
11240
11241 if (asc_dvc->err_code)
11242 shost_printk(KERN_ERR, shost, "error code 0x%x\n",
11243 asc_dvc->err_code);
11244
11245 return asc_dvc->err_code;
11246 }
11247 #endif
11248
11249 static struct scsi_host_template advansys_template = {
11250 .proc_name = DRV_NAME,
11251 #ifdef CONFIG_PROC_FS
11252 .show_info = advansys_show_info,
11253 #endif
11254 .name = DRV_NAME,
11255 .info = advansys_info,
11256 .queuecommand = advansys_queuecommand,
11257 .eh_bus_reset_handler = advansys_reset,
11258 .bios_param = advansys_biosparam,
11259 .slave_configure = advansys_slave_configure,
11260 /*
11261 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
11262 * must be set. The flag will be cleared in advansys_board_found
11263 * for non-ISA adapters.
11264 */
11265 .unchecked_isa_dma = 1,
11266 /*
11267 * All adapters controlled by this driver are capable of large
11268 * scatter-gather lists. According to the mid-level SCSI documentation
11269 * this obviates any performance gain provided by setting
11270 * 'use_clustering'. But empirically while CPU utilization is increased
11271 * by enabling clustering, I/O throughput increases as well.
11272 */
11273 .use_clustering = ENABLE_CLUSTERING,
11274 };
11275
11276 static int advansys_wide_init_chip(struct Scsi_Host *shost)
11277 {
11278 struct asc_board *board = shost_priv(shost);
11279 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
11280 int req_cnt = 0;
11281 adv_req_t *reqp = NULL;
11282 int sg_cnt = 0;
11283 adv_sgblk_t *sgp;
11284 int warn_code, err_code;
11285
11286 /*
11287 * Allocate buffer carrier structures. The total size
11288 * is about 4 KB, so allocate all at once.
11289 */
11290 adv_dvc->carrier_buf = kmalloc(ADV_CARRIER_BUFSIZE, GFP_KERNEL);
11291 ASC_DBG(1, "carrier_buf 0x%p\n", adv_dvc->carrier_buf);
11292
11293 if (!adv_dvc->carrier_buf)
11294 goto kmalloc_failed;
11295
11296 /*
11297 * Allocate up to 'max_host_qng' request structures for the Wide
11298 * board. The total size is about 16 KB, so allocate all at once.
11299 * If the allocation fails decrement and try again.
11300 */
11301 for (req_cnt = adv_dvc->max_host_qng; req_cnt > 0; req_cnt--) {
11302 reqp = kmalloc(sizeof(adv_req_t) * req_cnt, GFP_KERNEL);
11303
11304 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", reqp, req_cnt,
11305 (ulong)sizeof(adv_req_t) * req_cnt);
11306
11307 if (reqp)
11308 break;
11309 }
11310
11311 if (!reqp)
11312 goto kmalloc_failed;
11313
11314 adv_dvc->orig_reqp = reqp;
11315
11316 /*
11317 * Allocate up to ADV_TOT_SG_BLOCK request structures for
11318 * the Wide board. Each structure is about 136 bytes.
11319 */
11320 board->adv_sgblkp = NULL;
11321 for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
11322 sgp = kmalloc(sizeof(adv_sgblk_t), GFP_KERNEL);
11323
11324 if (!sgp)
11325 break;
11326
11327 sgp->next_sgblkp = board->adv_sgblkp;
11328 board->adv_sgblkp = sgp;
11329
11330 }
11331
11332 ASC_DBG(1, "sg_cnt %d * %lu = %lu bytes\n", sg_cnt, sizeof(adv_sgblk_t),
11333 sizeof(adv_sgblk_t) * sg_cnt);
11334
11335 if (!board->adv_sgblkp)
11336 goto kmalloc_failed;
11337
11338 /*
11339 * Point 'adv_reqp' to the request structures and
11340 * link them together.
11341 */
11342 req_cnt--;
11343 reqp[req_cnt].next_reqp = NULL;
11344 for (; req_cnt > 0; req_cnt--) {
11345 reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
11346 }
11347 board->adv_reqp = &reqp[0];
11348
11349 if (adv_dvc->chip_type == ADV_CHIP_ASC3550) {
11350 ASC_DBG(2, "AdvInitAsc3550Driver()\n");
11351 warn_code = AdvInitAsc3550Driver(adv_dvc);
11352 } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11353 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
11354 warn_code = AdvInitAsc38C0800Driver(adv_dvc);
11355 } else {
11356 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
11357 warn_code = AdvInitAsc38C1600Driver(adv_dvc);
11358 }
11359 err_code = adv_dvc->err_code;
11360
11361 if (warn_code || err_code) {
11362 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error "
11363 "0x%x\n", warn_code, err_code);
11364 }
11365
11366 goto exit;
11367
11368 kmalloc_failed:
11369 shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n");
11370 err_code = ADV_ERROR;
11371 exit:
11372 return err_code;
11373 }
11374
11375 static void advansys_wide_free_mem(struct asc_board *board)
11376 {
11377 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
11378 kfree(adv_dvc->carrier_buf);
11379 adv_dvc->carrier_buf = NULL;
11380 kfree(adv_dvc->orig_reqp);
11381 adv_dvc->orig_reqp = board->adv_reqp = NULL;
11382 while (board->adv_sgblkp) {
11383 adv_sgblk_t *sgp = board->adv_sgblkp;
11384 board->adv_sgblkp = sgp->next_sgblkp;
11385 kfree(sgp);
11386 }
11387 }
11388
11389 static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop,
11390 int bus_type)
11391 {
11392 struct pci_dev *pdev;
11393 struct asc_board *boardp = shost_priv(shost);
11394 ASC_DVC_VAR *asc_dvc_varp = NULL;
11395 ADV_DVC_VAR *adv_dvc_varp = NULL;
11396 int share_irq, warn_code, ret;
11397
11398 pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
11399
11400 if (ASC_NARROW_BOARD(boardp)) {
11401 ASC_DBG(1, "narrow board\n");
11402 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
11403 asc_dvc_varp->bus_type = bus_type;
11404 asc_dvc_varp->drv_ptr = boardp;
11405 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
11406 asc_dvc_varp->iop_base = iop;
11407 } else {
11408 #ifdef CONFIG_PCI
11409 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
11410 adv_dvc_varp->drv_ptr = boardp;
11411 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
11412 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
11413 ASC_DBG(1, "wide board ASC-3550\n");
11414 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
11415 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
11416 ASC_DBG(1, "wide board ASC-38C0800\n");
11417 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
11418 } else {
11419 ASC_DBG(1, "wide board ASC-38C1600\n");
11420 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
11421 }
11422
11423 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
11424 boardp->ioremap_addr = pci_ioremap_bar(pdev, 1);
11425 if (!boardp->ioremap_addr) {
11426 shost_printk(KERN_ERR, shost, "ioremap(%lx, %d) "
11427 "returned NULL\n",
11428 (long)pci_resource_start(pdev, 1),
11429 boardp->asc_n_io_port);
11430 ret = -ENODEV;
11431 goto err_shost;
11432 }
11433 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr;
11434 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base);
11435
11436 /*
11437 * Even though it isn't used to access wide boards, other
11438 * than for the debug line below, save I/O Port address so
11439 * that it can be reported.
11440 */
11441 boardp->ioport = iop;
11442
11443 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
11444 (ushort)inp(iop + 1), (ushort)inpw(iop));
11445 #endif /* CONFIG_PCI */
11446 }
11447
11448 if (ASC_NARROW_BOARD(boardp)) {
11449 /*
11450 * Set the board bus type and PCI IRQ before
11451 * calling AscInitGetConfig().
11452 */
11453 switch (asc_dvc_varp->bus_type) {
11454 #ifdef CONFIG_ISA
11455 case ASC_IS_ISA:
11456 shost->unchecked_isa_dma = TRUE;
11457 share_irq = 0;
11458 break;
11459 case ASC_IS_VL:
11460 shost->unchecked_isa_dma = FALSE;
11461 share_irq = 0;
11462 break;
11463 case ASC_IS_EISA:
11464 shost->unchecked_isa_dma = FALSE;
11465 share_irq = IRQF_SHARED;
11466 break;
11467 #endif /* CONFIG_ISA */
11468 #ifdef CONFIG_PCI
11469 case ASC_IS_PCI:
11470 shost->unchecked_isa_dma = FALSE;
11471 share_irq = IRQF_SHARED;
11472 break;
11473 #endif /* CONFIG_PCI */
11474 default:
11475 shost_printk(KERN_ERR, shost, "unknown adapter type: "
11476 "%d\n", asc_dvc_varp->bus_type);
11477 shost->unchecked_isa_dma = TRUE;
11478 share_irq = 0;
11479 break;
11480 }
11481
11482 /*
11483 * NOTE: AscInitGetConfig() may change the board's
11484 * bus_type value. The bus_type value should no
11485 * longer be used. If the bus_type field must be
11486 * referenced only use the bit-wise AND operator "&".
11487 */
11488 ASC_DBG(2, "AscInitGetConfig()\n");
11489 ret = AscInitGetConfig(shost) ? -ENODEV : 0;
11490 } else {
11491 #ifdef CONFIG_PCI
11492 /*
11493 * For Wide boards set PCI information before calling
11494 * AdvInitGetConfig().
11495 */
11496 shost->unchecked_isa_dma = FALSE;
11497 share_irq = IRQF_SHARED;
11498 ASC_DBG(2, "AdvInitGetConfig()\n");
11499
11500 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0;
11501 #endif /* CONFIG_PCI */
11502 }
11503
11504 if (ret)
11505 goto err_unmap;
11506
11507 /*
11508 * Save the EEPROM configuration so that it can be displayed
11509 * from /proc/scsi/advansys/[0...].
11510 */
11511 if (ASC_NARROW_BOARD(boardp)) {
11512
11513 ASCEEP_CONFIG *ep;
11514
11515 /*
11516 * Set the adapter's target id bit in the 'init_tidmask' field.
11517 */
11518 boardp->init_tidmask |=
11519 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
11520
11521 /*
11522 * Save EEPROM settings for the board.
11523 */
11524 ep = &boardp->eep_config.asc_eep;
11525
11526 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
11527 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
11528 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
11529 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
11530 ep->start_motor = asc_dvc_varp->start_motor;
11531 ep->cntl = asc_dvc_varp->dvc_cntl;
11532 ep->no_scam = asc_dvc_varp->no_scam;
11533 ep->max_total_qng = asc_dvc_varp->max_total_qng;
11534 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
11535 /* 'max_tag_qng' is set to the same value for every device. */
11536 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
11537 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
11538 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
11539 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
11540 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
11541 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
11542 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
11543
11544 /*
11545 * Modify board configuration.
11546 */
11547 ASC_DBG(2, "AscInitSetConfig()\n");
11548 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0;
11549 if (ret)
11550 goto err_unmap;
11551 } else {
11552 ADVEEP_3550_CONFIG *ep_3550;
11553 ADVEEP_38C0800_CONFIG *ep_38C0800;
11554 ADVEEP_38C1600_CONFIG *ep_38C1600;
11555
11556 /*
11557 * Save Wide EEP Configuration Information.
11558 */
11559 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
11560 ep_3550 = &boardp->eep_config.adv_3550_eep;
11561
11562 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
11563 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
11564 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11565 ep_3550->termination = adv_dvc_varp->cfg->termination;
11566 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
11567 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
11568 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
11569 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
11570 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
11571 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
11572 ep_3550->start_motor = adv_dvc_varp->start_motor;
11573 ep_3550->scsi_reset_delay =
11574 adv_dvc_varp->scsi_reset_wait;
11575 ep_3550->serial_number_word1 =
11576 adv_dvc_varp->cfg->serial1;
11577 ep_3550->serial_number_word2 =
11578 adv_dvc_varp->cfg->serial2;
11579 ep_3550->serial_number_word3 =
11580 adv_dvc_varp->cfg->serial3;
11581 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
11582 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
11583
11584 ep_38C0800->adapter_scsi_id =
11585 adv_dvc_varp->chip_scsi_id;
11586 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
11587 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11588 ep_38C0800->termination_lvd =
11589 adv_dvc_varp->cfg->termination;
11590 ep_38C0800->disc_enable =
11591 adv_dvc_varp->cfg->disc_enable;
11592 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
11593 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
11594 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11595 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11596 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11597 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11598 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11599 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11600 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
11601 ep_38C0800->scsi_reset_delay =
11602 adv_dvc_varp->scsi_reset_wait;
11603 ep_38C0800->serial_number_word1 =
11604 adv_dvc_varp->cfg->serial1;
11605 ep_38C0800->serial_number_word2 =
11606 adv_dvc_varp->cfg->serial2;
11607 ep_38C0800->serial_number_word3 =
11608 adv_dvc_varp->cfg->serial3;
11609 } else {
11610 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
11611
11612 ep_38C1600->adapter_scsi_id =
11613 adv_dvc_varp->chip_scsi_id;
11614 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
11615 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11616 ep_38C1600->termination_lvd =
11617 adv_dvc_varp->cfg->termination;
11618 ep_38C1600->disc_enable =
11619 adv_dvc_varp->cfg->disc_enable;
11620 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
11621 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
11622 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11623 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11624 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11625 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11626 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11627 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11628 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
11629 ep_38C1600->scsi_reset_delay =
11630 adv_dvc_varp->scsi_reset_wait;
11631 ep_38C1600->serial_number_word1 =
11632 adv_dvc_varp->cfg->serial1;
11633 ep_38C1600->serial_number_word2 =
11634 adv_dvc_varp->cfg->serial2;
11635 ep_38C1600->serial_number_word3 =
11636 adv_dvc_varp->cfg->serial3;
11637 }
11638
11639 /*
11640 * Set the adapter's target id bit in the 'init_tidmask' field.
11641 */
11642 boardp->init_tidmask |=
11643 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
11644 }
11645
11646 /*
11647 * Channels are numbered beginning with 0. For AdvanSys one host
11648 * structure supports one channel. Multi-channel boards have a
11649 * separate host structure for each channel.
11650 */
11651 shost->max_channel = 0;
11652 if (ASC_NARROW_BOARD(boardp)) {
11653 shost->max_id = ASC_MAX_TID + 1;
11654 shost->max_lun = ASC_MAX_LUN + 1;
11655 shost->max_cmd_len = ASC_MAX_CDB_LEN;
11656
11657 shost->io_port = asc_dvc_varp->iop_base;
11658 boardp->asc_n_io_port = ASC_IOADR_GAP;
11659 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
11660
11661 /* Set maximum number of queues the adapter can handle. */
11662 shost->can_queue = asc_dvc_varp->max_total_qng;
11663 } else {
11664 shost->max_id = ADV_MAX_TID + 1;
11665 shost->max_lun = ADV_MAX_LUN + 1;
11666 shost->max_cmd_len = ADV_MAX_CDB_LEN;
11667
11668 /*
11669 * Save the I/O Port address and length even though
11670 * I/O ports are not used to access Wide boards.
11671 * Instead the Wide boards are accessed with
11672 * PCI Memory Mapped I/O.
11673 */
11674 shost->io_port = iop;
11675
11676 shost->this_id = adv_dvc_varp->chip_scsi_id;
11677
11678 /* Set maximum number of queues the adapter can handle. */
11679 shost->can_queue = adv_dvc_varp->max_host_qng;
11680 }
11681
11682 /*
11683 * Following v1.3.89, 'cmd_per_lun' is no longer needed
11684 * and should be set to zero.
11685 *
11686 * But because of a bug introduced in v1.3.89 if the driver is
11687 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
11688 * SCSI function 'allocate_device' will panic. To allow the driver
11689 * to work as a module in these kernels set 'cmd_per_lun' to 1.
11690 *
11691 * Note: This is wrong. cmd_per_lun should be set to the depth
11692 * you want on untagged devices always.
11693 #ifdef MODULE
11694 */
11695 shost->cmd_per_lun = 1;
11696 /* #else
11697 shost->cmd_per_lun = 0;
11698 #endif */
11699
11700 /*
11701 * Set the maximum number of scatter-gather elements the
11702 * adapter can handle.
11703 */
11704 if (ASC_NARROW_BOARD(boardp)) {
11705 /*
11706 * Allow two commands with 'sg_tablesize' scatter-gather
11707 * elements to be executed simultaneously. This value is
11708 * the theoretical hardware limit. It may be decreased
11709 * below.
11710 */
11711 shost->sg_tablesize =
11712 (((asc_dvc_varp->max_total_qng - 2) / 2) *
11713 ASC_SG_LIST_PER_Q) + 1;
11714 } else {
11715 shost->sg_tablesize = ADV_MAX_SG_LIST;
11716 }
11717
11718 /*
11719 * The value of 'sg_tablesize' can not exceed the SCSI
11720 * mid-level driver definition of SG_ALL. SG_ALL also
11721 * must not be exceeded, because it is used to define the
11722 * size of the scatter-gather table in 'struct asc_sg_head'.
11723 */
11724 if (shost->sg_tablesize > SG_ALL) {
11725 shost->sg_tablesize = SG_ALL;
11726 }
11727
11728 ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize);
11729
11730 /* BIOS start address. */
11731 if (ASC_NARROW_BOARD(boardp)) {
11732 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
11733 asc_dvc_varp->bus_type);
11734 } else {
11735 /*
11736 * Fill-in BIOS board variables. The Wide BIOS saves
11737 * information in LRAM that is used by the driver.
11738 */
11739 AdvReadWordLram(adv_dvc_varp->iop_base,
11740 BIOS_SIGNATURE, boardp->bios_signature);
11741 AdvReadWordLram(adv_dvc_varp->iop_base,
11742 BIOS_VERSION, boardp->bios_version);
11743 AdvReadWordLram(adv_dvc_varp->iop_base,
11744 BIOS_CODESEG, boardp->bios_codeseg);
11745 AdvReadWordLram(adv_dvc_varp->iop_base,
11746 BIOS_CODELEN, boardp->bios_codelen);
11747
11748 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
11749 boardp->bios_signature, boardp->bios_version);
11750
11751 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
11752 boardp->bios_codeseg, boardp->bios_codelen);
11753
11754 /*
11755 * If the BIOS saved a valid signature, then fill in
11756 * the BIOS code segment base address.
11757 */
11758 if (boardp->bios_signature == 0x55AA) {
11759 /*
11760 * Convert x86 realmode code segment to a linear
11761 * address by shifting left 4.
11762 */
11763 shost->base = ((ulong)boardp->bios_codeseg << 4);
11764 } else {
11765 shost->base = 0;
11766 }
11767 }
11768
11769 /*
11770 * Register Board Resources - I/O Port, DMA, IRQ
11771 */
11772
11773 /* Register DMA Channel for Narrow boards. */
11774 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
11775 #ifdef CONFIG_ISA
11776 if (ASC_NARROW_BOARD(boardp)) {
11777 /* Register DMA channel for ISA bus. */
11778 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
11779 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
11780 ret = request_dma(shost->dma_channel, DRV_NAME);
11781 if (ret) {
11782 shost_printk(KERN_ERR, shost, "request_dma() "
11783 "%d failed %d\n",
11784 shost->dma_channel, ret);
11785 goto err_unmap;
11786 }
11787 AscEnableIsaDma(shost->dma_channel);
11788 }
11789 }
11790 #endif /* CONFIG_ISA */
11791
11792 /* Register IRQ Number. */
11793 ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost);
11794
11795 ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
11796 DRV_NAME, shost);
11797
11798 if (ret) {
11799 if (ret == -EBUSY) {
11800 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11801 "already in use\n", boardp->irq);
11802 } else if (ret == -EINVAL) {
11803 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11804 "not valid\n", boardp->irq);
11805 } else {
11806 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11807 "failed with %d\n", boardp->irq, ret);
11808 }
11809 goto err_free_dma;
11810 }
11811
11812 /*
11813 * Initialize board RISC chip and enable interrupts.
11814 */
11815 if (ASC_NARROW_BOARD(boardp)) {
11816 ASC_DBG(2, "AscInitAsc1000Driver()\n");
11817
11818 asc_dvc_varp->overrun_buf = kzalloc(ASC_OVERRUN_BSIZE, GFP_KERNEL);
11819 if (!asc_dvc_varp->overrun_buf) {
11820 ret = -ENOMEM;
11821 goto err_free_irq;
11822 }
11823 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
11824
11825 if (warn_code || asc_dvc_varp->err_code) {
11826 shost_printk(KERN_ERR, shost, "error: init_state 0x%x, "
11827 "warn 0x%x, error 0x%x\n",
11828 asc_dvc_varp->init_state, warn_code,
11829 asc_dvc_varp->err_code);
11830 if (!asc_dvc_varp->overrun_dma) {
11831 ret = -ENODEV;
11832 goto err_free_mem;
11833 }
11834 }
11835 } else {
11836 if (advansys_wide_init_chip(shost)) {
11837 ret = -ENODEV;
11838 goto err_free_mem;
11839 }
11840 }
11841
11842 ASC_DBG_PRT_SCSI_HOST(2, shost);
11843
11844 ret = scsi_add_host(shost, boardp->dev);
11845 if (ret)
11846 goto err_free_mem;
11847
11848 scsi_scan_host(shost);
11849 return 0;
11850
11851 err_free_mem:
11852 if (ASC_NARROW_BOARD(boardp)) {
11853 if (asc_dvc_varp->overrun_dma)
11854 dma_unmap_single(boardp->dev, asc_dvc_varp->overrun_dma,
11855 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11856 kfree(asc_dvc_varp->overrun_buf);
11857 } else
11858 advansys_wide_free_mem(boardp);
11859 err_free_irq:
11860 free_irq(boardp->irq, shost);
11861 err_free_dma:
11862 #ifdef CONFIG_ISA
11863 if (shost->dma_channel != NO_ISA_DMA)
11864 free_dma(shost->dma_channel);
11865 #endif
11866 err_unmap:
11867 if (boardp->ioremap_addr)
11868 iounmap(boardp->ioremap_addr);
11869 err_shost:
11870 return ret;
11871 }
11872
11873 /*
11874 * advansys_release()
11875 *
11876 * Release resources allocated for a single AdvanSys adapter.
11877 */
11878 static int advansys_release(struct Scsi_Host *shost)
11879 {
11880 struct asc_board *board = shost_priv(shost);
11881 ASC_DBG(1, "begin\n");
11882 scsi_remove_host(shost);
11883 free_irq(board->irq, shost);
11884 #ifdef CONFIG_ISA
11885 if (shost->dma_channel != NO_ISA_DMA) {
11886 ASC_DBG(1, "free_dma()\n");
11887 free_dma(shost->dma_channel);
11888 }
11889 #endif
11890 if (ASC_NARROW_BOARD(board)) {
11891 dma_unmap_single(board->dev,
11892 board->dvc_var.asc_dvc_var.overrun_dma,
11893 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11894 kfree(board->dvc_var.asc_dvc_var.overrun_buf);
11895 } else {
11896 iounmap(board->ioremap_addr);
11897 advansys_wide_free_mem(board);
11898 }
11899 scsi_host_put(shost);
11900 ASC_DBG(1, "end\n");
11901 return 0;
11902 }
11903
11904 #define ASC_IOADR_TABLE_MAX_IX 11
11905
11906 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = {
11907 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
11908 0x0210, 0x0230, 0x0250, 0x0330
11909 };
11910
11911 /*
11912 * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw. It decodes as:
11913 * 00: 10
11914 * 01: 11
11915 * 10: 12
11916 * 11: 15
11917 */
11918 static unsigned int advansys_isa_irq_no(PortAddr iop_base)
11919 {
11920 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11921 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
11922 if (chip_irq == 13)
11923 chip_irq = 15;
11924 return chip_irq;
11925 }
11926
11927 static int advansys_isa_probe(struct device *dev, unsigned int id)
11928 {
11929 int err = -ENODEV;
11930 PortAddr iop_base = _asc_def_iop_base[id];
11931 struct Scsi_Host *shost;
11932 struct asc_board *board;
11933
11934 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
11935 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
11936 return -ENODEV;
11937 }
11938 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
11939 if (!AscFindSignature(iop_base))
11940 goto release_region;
11941 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
11942 goto release_region;
11943
11944 err = -ENOMEM;
11945 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11946 if (!shost)
11947 goto release_region;
11948
11949 board = shost_priv(shost);
11950 board->irq = advansys_isa_irq_no(iop_base);
11951 board->dev = dev;
11952
11953 err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
11954 if (err)
11955 goto free_host;
11956
11957 dev_set_drvdata(dev, shost);
11958 return 0;
11959
11960 free_host:
11961 scsi_host_put(shost);
11962 release_region:
11963 release_region(iop_base, ASC_IOADR_GAP);
11964 return err;
11965 }
11966
11967 static int advansys_isa_remove(struct device *dev, unsigned int id)
11968 {
11969 int ioport = _asc_def_iop_base[id];
11970 advansys_release(dev_get_drvdata(dev));
11971 release_region(ioport, ASC_IOADR_GAP);
11972 return 0;
11973 }
11974
11975 static struct isa_driver advansys_isa_driver = {
11976 .probe = advansys_isa_probe,
11977 .remove = advansys_isa_remove,
11978 .driver = {
11979 .owner = THIS_MODULE,
11980 .name = DRV_NAME,
11981 },
11982 };
11983
11984 /*
11985 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as:
11986 * 000: invalid
11987 * 001: 10
11988 * 010: 11
11989 * 011: 12
11990 * 100: invalid
11991 * 101: 14
11992 * 110: 15
11993 * 111: invalid
11994 */
11995 static unsigned int advansys_vlb_irq_no(PortAddr iop_base)
11996 {
11997 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11998 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
11999 if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
12000 return 0;
12001 return chip_irq;
12002 }
12003
12004 static int advansys_vlb_probe(struct device *dev, unsigned int id)
12005 {
12006 int err = -ENODEV;
12007 PortAddr iop_base = _asc_def_iop_base[id];
12008 struct Scsi_Host *shost;
12009 struct asc_board *board;
12010
12011 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
12012 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
12013 return -ENODEV;
12014 }
12015 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
12016 if (!AscFindSignature(iop_base))
12017 goto release_region;
12018 /*
12019 * I don't think this condition can actually happen, but the old
12020 * driver did it, and the chances of finding a VLB setup in 2007
12021 * to do testing with is slight to none.
12022 */
12023 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
12024 goto release_region;
12025
12026 err = -ENOMEM;
12027 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
12028 if (!shost)
12029 goto release_region;
12030
12031 board = shost_priv(shost);
12032 board->irq = advansys_vlb_irq_no(iop_base);
12033 board->dev = dev;
12034
12035 err = advansys_board_found(shost, iop_base, ASC_IS_VL);
12036 if (err)
12037 goto free_host;
12038
12039 dev_set_drvdata(dev, shost);
12040 return 0;
12041
12042 free_host:
12043 scsi_host_put(shost);
12044 release_region:
12045 release_region(iop_base, ASC_IOADR_GAP);
12046 return -ENODEV;
12047 }
12048
12049 static struct isa_driver advansys_vlb_driver = {
12050 .probe = advansys_vlb_probe,
12051 .remove = advansys_isa_remove,
12052 .driver = {
12053 .owner = THIS_MODULE,
12054 .name = "advansys_vlb",
12055 },
12056 };
12057
12058 static struct eisa_device_id advansys_eisa_table[] = {
12059 { "ABP7401" },
12060 { "ABP7501" },
12061 { "" }
12062 };
12063
12064 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
12065
12066 /*
12067 * EISA is a little more tricky than PCI; each EISA device may have two
12068 * channels, and this driver is written to make each channel its own Scsi_Host
12069 */
12070 struct eisa_scsi_data {
12071 struct Scsi_Host *host[2];
12072 };
12073
12074 /*
12075 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as:
12076 * 000: 10
12077 * 001: 11
12078 * 010: 12
12079 * 011: invalid
12080 * 100: 14
12081 * 101: 15
12082 * 110: invalid
12083 * 111: invalid
12084 */
12085 static unsigned int advansys_eisa_irq_no(struct eisa_device *edev)
12086 {
12087 unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
12088 unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
12089 if ((chip_irq == 13) || (chip_irq > 15))
12090 return 0;
12091 return chip_irq;
12092 }
12093
12094 static int advansys_eisa_probe(struct device *dev)
12095 {
12096 int i, ioport, irq = 0;
12097 int err;
12098 struct eisa_device *edev = to_eisa_device(dev);
12099 struct eisa_scsi_data *data;
12100
12101 err = -ENOMEM;
12102 data = kzalloc(sizeof(*data), GFP_KERNEL);
12103 if (!data)
12104 goto fail;
12105 ioport = edev->base_addr + 0xc30;
12106
12107 err = -ENODEV;
12108 for (i = 0; i < 2; i++, ioport += 0x20) {
12109 struct asc_board *board;
12110 struct Scsi_Host *shost;
12111 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
12112 printk(KERN_WARNING "Region %x-%x busy\n", ioport,
12113 ioport + ASC_IOADR_GAP - 1);
12114 continue;
12115 }
12116 if (!AscFindSignature(ioport)) {
12117 release_region(ioport, ASC_IOADR_GAP);
12118 continue;
12119 }
12120
12121 /*
12122 * I don't know why we need to do this for EISA chips, but
12123 * not for any others. It looks to be equivalent to
12124 * AscGetChipCfgMsw, but I may have overlooked something,
12125 * so I'm not converting it until I get an EISA board to
12126 * test with.
12127 */
12128 inw(ioport + 4);
12129
12130 if (!irq)
12131 irq = advansys_eisa_irq_no(edev);
12132
12133 err = -ENOMEM;
12134 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
12135 if (!shost)
12136 goto release_region;
12137
12138 board = shost_priv(shost);
12139 board->irq = irq;
12140 board->dev = dev;
12141
12142 err = advansys_board_found(shost, ioport, ASC_IS_EISA);
12143 if (!err) {
12144 data->host[i] = shost;
12145 continue;
12146 }
12147
12148 scsi_host_put(shost);
12149 release_region:
12150 release_region(ioport, ASC_IOADR_GAP);
12151 break;
12152 }
12153
12154 if (err)
12155 goto free_data;
12156 dev_set_drvdata(dev, data);
12157 return 0;
12158
12159 free_data:
12160 kfree(data->host[0]);
12161 kfree(data->host[1]);
12162 kfree(data);
12163 fail:
12164 return err;
12165 }
12166
12167 static int advansys_eisa_remove(struct device *dev)
12168 {
12169 int i;
12170 struct eisa_scsi_data *data = dev_get_drvdata(dev);
12171
12172 for (i = 0; i < 2; i++) {
12173 int ioport;
12174 struct Scsi_Host *shost = data->host[i];
12175 if (!shost)
12176 continue;
12177 ioport = shost->io_port;
12178 advansys_release(shost);
12179 release_region(ioport, ASC_IOADR_GAP);
12180 }
12181
12182 kfree(data);
12183 return 0;
12184 }
12185
12186 static struct eisa_driver advansys_eisa_driver = {
12187 .id_table = advansys_eisa_table,
12188 .driver = {
12189 .name = DRV_NAME,
12190 .probe = advansys_eisa_probe,
12191 .remove = advansys_eisa_remove,
12192 }
12193 };
12194
12195 /* PCI Devices supported by this driver */
12196 static struct pci_device_id advansys_pci_tbl[] = {
12197 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
12198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12199 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
12200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12201 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
12202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12203 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
12204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12205 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
12206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12207 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
12208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12209 {}
12210 };
12211
12212 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
12213
12214 static void advansys_set_latency(struct pci_dev *pdev)
12215 {
12216 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
12217 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
12218 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
12219 } else {
12220 u8 latency;
12221 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
12222 if (latency < 0x20)
12223 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
12224 }
12225 }
12226
12227 static int advansys_pci_probe(struct pci_dev *pdev,
12228 const struct pci_device_id *ent)
12229 {
12230 int err, ioport;
12231 struct Scsi_Host *shost;
12232 struct asc_board *board;
12233
12234 err = pci_enable_device(pdev);
12235 if (err)
12236 goto fail;
12237 err = pci_request_regions(pdev, DRV_NAME);
12238 if (err)
12239 goto disable_device;
12240 pci_set_master(pdev);
12241 advansys_set_latency(pdev);
12242
12243 err = -ENODEV;
12244 if (pci_resource_len(pdev, 0) == 0)
12245 goto release_region;
12246
12247 ioport = pci_resource_start(pdev, 0);
12248
12249 err = -ENOMEM;
12250 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
12251 if (!shost)
12252 goto release_region;
12253
12254 board = shost_priv(shost);
12255 board->irq = pdev->irq;
12256 board->dev = &pdev->dev;
12257
12258 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
12259 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
12260 pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
12261 board->flags |= ASC_IS_WIDE_BOARD;
12262 }
12263
12264 err = advansys_board_found(shost, ioport, ASC_IS_PCI);
12265 if (err)
12266 goto free_host;
12267
12268 pci_set_drvdata(pdev, shost);
12269 return 0;
12270
12271 free_host:
12272 scsi_host_put(shost);
12273 release_region:
12274 pci_release_regions(pdev);
12275 disable_device:
12276 pci_disable_device(pdev);
12277 fail:
12278 return err;
12279 }
12280
12281 static void advansys_pci_remove(struct pci_dev *pdev)
12282 {
12283 advansys_release(pci_get_drvdata(pdev));
12284 pci_release_regions(pdev);
12285 pci_disable_device(pdev);
12286 }
12287
12288 static struct pci_driver advansys_pci_driver = {
12289 .name = DRV_NAME,
12290 .id_table = advansys_pci_tbl,
12291 .probe = advansys_pci_probe,
12292 .remove = advansys_pci_remove,
12293 };
12294
12295 static int __init advansys_init(void)
12296 {
12297 int error;
12298
12299 error = isa_register_driver(&advansys_isa_driver,
12300 ASC_IOADR_TABLE_MAX_IX);
12301 if (error)
12302 goto fail;
12303
12304 error = isa_register_driver(&advansys_vlb_driver,
12305 ASC_IOADR_TABLE_MAX_IX);
12306 if (error)
12307 goto unregister_isa;
12308
12309 error = eisa_driver_register(&advansys_eisa_driver);
12310 if (error)
12311 goto unregister_vlb;
12312
12313 error = pci_register_driver(&advansys_pci_driver);
12314 if (error)
12315 goto unregister_eisa;
12316
12317 return 0;
12318
12319 unregister_eisa:
12320 eisa_driver_unregister(&advansys_eisa_driver);
12321 unregister_vlb:
12322 isa_unregister_driver(&advansys_vlb_driver);
12323 unregister_isa:
12324 isa_unregister_driver(&advansys_isa_driver);
12325 fail:
12326 return error;
12327 }
12328
12329 static void __exit advansys_exit(void)
12330 {
12331 pci_unregister_driver(&advansys_pci_driver);
12332 eisa_driver_unregister(&advansys_eisa_driver);
12333 isa_unregister_driver(&advansys_vlb_driver);
12334 isa_unregister_driver(&advansys_isa_driver);
12335 }
12336
12337 module_init(advansys_init);
12338 module_exit(advansys_exit);
12339
12340 MODULE_LICENSE("GPL");
12341 MODULE_FIRMWARE("advansys/mcode.bin");
12342 MODULE_FIRMWARE("advansys/3550.bin");
12343 MODULE_FIRMWARE("advansys/38C0800.bin");
12344 MODULE_FIRMWARE("advansys/38C1600.bin");
Linux with added FPC-III support