arch/arm64/kernel/cpu_errata.c

   1 /*
   2  * Contains CPU specific errata definitions
   3  *
   4  * Copyright (C) 2014 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/types.h>
  20 #include <asm/cpu.h>
  21 #include <asm/cputype.h>
  22 #include <asm/cpufeature.h>
  23
  24 static bool __maybe_unused
  25 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
  26 {
  27         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
  28         return MIDR_IS_CPU_MODEL_RANGE(read_cpuid_id(), entry->midr_model,
  29                                        entry->midr_range_min,
  30                                        entry->midr_range_max);
  31 }
  32
  33 static bool __maybe_unused
  34 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
  35 {
  36         u32 model;
  37
  38         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
  39
  40         model = read_cpuid_id();
  41         model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
  42                  MIDR_ARCHITECTURE_MASK;
  43
  44         return model == entry->midr_model;
  45 }
  46
  47 static bool
  48 has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry,
  49                                 int scope)
  50 {
  51         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
  52         return (read_cpuid_cachetype() & arm64_ftr_reg_ctrel0.strict_mask) !=
  53                 (arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask);
  54 }
  55
  56 static int cpu_enable_trap_ctr_access(void *__unused)
  57 {
  58         /* Clear SCTLR_EL1.UCT */
  59         config_sctlr_el1(SCTLR_EL1_UCT, 0);
  60         return 0;
  61 }
  62
  63 atomic_t arm64_el2_vector_last_slot = ATOMIC_INIT(-1);
  64
  65 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
  66 #include <asm/mmu_context.h>
  67 #include <asm/cacheflush.h>
  68
  69 DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
  70
  71 #ifdef CONFIG_KVM
  72 extern char __smccc_workaround_1_smc_start[];
  73 extern char __smccc_workaround_1_smc_end[];
  74 extern char __smccc_workaround_1_hvc_start[];
  75 extern char __smccc_workaround_1_hvc_end[];
  76
  77 static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
  78                                 const char *hyp_vecs_end)
  79 {
  80         void *dst = lm_alias(__bp_harden_hyp_vecs_start + slot * SZ_2K);
  81         int i;
  82
  83         for (i = 0; i < SZ_2K; i += 0x80)
  84                 memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start);
  85
  86         flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K);
  87 }
  88
  89 static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
  90                                       const char *hyp_vecs_start,
  91                                       const char *hyp_vecs_end)
  92 {
  93         static DEFINE_SPINLOCK(bp_lock);
  94         int cpu, slot = -1;
  95
  96         spin_lock(&bp_lock);
  97         for_each_possible_cpu(cpu) {
  98                 if (per_cpu(bp_hardening_data.fn, cpu) == fn) {
  99                         slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu);
 100                         break;
 101                 }
 102         }
 103
 104         if (slot == -1) {
 105                 slot = atomic_inc_return(&arm64_el2_vector_last_slot);
 106                 BUG_ON(slot >= BP_HARDEN_EL2_SLOTS);
 107                 __copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end);
 108         }
 109
 110         __this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
 111         __this_cpu_write(bp_hardening_data.fn, fn);
 112         spin_unlock(&bp_lock);
 113 }
 114 #else
 115 #define __smccc_workaround_1_smc_start          NULL
 116 #define __smccc_workaround_1_smc_end            NULL
 117 #define __smccc_workaround_1_hvc_start          NULL
 118 #define __smccc_workaround_1_hvc_end            NULL
 119
 120 static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
 121                                       const char *hyp_vecs_start,
 122                                       const char *hyp_vecs_end)
 123 {
 124         __this_cpu_write(bp_hardening_data.fn, fn);
 125 }
 126 #endif  /* CONFIG_KVM */
 127
 128 static void  install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry,
 129                                      bp_hardening_cb_t fn,
 130                                      const char *hyp_vecs_start,
 131                                      const char *hyp_vecs_end)
 132 {
 133         u64 pfr0;
 134
 135         if (!entry->matches(entry, SCOPE_LOCAL_CPU))
 136                 return;
 137
 138         pfr0 = read_cpuid(ID_AA64PFR0_EL1);
 139         if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT))
 140                 return;
 141
 142         __install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end);
 143 }
 144
 145 #include <uapi/linux/psci.h>
 146 #include <linux/arm-smccc.h>
 147 #include <linux/psci.h>
 148
 149 static void call_smc_arch_workaround_1(void)
 150 {
 151         arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
 152 }
 153
 154 static void call_hvc_arch_workaround_1(void)
 155 {
 156         arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
 157 }
 158
 159 static void qcom_link_stack_sanitization(void)
 160 {
 161         u64 tmp;
 162
 163         asm volatile("mov       %0, x30         \n"
 164                      ".rept     16              \n"
 165                      "bl        . + 4           \n"
 166                      ".endr                     \n"
 167                      "mov       x30, %0         \n"
 168                      : "=&r" (tmp));
 169 }
 170
 171 static int enable_smccc_arch_workaround_1(void *data)
 172 {
 173         const struct arm64_cpu_capabilities *entry = data;
 174         bp_hardening_cb_t cb;
 175         void *smccc_start, *smccc_end;
 176         struct arm_smccc_res res;
 177         u32 midr = read_cpuid_id();
 178
 179         if (!entry->matches(entry, SCOPE_LOCAL_CPU))
 180                 return 0;
 181
 182         if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
 183                 return 0;
 184
 185         switch (psci_ops.conduit) {
 186         case PSCI_CONDUIT_HVC:
 187                 arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
 188                                   ARM_SMCCC_ARCH_WORKAROUND_1, &res);
 189                 if (res.a0)
 190                         return 0;
 191                 cb = call_hvc_arch_workaround_1;
 192                 smccc_start = __smccc_workaround_1_hvc_start;
 193                 smccc_end = __smccc_workaround_1_hvc_end;
 194                 break;
 195
 196         case PSCI_CONDUIT_SMC:
 197                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
 198                                   ARM_SMCCC_ARCH_WORKAROUND_1, &res);
 199                 if (res.a0)
 200                         return 0;
 201                 cb = call_smc_arch_workaround_1;
 202                 smccc_start = __smccc_workaround_1_smc_start;
 203                 smccc_end = __smccc_workaround_1_smc_end;
 204                 break;
 205
 206         default:
 207                 return 0;
 208         }
 209
 210         if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) ||
 211             ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1))
 212                 cb = qcom_link_stack_sanitization;
 213
 214         install_bp_hardening_cb(entry, cb, smccc_start, smccc_end);
 215
 216         return 0;
 217 }
 218
 219 #endif  /* CONFIG_HARDEN_BRANCH_PREDICTOR */
 220
 221 #define MIDR_RANGE(model, min, max) \
 222         .def_scope = SCOPE_LOCAL_CPU, \
 223         .matches = is_affected_midr_range, \
 224         .midr_model = model, \
 225         .midr_range_min = min, \
 226         .midr_range_max = max
 227
 228 #define MIDR_ALL_VERSIONS(model) \
 229         .def_scope = SCOPE_LOCAL_CPU, \
 230         .matches = is_affected_midr_range, \
 231         .midr_model = model, \
 232         .midr_range_min = 0, \
 233         .midr_range_max = (MIDR_VARIANT_MASK | MIDR_REVISION_MASK)
 234
 235 const struct arm64_cpu_capabilities arm64_errata[] = {
 236 #if     defined(CONFIG_ARM64_ERRATUM_826319) || \
 237         defined(CONFIG_ARM64_ERRATUM_827319) || \
 238         defined(CONFIG_ARM64_ERRATUM_824069)
 239         {
 240         /* Cortex-A53 r0p[012] */
 241                 .desc = "ARM errata 826319, 827319, 824069",
 242                 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
 243                 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02),
 244                 .enable = cpu_enable_cache_maint_trap,
 245         },
 246 #endif
 247 #ifdef CONFIG_ARM64_ERRATUM_819472
 248         {
 249         /* Cortex-A53 r0p[01] */
 250                 .desc = "ARM errata 819472",
 251                 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
 252                 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01),
 253                 .enable = cpu_enable_cache_maint_trap,
 254         },
 255 #endif
 256 #ifdef CONFIG_ARM64_ERRATUM_832075
 257         {
 258         /* Cortex-A57 r0p0 - r1p2 */
 259                 .desc = "ARM erratum 832075",
 260                 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
 261                 MIDR_RANGE(MIDR_CORTEX_A57,
 262                            MIDR_CPU_VAR_REV(0, 0),
 263                            MIDR_CPU_VAR_REV(1, 2)),
 264         },
 265 #endif
 266 #ifdef CONFIG_ARM64_ERRATUM_834220
 267         {
 268         /* Cortex-A57 r0p0 - r1p2 */
 269                 .desc = "ARM erratum 834220",
 270                 .capability = ARM64_WORKAROUND_834220,
 271                 MIDR_RANGE(MIDR_CORTEX_A57,
 272                            MIDR_CPU_VAR_REV(0, 0),
 273                            MIDR_CPU_VAR_REV(1, 2)),
 274         },
 275 #endif
 276 #ifdef CONFIG_ARM64_ERRATUM_845719
 277         {
 278         /* Cortex-A53 r0p[01234] */
 279                 .desc = "ARM erratum 845719",
 280                 .capability = ARM64_WORKAROUND_845719,
 281                 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
 282         },
 283 #endif
 284 #ifdef CONFIG_CAVIUM_ERRATUM_23154
 285         {
 286         /* Cavium ThunderX, pass 1.x */
 287                 .desc = "Cavium erratum 23154",
 288                 .capability = ARM64_WORKAROUND_CAVIUM_23154,
 289                 MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),
 290         },
 291 #endif
 292 #ifdef CONFIG_CAVIUM_ERRATUM_27456
 293         {
 294         /* Cavium ThunderX, T88 pass 1.x - 2.1 */
 295                 .desc = "Cavium erratum 27456",
 296                 .capability = ARM64_WORKAROUND_CAVIUM_27456,
 297                 MIDR_RANGE(MIDR_THUNDERX,
 298                            MIDR_CPU_VAR_REV(0, 0),
 299                            MIDR_CPU_VAR_REV(1, 1)),
 300         },
 301         {
 302         /* Cavium ThunderX, T81 pass 1.0 */
 303                 .desc = "Cavium erratum 27456",
 304                 .capability = ARM64_WORKAROUND_CAVIUM_27456,
 305                 MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00),
 306         },
 307 #endif
 308 #ifdef CONFIG_CAVIUM_ERRATUM_30115
 309         {
 310         /* Cavium ThunderX, T88 pass 1.x - 2.2 */
 311                 .desc = "Cavium erratum 30115",
 312                 .capability = ARM64_WORKAROUND_CAVIUM_30115,
 313                 MIDR_RANGE(MIDR_THUNDERX, 0x00,
 314                            (1 << MIDR_VARIANT_SHIFT) | 2),
 315         },
 316         {
 317         /* Cavium ThunderX, T81 pass 1.0 - 1.2 */
 318                 .desc = "Cavium erratum 30115",
 319                 .capability = ARM64_WORKAROUND_CAVIUM_30115,
 320                 MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x02),
 321         },
 322         {
 323         /* Cavium ThunderX, T83 pass 1.0 */
 324                 .desc = "Cavium erratum 30115",
 325                 .capability = ARM64_WORKAROUND_CAVIUM_30115,
 326                 MIDR_RANGE(MIDR_THUNDERX_83XX, 0x00, 0x00),
 327         },
 328 #endif
 329         {
 330                 .desc = "Mismatched cache line size",
 331                 .capability = ARM64_MISMATCHED_CACHE_LINE_SIZE,
 332                 .matches = has_mismatched_cache_line_size,
 333                 .def_scope = SCOPE_LOCAL_CPU,
 334                 .enable = cpu_enable_trap_ctr_access,
 335         },
 336 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
 337         {
 338                 .desc = "Qualcomm Technologies Falkor erratum 1003",
 339                 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
 340                 MIDR_RANGE(MIDR_QCOM_FALKOR_V1,
 341                            MIDR_CPU_VAR_REV(0, 0),
 342                            MIDR_CPU_VAR_REV(0, 0)),
 343         },
 344         {
 345                 .desc = "Qualcomm Technologies Kryo erratum 1003",
 346                 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
 347                 .def_scope = SCOPE_LOCAL_CPU,
 348                 .midr_model = MIDR_QCOM_KRYO,
 349                 .matches = is_kryo_midr,
 350         },
 351 #endif
 352 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
 353         {
 354                 .desc = "Qualcomm Technologies Falkor erratum 1009",
 355                 .capability = ARM64_WORKAROUND_REPEAT_TLBI,
 356                 MIDR_RANGE(MIDR_QCOM_FALKOR_V1,
 357                            MIDR_CPU_VAR_REV(0, 0),
 358                            MIDR_CPU_VAR_REV(0, 0)),
 359         },
 360 #endif
 361 #ifdef CONFIG_ARM64_ERRATUM_858921
 362         {
 363         /* Cortex-A73 all versions */
 364                 .desc = "ARM erratum 858921",
 365                 .capability = ARM64_WORKAROUND_858921,
 366                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
 367         },
 368 #endif
 369 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
 370         {
 371                 .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
 372                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 373                 .enable = enable_smccc_arch_workaround_1,
 374         },
 375         {
 376                 .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
 377                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 378                 .enable = enable_smccc_arch_workaround_1,
 379         },
 380         {
 381                 .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
 382                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
 383                 .enable = enable_smccc_arch_workaround_1,
 384         },
 385         {
 386                 .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
 387                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
 388                 .enable = enable_smccc_arch_workaround_1,
 389         },
 390         {
 391                 .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
 392                 MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
 393                 .enable = enable_smccc_arch_workaround_1,
 394         },
 395         {
 396                 .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
 397                 MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
 398                 .enable = enable_smccc_arch_workaround_1,
 399         },
 400         {
 401                 .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
 402                 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
 403                 .enable = enable_smccc_arch_workaround_1,
 404         },
 405         {
 406                 .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
 407                 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
 408                 .enable = enable_smccc_arch_workaround_1,
 409         },
 410 #endif
 411 #ifdef CONFIG_HARDEN_EL2_VECTORS
 412         {
 413                 .desc = "Cortex-A57 EL2 vector hardening",
 414                 .capability = ARM64_HARDEN_EL2_VECTORS,
 415                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 416         },
 417         {
 418                 .desc = "Cortex-A72 EL2 vector hardening",
 419                 .capability = ARM64_HARDEN_EL2_VECTORS,
 420                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 421         },
 422 #endif
 423         {
 424         }
 425 };
 426
 427 /*
 428  * The CPU Errata work arounds are detected and applied at boot time
 429  * and the related information is freed soon after. If the new CPU requires
 430  * an errata not detected at boot, fail this CPU.
 431  */
 432 void verify_local_cpu_errata_workarounds(void)
 433 {
 434         const struct arm64_cpu_capabilities *caps = arm64_errata;
 435
 436         for (; caps->matches; caps++) {
 437                 if (cpus_have_cap(caps->capability)) {
 438                         if (caps->enable)
 439                                 caps->enable((void *)caps);
 440                 } else if (caps->matches(caps, SCOPE_LOCAL_CPU)) {
 441                         pr_crit("CPU%d: Requires work around for %s, not detected"
 442                                         " at boot time\n",
 443                                 smp_processor_id(),
 444                                 caps->desc ? : "an erratum");
 445                         cpu_die_early();
 446                 }
 447         }
 448 }
 449
 450 void update_cpu_errata_workarounds(void)
 451 {
 452         update_cpu_capabilities(arm64_errata, "enabling workaround for");
 453 }
 454
 455 void __init enable_errata_workarounds(void)
 456 {
 457         enable_cpu_capabilities(arm64_errata);
 458 }