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Merge tag 'nios2-v4.19-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/lftan...
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-omap.c
blob65d06a8193074814cb18a0864eaea9cbc3c044de
1 /*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
7 *
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 */
26
27 #include <linux/module.h>
28 #include <linux/delay.h>
29 #include <linux/i2c.h>
30 #include <linux/err.h>
31 #include <linux/interrupt.h>
32 #include <linux/completion.h>
33 #include <linux/platform_device.h>
34 #include <linux/clk.h>
35 #include <linux/io.h>
36 #include <linux/of.h>
37 #include <linux/of_device.h>
38 #include <linux/slab.h>
39 #include <linux/platform_data/i2c-omap.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/pinctrl/consumer.h>
42
43 /* I2C controller revisions */
44 #define OMAP_I2C_OMAP1_REV_2 0x20
45
46 /* I2C controller revisions present on specific hardware */
47 #define OMAP_I2C_REV_ON_2430 0x00000036
48 #define OMAP_I2C_REV_ON_3430_3530 0x0000003C
49 #define OMAP_I2C_REV_ON_3630 0x00000040
50 #define OMAP_I2C_REV_ON_4430_PLUS 0x50400002
51
52 /* timeout waiting for the controller to respond */
53 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
54
55 /* timeout for pm runtime autosuspend */
56 #define OMAP_I2C_PM_TIMEOUT 1000 /* ms */
57
58 /* timeout for making decision on bus free status */
59 #define OMAP_I2C_BUS_FREE_TIMEOUT (msecs_to_jiffies(10))
60
61 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
62 enum {
63 OMAP_I2C_REV_REG = 0,
64 OMAP_I2C_IE_REG,
65 OMAP_I2C_STAT_REG,
66 OMAP_I2C_IV_REG,
67 OMAP_I2C_WE_REG,
68 OMAP_I2C_SYSS_REG,
69 OMAP_I2C_BUF_REG,
70 OMAP_I2C_CNT_REG,
71 OMAP_I2C_DATA_REG,
72 OMAP_I2C_SYSC_REG,
73 OMAP_I2C_CON_REG,
74 OMAP_I2C_OA_REG,
75 OMAP_I2C_SA_REG,
76 OMAP_I2C_PSC_REG,
77 OMAP_I2C_SCLL_REG,
78 OMAP_I2C_SCLH_REG,
79 OMAP_I2C_SYSTEST_REG,
80 OMAP_I2C_BUFSTAT_REG,
81 /* only on OMAP4430 */
82 OMAP_I2C_IP_V2_REVNB_LO,
83 OMAP_I2C_IP_V2_REVNB_HI,
84 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
85 OMAP_I2C_IP_V2_IRQENABLE_SET,
86 OMAP_I2C_IP_V2_IRQENABLE_CLR,
87 };
88
89 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
90 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
91 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
92 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
93 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
94 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
95 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
96 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
97
98 /* I2C Status Register (OMAP_I2C_STAT): */
99 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
100 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
101 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
102 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
103 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
104 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
105 #define OMAP_I2C_STAT_BF (1 << 8) /* Bus Free */
106 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
107 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
108 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
109 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
110 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
111
112 /* I2C WE wakeup enable register */
113 #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
114 #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
115 #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
116 #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
117 #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
118 #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
119 #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
120 #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
121 #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
122 #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
123
124 #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
125 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
126 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
127 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
128 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
129
130 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
131 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
132 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
133 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
134 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
135
136 /* I2C Configuration Register (OMAP_I2C_CON): */
137 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
138 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
139 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
140 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
141 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
142 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
143 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
144 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
145 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
146 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
147
148 /* I2C SCL time value when Master */
149 #define OMAP_I2C_SCLL_HSSCLL 8
150 #define OMAP_I2C_SCLH_HSSCLH 8
151
152 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
153 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
154 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
155 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
156 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
157 /* Functional mode */
158 #define OMAP_I2C_SYSTEST_SCL_I_FUNC (1 << 8) /* SCL line input value */
159 #define OMAP_I2C_SYSTEST_SCL_O_FUNC (1 << 7) /* SCL line output value */
160 #define OMAP_I2C_SYSTEST_SDA_I_FUNC (1 << 6) /* SDA line input value */
161 #define OMAP_I2C_SYSTEST_SDA_O_FUNC (1 << 5) /* SDA line output value */
162 /* SDA/SCL IO mode */
163 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
164 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
165 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
166 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
167
168 /* OCP_SYSSTATUS bit definitions */
169 #define SYSS_RESETDONE_MASK (1 << 0)
170
171 /* OCP_SYSCONFIG bit definitions */
172 #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
173 #define SYSC_SIDLEMODE_MASK (0x3 << 3)
174 #define SYSC_ENAWAKEUP_MASK (1 << 2)
175 #define SYSC_SOFTRESET_MASK (1 << 1)
176 #define SYSC_AUTOIDLE_MASK (1 << 0)
177
178 #define SYSC_IDLEMODE_SMART 0x2
179 #define SYSC_CLOCKACTIVITY_FCLK 0x2
180
181 /* Errata definitions */
182 #define I2C_OMAP_ERRATA_I207 (1 << 0)
183 #define I2C_OMAP_ERRATA_I462 (1 << 1)
184
185 #define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF
186
187 struct omap_i2c_dev {
188 struct device *dev;
189 void __iomem *base; /* virtual */
190 int irq;
191 int reg_shift; /* bit shift for I2C register addresses */
192 struct completion cmd_complete;
193 struct resource *ioarea;
194 u32 latency; /* maximum mpu wkup latency */
195 void (*set_mpu_wkup_lat)(struct device *dev,
196 long latency);
197 u32 speed; /* Speed of bus in kHz */
198 u32 flags;
199 u16 scheme;
200 u16 cmd_err;
201 u8 *buf;
202 u8 *regs;
203 size_t buf_len;
204 struct i2c_adapter adapter;
205 u8 threshold;
206 u8 fifo_size; /* use as flag and value
207 * fifo_size==0 implies no fifo
208 * if set, should be trsh+1
209 */
210 u32 rev;
211 unsigned b_hw:1; /* bad h/w fixes */
212 unsigned bb_valid:1; /* true when BB-bit reflects
213 * the I2C bus state
214 */
215 unsigned receiver:1; /* true when we're in receiver mode */
216 u16 iestate; /* Saved interrupt register */
217 u16 pscstate;
218 u16 scllstate;
219 u16 sclhstate;
220 u16 syscstate;
221 u16 westate;
222 u16 errata;
223 };
224
225 static const u8 reg_map_ip_v1[] = {
226 [OMAP_I2C_REV_REG] = 0x00,
227 [OMAP_I2C_IE_REG] = 0x01,
228 [OMAP_I2C_STAT_REG] = 0x02,
229 [OMAP_I2C_IV_REG] = 0x03,
230 [OMAP_I2C_WE_REG] = 0x03,
231 [OMAP_I2C_SYSS_REG] = 0x04,
232 [OMAP_I2C_BUF_REG] = 0x05,
233 [OMAP_I2C_CNT_REG] = 0x06,
234 [OMAP_I2C_DATA_REG] = 0x07,
235 [OMAP_I2C_SYSC_REG] = 0x08,
236 [OMAP_I2C_CON_REG] = 0x09,
237 [OMAP_I2C_OA_REG] = 0x0a,
238 [OMAP_I2C_SA_REG] = 0x0b,
239 [OMAP_I2C_PSC_REG] = 0x0c,
240 [OMAP_I2C_SCLL_REG] = 0x0d,
241 [OMAP_I2C_SCLH_REG] = 0x0e,
242 [OMAP_I2C_SYSTEST_REG] = 0x0f,
243 [OMAP_I2C_BUFSTAT_REG] = 0x10,
244 };
245
246 static const u8 reg_map_ip_v2[] = {
247 [OMAP_I2C_REV_REG] = 0x04,
248 [OMAP_I2C_IE_REG] = 0x2c,
249 [OMAP_I2C_STAT_REG] = 0x28,
250 [OMAP_I2C_IV_REG] = 0x34,
251 [OMAP_I2C_WE_REG] = 0x34,
252 [OMAP_I2C_SYSS_REG] = 0x90,
253 [OMAP_I2C_BUF_REG] = 0x94,
254 [OMAP_I2C_CNT_REG] = 0x98,
255 [OMAP_I2C_DATA_REG] = 0x9c,
256 [OMAP_I2C_SYSC_REG] = 0x10,
257 [OMAP_I2C_CON_REG] = 0xa4,
258 [OMAP_I2C_OA_REG] = 0xa8,
259 [OMAP_I2C_SA_REG] = 0xac,
260 [OMAP_I2C_PSC_REG] = 0xb0,
261 [OMAP_I2C_SCLL_REG] = 0xb4,
262 [OMAP_I2C_SCLH_REG] = 0xb8,
263 [OMAP_I2C_SYSTEST_REG] = 0xbC,
264 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
265 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
266 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
267 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
268 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
269 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
270 };
271
272 static inline void omap_i2c_write_reg(struct omap_i2c_dev *omap,
273 int reg, u16 val)
274 {
275 writew_relaxed(val, omap->base +
276 (omap->regs[reg] << omap->reg_shift));
277 }
278
279 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *omap, int reg)
280 {
281 return readw_relaxed(omap->base +
282 (omap->regs[reg] << omap->reg_shift));
283 }
284
285 static void __omap_i2c_init(struct omap_i2c_dev *omap)
286 {
287
288 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
289
290 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
291 omap_i2c_write_reg(omap, OMAP_I2C_PSC_REG, omap->pscstate);
292
293 /* SCL low and high time values */
294 omap_i2c_write_reg(omap, OMAP_I2C_SCLL_REG, omap->scllstate);
295 omap_i2c_write_reg(omap, OMAP_I2C_SCLH_REG, omap->sclhstate);
296 if (omap->rev >= OMAP_I2C_REV_ON_3430_3530)
297 omap_i2c_write_reg(omap, OMAP_I2C_WE_REG, omap->westate);
298
299 /* Take the I2C module out of reset: */
300 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
301
302 /*
303 * NOTE: right after setting CON_EN, STAT_BB could be 0 while the
304 * bus is busy. It will be changed to 1 on the next IP FCLK clock.
305 * udelay(1) will be enough to fix that.
306 */
307
308 /*
309 * Don't write to this register if the IE state is 0 as it can
310 * cause deadlock.
311 */
312 if (omap->iestate)
313 omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, omap->iestate);
314 }
315
316 static int omap_i2c_reset(struct omap_i2c_dev *omap)
317 {
318 unsigned long timeout;
319 u16 sysc;
320
321 if (omap->rev >= OMAP_I2C_OMAP1_REV_2) {
322 sysc = omap_i2c_read_reg(omap, OMAP_I2C_SYSC_REG);
323
324 /* Disable I2C controller before soft reset */
325 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG,
326 omap_i2c_read_reg(omap, OMAP_I2C_CON_REG) &
327 ~(OMAP_I2C_CON_EN));
328
329 omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
330 /* For some reason we need to set the EN bit before the
331 * reset done bit gets set. */
332 timeout = jiffies + OMAP_I2C_TIMEOUT;
333 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
334 while (!(omap_i2c_read_reg(omap, OMAP_I2C_SYSS_REG) &
335 SYSS_RESETDONE_MASK)) {
336 if (time_after(jiffies, timeout)) {
337 dev_warn(omap->dev, "timeout waiting "
338 "for controller reset\n");
339 return -ETIMEDOUT;
340 }
341 msleep(1);
342 }
343
344 /* SYSC register is cleared by the reset; rewrite it */
345 omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, sysc);
346
347 if (omap->rev > OMAP_I2C_REV_ON_3430_3530) {
348 /* Schedule I2C-bus monitoring on the next transfer */
349 omap->bb_valid = 0;
350 }
351 }
352
353 return 0;
354 }
355
356 static int omap_i2c_init(struct omap_i2c_dev *omap)
357 {
358 u16 psc = 0, scll = 0, sclh = 0;
359 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
360 unsigned long fclk_rate = 12000000;
361 unsigned long internal_clk = 0;
362 struct clk *fclk;
363 int error;
364
365 if (omap->rev >= OMAP_I2C_REV_ON_3430_3530) {
366 /*
367 * Enabling all wakup sources to stop I2C freezing on
368 * WFI instruction.
369 * REVISIT: Some wkup sources might not be needed.
370 */
371 omap->westate = OMAP_I2C_WE_ALL;
372 }
373
374 if (omap->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
375 /*
376 * The I2C functional clock is the armxor_ck, so there's
377 * no need to get "armxor_ck" separately. Now, if OMAP2420
378 * always returns 12MHz for the functional clock, we can
379 * do this bit unconditionally.
380 */
381 fclk = clk_get(omap->dev, "fck");
382 if (IS_ERR(fclk)) {
383 error = PTR_ERR(fclk);
384 dev_err(omap->dev, "could not get fck: %i\n", error);
385
386 return error;
387 }
388
389 fclk_rate = clk_get_rate(fclk);
390 clk_put(fclk);
391
392 /* TRM for 5912 says the I2C clock must be prescaled to be
393 * between 7 - 12 MHz. The XOR input clock is typically
394 * 12, 13 or 19.2 MHz. So we should have code that produces:
395 *
396 * XOR MHz Divider Prescaler
397 * 12 1 0
398 * 13 2 1
399 * 19.2 2 1
400 */
401 if (fclk_rate > 12000000)
402 psc = fclk_rate / 12000000;
403 }
404
405 if (!(omap->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
406
407 /*
408 * HSI2C controller internal clk rate should be 19.2 Mhz for
409 * HS and for all modes on 2430. On 34xx we can use lower rate
410 * to get longer filter period for better noise suppression.
411 * The filter is iclk (fclk for HS) period.
412 */
413 if (omap->speed > 400 ||
414 omap->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
415 internal_clk = 19200;
416 else if (omap->speed > 100)
417 internal_clk = 9600;
418 else
419 internal_clk = 4000;
420 fclk = clk_get(omap->dev, "fck");
421 if (IS_ERR(fclk)) {
422 error = PTR_ERR(fclk);
423 dev_err(omap->dev, "could not get fck: %i\n", error);
424
425 return error;
426 }
427 fclk_rate = clk_get_rate(fclk) / 1000;
428 clk_put(fclk);
429
430 /* Compute prescaler divisor */
431 psc = fclk_rate / internal_clk;
432 psc = psc - 1;
433
434 /* If configured for High Speed */
435 if (omap->speed > 400) {
436 unsigned long scl;
437
438 /* For first phase of HS mode */
439 scl = internal_clk / 400;
440 fsscll = scl - (scl / 3) - 7;
441 fssclh = (scl / 3) - 5;
442
443 /* For second phase of HS mode */
444 scl = fclk_rate / omap->speed;
445 hsscll = scl - (scl / 3) - 7;
446 hssclh = (scl / 3) - 5;
447 } else if (omap->speed > 100) {
448 unsigned long scl;
449
450 /* Fast mode */
451 scl = internal_clk / omap->speed;
452 fsscll = scl - (scl / 3) - 7;
453 fssclh = (scl / 3) - 5;
454 } else {
455 /* Standard mode */
456 fsscll = internal_clk / (omap->speed * 2) - 7;
457 fssclh = internal_clk / (omap->speed * 2) - 5;
458 }
459 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
460 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
461 } else {
462 /* Program desired operating rate */
463 fclk_rate /= (psc + 1) * 1000;
464 if (psc > 2)
465 psc = 2;
466 scll = fclk_rate / (omap->speed * 2) - 7 + psc;
467 sclh = fclk_rate / (omap->speed * 2) - 7 + psc;
468 }
469
470 omap->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
471 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
472 OMAP_I2C_IE_AL) | ((omap->fifo_size) ?
473 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
474
475 omap->pscstate = psc;
476 omap->scllstate = scll;
477 omap->sclhstate = sclh;
478
479 if (omap->rev <= OMAP_I2C_REV_ON_3430_3530) {
480 /* Not implemented */
481 omap->bb_valid = 1;
482 }
483
484 __omap_i2c_init(omap);
485
486 return 0;
487 }
488
489 /*
490 * Try bus recovery, but only if SDA is actually low.
491 */
492 static int omap_i2c_recover_bus(struct omap_i2c_dev *omap)
493 {
494 u16 systest;
495
496 systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG);
497 if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&
498 (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC))
499 return 0; /* bus seems to already be fine */
500 if (!(systest & OMAP_I2C_SYSTEST_SCL_I_FUNC))
501 return -EBUSY; /* recovery would not fix SCL */
502 return i2c_recover_bus(&omap->adapter);
503 }
504
505 /*
506 * Waiting on Bus Busy
507 */
508 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *omap)
509 {
510 unsigned long timeout;
511
512 timeout = jiffies + OMAP_I2C_TIMEOUT;
513 while (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
514 if (time_after(jiffies, timeout))
515 return omap_i2c_recover_bus(omap);
516 msleep(1);
517 }
518
519 return 0;
520 }
521
522 /*
523 * Wait while BB-bit doesn't reflect the I2C bus state
524 *
525 * In a multimaster environment, after IP software reset, BB-bit value doesn't
526 * correspond to the current bus state. It may happen what BB-bit will be 0,
527 * while the bus is busy due to another I2C master activity.
528 * Here are BB-bit values after reset:
529 * SDA SCL BB NOTES
530 * 0 0 0 1, 2
531 * 1 0 0 1, 2
532 * 0 1 1
533 * 1 1 0 3
534 * Later, if IP detect SDA=0 and SCL=1 (ACK) or SDA 1->0 while SCL=1 (START)
535 * combinations on the bus, it set BB-bit to 1.
536 * If IP detect SDA 0->1 while SCL=1 (STOP) combination on the bus,
537 * it set BB-bit to 0 and BF to 1.
538 * BB and BF bits correctly tracks the bus state while IP is suspended
539 * BB bit became valid on the next FCLK clock after CON_EN bit set
540 *
541 * NOTES:
542 * 1. Any transfer started when BB=0 and bus is busy wouldn't be
543 * completed by IP and results in controller timeout.
544 * 2. Any transfer started when BB=0 and SCL=0 results in IP
545 * starting to drive SDA low. In that case IP corrupt data
546 * on the bus.
547 * 3. Any transfer started in the middle of another master's transfer
548 * results in unpredictable results and data corruption
549 */
550 static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *omap)
551 {
552 unsigned long bus_free_timeout = 0;
553 unsigned long timeout;
554 int bus_free = 0;
555 u16 stat, systest;
556
557 if (omap->bb_valid)
558 return 0;
559
560 timeout = jiffies + OMAP_I2C_TIMEOUT;
561 while (1) {
562 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
563 /*
564 * We will see BB or BF event in a case IP had detected any
565 * activity on the I2C bus. Now IP correctly tracks the bus
566 * state. BB-bit value is valid.
567 */
568 if (stat & (OMAP_I2C_STAT_BB | OMAP_I2C_STAT_BF))
569 break;
570
571 /*
572 * Otherwise, we must look signals on the bus to make
573 * the right decision.
574 */
575 systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG);
576 if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&
577 (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) {
578 if (!bus_free) {
579 bus_free_timeout = jiffies +
580 OMAP_I2C_BUS_FREE_TIMEOUT;
581 bus_free = 1;
582 }
583
584 /*
585 * SDA and SCL lines was high for 10 ms without bus
586 * activity detected. The bus is free. Consider
587 * BB-bit value is valid.
588 */
589 if (time_after(jiffies, bus_free_timeout))
590 break;
591 } else {
592 bus_free = 0;
593 }
594
595 if (time_after(jiffies, timeout)) {
596 /*
597 * SDA or SCL were low for the entire timeout without
598 * any activity detected. Most likely, a slave is
599 * locking up the bus with no master driving the clock.
600 */
601 dev_warn(omap->dev, "timeout waiting for bus ready\n");
602 return omap_i2c_recover_bus(omap);
603 }
604
605 msleep(1);
606 }
607
608 omap->bb_valid = 1;
609 return 0;
610 }
611
612 static void omap_i2c_resize_fifo(struct omap_i2c_dev *omap, u8 size, bool is_rx)
613 {
614 u16 buf;
615
616 if (omap->flags & OMAP_I2C_FLAG_NO_FIFO)
617 return;
618
619 /*
620 * Set up notification threshold based on message size. We're doing
621 * this to try and avoid draining feature as much as possible. Whenever
622 * we have big messages to transfer (bigger than our total fifo size)
623 * then we might use draining feature to transfer the remaining bytes.
624 */
625
626 omap->threshold = clamp(size, (u8) 1, omap->fifo_size);
627
628 buf = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
629
630 if (is_rx) {
631 /* Clear RX Threshold */
632 buf &= ~(0x3f << 8);
633 buf |= ((omap->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
634 } else {
635 /* Clear TX Threshold */
636 buf &= ~0x3f;
637 buf |= (omap->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
638 }
639
640 omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, buf);
641
642 if (omap->rev < OMAP_I2C_REV_ON_3630)
643 omap->b_hw = 1; /* Enable hardware fixes */
644
645 /* calculate wakeup latency constraint for MPU */
646 if (omap->set_mpu_wkup_lat != NULL)
647 omap->latency = (1000000 * omap->threshold) /
648 (1000 * omap->speed / 8);
649 }
650
651 /*
652 * Low level master read/write transaction.
653 */
654 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
655 struct i2c_msg *msg, int stop)
656 {
657 struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
658 unsigned long timeout;
659 u16 w;
660
661 dev_dbg(omap->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
662 msg->addr, msg->len, msg->flags, stop);
663
664 if (msg->len == 0)
665 return -EINVAL;
666
667 omap->receiver = !!(msg->flags & I2C_M_RD);
668 omap_i2c_resize_fifo(omap, msg->len, omap->receiver);
669
670 omap_i2c_write_reg(omap, OMAP_I2C_SA_REG, msg->addr);
671
672 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
673 omap->buf = msg->buf;
674 omap->buf_len = msg->len;
675
676 /* make sure writes to omap->buf_len are ordered */
677 barrier();
678
679 omap_i2c_write_reg(omap, OMAP_I2C_CNT_REG, omap->buf_len);
680
681 /* Clear the FIFO Buffers */
682 w = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
683 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
684 omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, w);
685
686 reinit_completion(&omap->cmd_complete);
687 omap->cmd_err = 0;
688
689 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
690
691 /* High speed configuration */
692 if (omap->speed > 400)
693 w |= OMAP_I2C_CON_OPMODE_HS;
694
695 if (msg->flags & I2C_M_STOP)
696 stop = 1;
697 if (msg->flags & I2C_M_TEN)
698 w |= OMAP_I2C_CON_XA;
699 if (!(msg->flags & I2C_M_RD))
700 w |= OMAP_I2C_CON_TRX;
701
702 if (!omap->b_hw && stop)
703 w |= OMAP_I2C_CON_STP;
704 /*
705 * NOTE: STAT_BB bit could became 1 here if another master occupy
706 * the bus. IP successfully complete transfer when the bus will be
707 * free again (BB reset to 0).
708 */
709 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
710
711 /*
712 * Don't write stt and stp together on some hardware.
713 */
714 if (omap->b_hw && stop) {
715 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
716 u16 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
717 while (con & OMAP_I2C_CON_STT) {
718 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
719
720 /* Let the user know if i2c is in a bad state */
721 if (time_after(jiffies, delay)) {
722 dev_err(omap->dev, "controller timed out "
723 "waiting for start condition to finish\n");
724 return -ETIMEDOUT;
725 }
726 cpu_relax();
727 }
728
729 w |= OMAP_I2C_CON_STP;
730 w &= ~OMAP_I2C_CON_STT;
731 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
732 }
733
734 /*
735 * REVISIT: We should abort the transfer on signals, but the bus goes
736 * into arbitration and we're currently unable to recover from it.
737 */
738 timeout = wait_for_completion_timeout(&omap->cmd_complete,
739 OMAP_I2C_TIMEOUT);
740 if (timeout == 0) {
741 dev_err(omap->dev, "controller timed out\n");
742 omap_i2c_reset(omap);
743 __omap_i2c_init(omap);
744 return -ETIMEDOUT;
745 }
746
747 if (likely(!omap->cmd_err))
748 return 0;
749
750 /* We have an error */
751 if (omap->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) {
752 omap_i2c_reset(omap);
753 __omap_i2c_init(omap);
754 return -EIO;
755 }
756
757 if (omap->cmd_err & OMAP_I2C_STAT_AL)
758 return -EAGAIN;
759
760 if (omap->cmd_err & OMAP_I2C_STAT_NACK) {
761 if (msg->flags & I2C_M_IGNORE_NAK)
762 return 0;
763
764 w = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
765 w |= OMAP_I2C_CON_STP;
766 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
767 return -EREMOTEIO;
768 }
769 return -EIO;
770 }
771
772
773 /*
774 * Prepare controller for a transaction and call omap_i2c_xfer_msg
775 * to do the work during IRQ processing.
776 */
777 static int
778 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
779 {
780 struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
781 int i;
782 int r;
783
784 r = pm_runtime_get_sync(omap->dev);
785 if (r < 0)
786 goto out;
787
788 r = omap_i2c_wait_for_bb_valid(omap);
789 if (r < 0)
790 goto out;
791
792 r = omap_i2c_wait_for_bb(omap);
793 if (r < 0)
794 goto out;
795
796 if (omap->set_mpu_wkup_lat != NULL)
797 omap->set_mpu_wkup_lat(omap->dev, omap->latency);
798
799 for (i = 0; i < num; i++) {
800 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
801 if (r != 0)
802 break;
803 }
804
805 if (r == 0)
806 r = num;
807
808 omap_i2c_wait_for_bb(omap);
809
810 if (omap->set_mpu_wkup_lat != NULL)
811 omap->set_mpu_wkup_lat(omap->dev, -1);
812
813 out:
814 pm_runtime_mark_last_busy(omap->dev);
815 pm_runtime_put_autosuspend(omap->dev);
816 return r;
817 }
818
819 static u32
820 omap_i2c_func(struct i2c_adapter *adap)
821 {
822 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
823 I2C_FUNC_PROTOCOL_MANGLING;
824 }
825
826 static inline void
827 omap_i2c_complete_cmd(struct omap_i2c_dev *omap, u16 err)
828 {
829 omap->cmd_err |= err;
830 complete(&omap->cmd_complete);
831 }
832
833 static inline void
834 omap_i2c_ack_stat(struct omap_i2c_dev *omap, u16 stat)
835 {
836 omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, stat);
837 }
838
839 static inline void i2c_omap_errata_i207(struct omap_i2c_dev *omap, u16 stat)
840 {
841 /*
842 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
843 * Not applicable for OMAP4.
844 * Under certain rare conditions, RDR could be set again
845 * when the bus is busy, then ignore the interrupt and
846 * clear the interrupt.
847 */
848 if (stat & OMAP_I2C_STAT_RDR) {
849 /* Step 1: If RDR is set, clear it */
850 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
851
852 /* Step 2: */
853 if (!(omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
854 & OMAP_I2C_STAT_BB)) {
855
856 /* Step 3: */
857 if (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
858 & OMAP_I2C_STAT_RDR) {
859 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
860 dev_dbg(omap->dev, "RDR when bus is busy.\n");
861 }
862
863 }
864 }
865 }
866
867 /* rev1 devices are apparently only on some 15xx */
868 #ifdef CONFIG_ARCH_OMAP15XX
869
870 static irqreturn_t
871 omap_i2c_omap1_isr(int this_irq, void *dev_id)
872 {
873 struct omap_i2c_dev *omap = dev_id;
874 u16 iv, w;
875
876 if (pm_runtime_suspended(omap->dev))
877 return IRQ_NONE;
878
879 iv = omap_i2c_read_reg(omap, OMAP_I2C_IV_REG);
880 switch (iv) {
881 case 0x00: /* None */
882 break;
883 case 0x01: /* Arbitration lost */
884 dev_err(omap->dev, "Arbitration lost\n");
885 omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_AL);
886 break;
887 case 0x02: /* No acknowledgement */
888 omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_NACK);
889 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
890 break;
891 case 0x03: /* Register access ready */
892 omap_i2c_complete_cmd(omap, 0);
893 break;
894 case 0x04: /* Receive data ready */
895 if (omap->buf_len) {
896 w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
897 *omap->buf++ = w;
898 omap->buf_len--;
899 if (omap->buf_len) {
900 *omap->buf++ = w >> 8;
901 omap->buf_len--;
902 }
903 } else
904 dev_err(omap->dev, "RRDY IRQ while no data requested\n");
905 break;
906 case 0x05: /* Transmit data ready */
907 if (omap->buf_len) {
908 w = *omap->buf++;
909 omap->buf_len--;
910 if (omap->buf_len) {
911 w |= *omap->buf++ << 8;
912 omap->buf_len--;
913 }
914 omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
915 } else
916 dev_err(omap->dev, "XRDY IRQ while no data to send\n");
917 break;
918 default:
919 return IRQ_NONE;
920 }
921
922 return IRQ_HANDLED;
923 }
924 #else
925 #define omap_i2c_omap1_isr NULL
926 #endif
927
928 /*
929 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
930 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
931 * them from the memory to the I2C interface.
932 */
933 static int errata_omap3_i462(struct omap_i2c_dev *omap)
934 {
935 unsigned long timeout = 10000;
936 u16 stat;
937
938 do {
939 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
940 if (stat & OMAP_I2C_STAT_XUDF)
941 break;
942
943 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
944 omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_XRDY |
945 OMAP_I2C_STAT_XDR));
946 if (stat & OMAP_I2C_STAT_NACK) {
947 omap->cmd_err |= OMAP_I2C_STAT_NACK;
948 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
949 }
950
951 if (stat & OMAP_I2C_STAT_AL) {
952 dev_err(omap->dev, "Arbitration lost\n");
953 omap->cmd_err |= OMAP_I2C_STAT_AL;
954 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
955 }
956
957 return -EIO;
958 }
959
960 cpu_relax();
961 } while (--timeout);
962
963 if (!timeout) {
964 dev_err(omap->dev, "timeout waiting on XUDF bit\n");
965 return 0;
966 }
967
968 return 0;
969 }
970
971 static void omap_i2c_receive_data(struct omap_i2c_dev *omap, u8 num_bytes,
972 bool is_rdr)
973 {
974 u16 w;
975
976 while (num_bytes--) {
977 w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
978 *omap->buf++ = w;
979 omap->buf_len--;
980
981 /*
982 * Data reg in 2430, omap3 and
983 * omap4 is 8 bit wide
984 */
985 if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
986 *omap->buf++ = w >> 8;
987 omap->buf_len--;
988 }
989 }
990 }
991
992 static int omap_i2c_transmit_data(struct omap_i2c_dev *omap, u8 num_bytes,
993 bool is_xdr)
994 {
995 u16 w;
996
997 while (num_bytes--) {
998 w = *omap->buf++;
999 omap->buf_len--;
1000
1001 /*
1002 * Data reg in 2430, omap3 and
1003 * omap4 is 8 bit wide
1004 */
1005 if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
1006 w |= *omap->buf++ << 8;
1007 omap->buf_len--;
1008 }
1009
1010 if (omap->errata & I2C_OMAP_ERRATA_I462) {
1011 int ret;
1012
1013 ret = errata_omap3_i462(omap);
1014 if (ret < 0)
1015 return ret;
1016 }
1017
1018 omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
1019 }
1020
1021 return 0;
1022 }
1023
1024 static irqreturn_t
1025 omap_i2c_isr(int irq, void *dev_id)
1026 {
1027 struct omap_i2c_dev *omap = dev_id;
1028 irqreturn_t ret = IRQ_HANDLED;
1029 u16 mask;
1030 u16 stat;
1031
1032 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
1033 mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1034
1035 if (stat & mask)
1036 ret = IRQ_WAKE_THREAD;
1037
1038 return ret;
1039 }
1040
1041 static irqreturn_t
1042 omap_i2c_isr_thread(int this_irq, void *dev_id)
1043 {
1044 struct omap_i2c_dev *omap = dev_id;
1045 u16 bits;
1046 u16 stat;
1047 int err = 0, count = 0;
1048
1049 do {
1050 bits = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1051 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
1052 stat &= bits;
1053
1054 /* If we're in receiver mode, ignore XDR/XRDY */
1055 if (omap->receiver)
1056 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
1057 else
1058 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
1059
1060 if (!stat) {
1061 /* my work here is done */
1062 goto out;
1063 }
1064
1065 dev_dbg(omap->dev, "IRQ (ISR = 0x%04x)\n", stat);
1066 if (count++ == 100) {
1067 dev_warn(omap->dev, "Too much work in one IRQ\n");
1068 break;
1069 }
1070
1071 if (stat & OMAP_I2C_STAT_NACK) {
1072 err |= OMAP_I2C_STAT_NACK;
1073 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
1074 }
1075
1076 if (stat & OMAP_I2C_STAT_AL) {
1077 dev_err(omap->dev, "Arbitration lost\n");
1078 err |= OMAP_I2C_STAT_AL;
1079 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
1080 }
1081
1082 /*
1083 * ProDB0017052: Clear ARDY bit twice
1084 */
1085 if (stat & OMAP_I2C_STAT_ARDY)
1086 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ARDY);
1087
1088 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
1089 OMAP_I2C_STAT_AL)) {
1090 omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_RRDY |
1091 OMAP_I2C_STAT_RDR |
1092 OMAP_I2C_STAT_XRDY |
1093 OMAP_I2C_STAT_XDR |
1094 OMAP_I2C_STAT_ARDY));
1095 break;
1096 }
1097
1098 if (stat & OMAP_I2C_STAT_RDR) {
1099 u8 num_bytes = 1;
1100
1101 if (omap->fifo_size)
1102 num_bytes = omap->buf_len;
1103
1104 if (omap->errata & I2C_OMAP_ERRATA_I207) {
1105 i2c_omap_errata_i207(omap, stat);
1106 num_bytes = (omap_i2c_read_reg(omap,
1107 OMAP_I2C_BUFSTAT_REG) >> 8) & 0x3F;
1108 }
1109
1110 omap_i2c_receive_data(omap, num_bytes, true);
1111 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
1112 continue;
1113 }
1114
1115 if (stat & OMAP_I2C_STAT_RRDY) {
1116 u8 num_bytes = 1;
1117
1118 if (omap->threshold)
1119 num_bytes = omap->threshold;
1120
1121 omap_i2c_receive_data(omap, num_bytes, false);
1122 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RRDY);
1123 continue;
1124 }
1125
1126 if (stat & OMAP_I2C_STAT_XDR) {
1127 u8 num_bytes = 1;
1128 int ret;
1129
1130 if (omap->fifo_size)
1131 num_bytes = omap->buf_len;
1132
1133 ret = omap_i2c_transmit_data(omap, num_bytes, true);
1134 if (ret < 0)
1135 break;
1136
1137 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XDR);
1138 continue;
1139 }
1140
1141 if (stat & OMAP_I2C_STAT_XRDY) {
1142 u8 num_bytes = 1;
1143 int ret;
1144
1145 if (omap->threshold)
1146 num_bytes = omap->threshold;
1147
1148 ret = omap_i2c_transmit_data(omap, num_bytes, false);
1149 if (ret < 0)
1150 break;
1151
1152 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XRDY);
1153 continue;
1154 }
1155
1156 if (stat & OMAP_I2C_STAT_ROVR) {
1157 dev_err(omap->dev, "Receive overrun\n");
1158 err |= OMAP_I2C_STAT_ROVR;
1159 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ROVR);
1160 break;
1161 }
1162
1163 if (stat & OMAP_I2C_STAT_XUDF) {
1164 dev_err(omap->dev, "Transmit underflow\n");
1165 err |= OMAP_I2C_STAT_XUDF;
1166 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XUDF);
1167 break;
1168 }
1169 } while (stat);
1170
1171 omap_i2c_complete_cmd(omap, err);
1172
1173 out:
1174 return IRQ_HANDLED;
1175 }
1176
1177 static const struct i2c_algorithm omap_i2c_algo = {
1178 .master_xfer = omap_i2c_xfer,
1179 .functionality = omap_i2c_func,
1180 };
1181
1182 #ifdef CONFIG_OF
1183 static struct omap_i2c_bus_platform_data omap2420_pdata = {
1184 .rev = OMAP_I2C_IP_VERSION_1,
1185 .flags = OMAP_I2C_FLAG_NO_FIFO |
1186 OMAP_I2C_FLAG_SIMPLE_CLOCK |
1187 OMAP_I2C_FLAG_16BIT_DATA_REG |
1188 OMAP_I2C_FLAG_BUS_SHIFT_2,
1189 };
1190
1191 static struct omap_i2c_bus_platform_data omap2430_pdata = {
1192 .rev = OMAP_I2C_IP_VERSION_1,
1193 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
1194 OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
1195 };
1196
1197 static struct omap_i2c_bus_platform_data omap3_pdata = {
1198 .rev = OMAP_I2C_IP_VERSION_1,
1199 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
1200 };
1201
1202 static struct omap_i2c_bus_platform_data omap4_pdata = {
1203 .rev = OMAP_I2C_IP_VERSION_2,
1204 };
1205
1206 static const struct of_device_id omap_i2c_of_match[] = {
1207 {
1208 .compatible = "ti,omap4-i2c",
1209 .data = &omap4_pdata,
1210 },
1211 {
1212 .compatible = "ti,omap3-i2c",
1213 .data = &omap3_pdata,
1214 },
1215 {
1216 .compatible = "ti,omap2430-i2c",
1217 .data = &omap2430_pdata,
1218 },
1219 {
1220 .compatible = "ti,omap2420-i2c",
1221 .data = &omap2420_pdata,
1222 },
1223 { },
1224 };
1225 MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1226 #endif
1227
1228 #define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14)
1229
1230 #define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
1231 #define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)
1232
1233 #define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
1234 #define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
1235 #define OMAP_I2C_SCHEME_0 0
1236 #define OMAP_I2C_SCHEME_1 1
1237
1238 static int omap_i2c_get_scl(struct i2c_adapter *adap)
1239 {
1240 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1241 u32 reg;
1242
1243 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1244
1245 return reg & OMAP_I2C_SYSTEST_SCL_I_FUNC;
1246 }
1247
1248 static int omap_i2c_get_sda(struct i2c_adapter *adap)
1249 {
1250 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1251 u32 reg;
1252
1253 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1254
1255 return reg & OMAP_I2C_SYSTEST_SDA_I_FUNC;
1256 }
1257
1258 static void omap_i2c_set_scl(struct i2c_adapter *adap, int val)
1259 {
1260 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1261 u32 reg;
1262
1263 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1264 if (val)
1265 reg |= OMAP_I2C_SYSTEST_SCL_O;
1266 else
1267 reg &= ~OMAP_I2C_SYSTEST_SCL_O;
1268 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1269 }
1270
1271 static void omap_i2c_prepare_recovery(struct i2c_adapter *adap)
1272 {
1273 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1274 u32 reg;
1275
1276 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1277 /* enable test mode */
1278 reg |= OMAP_I2C_SYSTEST_ST_EN;
1279 /* select SDA/SCL IO mode */
1280 reg |= 3 << OMAP_I2C_SYSTEST_TMODE_SHIFT;
1281 /* set SCL to high-impedance state (reset value is 0) */
1282 reg |= OMAP_I2C_SYSTEST_SCL_O;
1283 /* set SDA to high-impedance state (reset value is 0) */
1284 reg |= OMAP_I2C_SYSTEST_SDA_O;
1285 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1286 }
1287
1288 static void omap_i2c_unprepare_recovery(struct i2c_adapter *adap)
1289 {
1290 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1291 u32 reg;
1292
1293 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1294 /* restore reset values */
1295 reg &= ~OMAP_I2C_SYSTEST_ST_EN;
1296 reg &= ~OMAP_I2C_SYSTEST_TMODE_MASK;
1297 reg &= ~OMAP_I2C_SYSTEST_SCL_O;
1298 reg &= ~OMAP_I2C_SYSTEST_SDA_O;
1299 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1300 }
1301
1302 static struct i2c_bus_recovery_info omap_i2c_bus_recovery_info = {
1303 .get_scl = omap_i2c_get_scl,
1304 .get_sda = omap_i2c_get_sda,
1305 .set_scl = omap_i2c_set_scl,
1306 .prepare_recovery = omap_i2c_prepare_recovery,
1307 .unprepare_recovery = omap_i2c_unprepare_recovery,
1308 .recover_bus = i2c_generic_scl_recovery,
1309 };
1310
1311 static int
1312 omap_i2c_probe(struct platform_device *pdev)
1313 {
1314 struct omap_i2c_dev *omap;
1315 struct i2c_adapter *adap;
1316 struct resource *mem;
1317 const struct omap_i2c_bus_platform_data *pdata =
1318 dev_get_platdata(&pdev->dev);
1319 struct device_node *node = pdev->dev.of_node;
1320 const struct of_device_id *match;
1321 int irq;
1322 int r;
1323 u32 rev;
1324 u16 minor, major;
1325
1326 irq = platform_get_irq(pdev, 0);
1327 if (irq < 0) {
1328 dev_err(&pdev->dev, "no irq resource?\n");
1329 return irq;
1330 }
1331
1332 omap = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
1333 if (!omap)
1334 return -ENOMEM;
1335
1336 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1337 omap->base = devm_ioremap_resource(&pdev->dev, mem);
1338 if (IS_ERR(omap->base))
1339 return PTR_ERR(omap->base);
1340
1341 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
1342 if (match) {
1343 u32 freq = 100000; /* default to 100000 Hz */
1344
1345 pdata = match->data;
1346 omap->flags = pdata->flags;
1347
1348 of_property_read_u32(node, "clock-frequency", &freq);
1349 /* convert DT freq value in Hz into kHz for speed */
1350 omap->speed = freq / 1000;
1351 } else if (pdata != NULL) {
1352 omap->speed = pdata->clkrate;
1353 omap->flags = pdata->flags;
1354 omap->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1355 }
1356
1357 omap->dev = &pdev->dev;
1358 omap->irq = irq;
1359
1360 platform_set_drvdata(pdev, omap);
1361 init_completion(&omap->cmd_complete);
1362
1363 omap->reg_shift = (omap->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
1364
1365 pm_runtime_enable(omap->dev);
1366 pm_runtime_set_autosuspend_delay(omap->dev, OMAP_I2C_PM_TIMEOUT);
1367 pm_runtime_use_autosuspend(omap->dev);
1368
1369 r = pm_runtime_get_sync(omap->dev);
1370 if (r < 0)
1371 goto err_free_mem;
1372
1373 /*
1374 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
1375 * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
1376 * Also since the omap_i2c_read_reg uses reg_map_ip_* a
1377 * readw_relaxed is done.
1378 */
1379 rev = readw_relaxed(omap->base + 0x04);
1380
1381 omap->scheme = OMAP_I2C_SCHEME(rev);
1382 switch (omap->scheme) {
1383 case OMAP_I2C_SCHEME_0:
1384 omap->regs = (u8 *)reg_map_ip_v1;
1385 omap->rev = omap_i2c_read_reg(omap, OMAP_I2C_REV_REG);
1386 minor = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
1387 major = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
1388 break;
1389 case OMAP_I2C_SCHEME_1:
1390 /* FALLTHROUGH */
1391 default:
1392 omap->regs = (u8 *)reg_map_ip_v2;
1393 rev = (rev << 16) |
1394 omap_i2c_read_reg(omap, OMAP_I2C_IP_V2_REVNB_LO);
1395 minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
1396 major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
1397 omap->rev = rev;
1398 }
1399
1400 omap->errata = 0;
1401
1402 if (omap->rev >= OMAP_I2C_REV_ON_2430 &&
1403 omap->rev < OMAP_I2C_REV_ON_4430_PLUS)
1404 omap->errata |= I2C_OMAP_ERRATA_I207;
1405
1406 if (omap->rev <= OMAP_I2C_REV_ON_3430_3530)
1407 omap->errata |= I2C_OMAP_ERRATA_I462;
1408
1409 if (!(omap->flags & OMAP_I2C_FLAG_NO_FIFO)) {
1410 u16 s;
1411
1412 /* Set up the fifo size - Get total size */
1413 s = (omap_i2c_read_reg(omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1414 omap->fifo_size = 0x8 << s;
1415
1416 /*
1417 * Set up notification threshold as half the total available
1418 * size. This is to ensure that we can handle the status on int
1419 * call back latencies.
1420 */
1421
1422 omap->fifo_size = (omap->fifo_size / 2);
1423
1424 if (omap->rev < OMAP_I2C_REV_ON_3630)
1425 omap->b_hw = 1; /* Enable hardware fixes */
1426
1427 /* calculate wakeup latency constraint for MPU */
1428 if (omap->set_mpu_wkup_lat != NULL)
1429 omap->latency = (1000000 * omap->fifo_size) /
1430 (1000 * omap->speed / 8);
1431 }
1432
1433 /* reset ASAP, clearing any IRQs */
1434 omap_i2c_init(omap);
1435
1436 if (omap->rev < OMAP_I2C_OMAP1_REV_2)
1437 r = devm_request_irq(&pdev->dev, omap->irq, omap_i2c_omap1_isr,
1438 IRQF_NO_SUSPEND, pdev->name, omap);
1439 else
1440 r = devm_request_threaded_irq(&pdev->dev, omap->irq,
1441 omap_i2c_isr, omap_i2c_isr_thread,
1442 IRQF_NO_SUSPEND | IRQF_ONESHOT,
1443 pdev->name, omap);
1444
1445 if (r) {
1446 dev_err(omap->dev, "failure requesting irq %i\n", omap->irq);
1447 goto err_unuse_clocks;
1448 }
1449
1450 adap = &omap->adapter;
1451 i2c_set_adapdata(adap, omap);
1452 adap->owner = THIS_MODULE;
1453 adap->class = I2C_CLASS_DEPRECATED;
1454 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1455 adap->algo = &omap_i2c_algo;
1456 adap->dev.parent = &pdev->dev;
1457 adap->dev.of_node = pdev->dev.of_node;
1458 adap->bus_recovery_info = &omap_i2c_bus_recovery_info;
1459
1460 /* i2c device drivers may be active on return from add_adapter() */
1461 adap->nr = pdev->id;
1462 r = i2c_add_numbered_adapter(adap);
1463 if (r)
1464 goto err_unuse_clocks;
1465
1466 dev_info(omap->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
1467 major, minor, omap->speed);
1468
1469 pm_runtime_mark_last_busy(omap->dev);
1470 pm_runtime_put_autosuspend(omap->dev);
1471
1472 return 0;
1473
1474 err_unuse_clocks:
1475 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
1476 pm_runtime_dont_use_autosuspend(omap->dev);
1477 pm_runtime_put_sync(omap->dev);
1478 pm_runtime_disable(&pdev->dev);
1479 err_free_mem:
1480
1481 return r;
1482 }
1483
1484 static int omap_i2c_remove(struct platform_device *pdev)
1485 {
1486 struct omap_i2c_dev *omap = platform_get_drvdata(pdev);
1487 int ret;
1488
1489 i2c_del_adapter(&omap->adapter);
1490 ret = pm_runtime_get_sync(&pdev->dev);
1491 if (ret < 0)
1492 return ret;
1493
1494 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
1495 pm_runtime_dont_use_autosuspend(&pdev->dev);
1496 pm_runtime_put_sync(&pdev->dev);
1497 pm_runtime_disable(&pdev->dev);
1498 return 0;
1499 }
1500
1501 #ifdef CONFIG_PM
1502 static int omap_i2c_runtime_suspend(struct device *dev)
1503 {
1504 struct omap_i2c_dev *omap = dev_get_drvdata(dev);
1505
1506 omap->iestate = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1507
1508 if (omap->scheme == OMAP_I2C_SCHEME_0)
1509 omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, 0);
1510 else
1511 omap_i2c_write_reg(omap, OMAP_I2C_IP_V2_IRQENABLE_CLR,
1512 OMAP_I2C_IP_V2_INTERRUPTS_MASK);
1513
1514 if (omap->rev < OMAP_I2C_OMAP1_REV_2) {
1515 omap_i2c_read_reg(omap, OMAP_I2C_IV_REG); /* Read clears */
1516 } else {
1517 omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, omap->iestate);
1518
1519 /* Flush posted write */
1520 omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
1521 }
1522
1523 pinctrl_pm_select_sleep_state(dev);
1524
1525 return 0;
1526 }
1527
1528 static int omap_i2c_runtime_resume(struct device *dev)
1529 {
1530 struct omap_i2c_dev *omap = dev_get_drvdata(dev);
1531
1532 pinctrl_pm_select_default_state(dev);
1533
1534 if (!omap->regs)
1535 return 0;
1536
1537 __omap_i2c_init(omap);
1538
1539 return 0;
1540 }
1541
1542 static const struct dev_pm_ops omap_i2c_pm_ops = {
1543 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1544 omap_i2c_runtime_resume, NULL)
1545 };
1546 #define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1547 #else
1548 #define OMAP_I2C_PM_OPS NULL
1549 #endif /* CONFIG_PM */
1550
1551 static struct platform_driver omap_i2c_driver = {
1552 .probe = omap_i2c_probe,
1553 .remove = omap_i2c_remove,
1554 .driver = {
1555 .name = "omap_i2c",
1556 .pm = OMAP_I2C_PM_OPS,
1557 .of_match_table = of_match_ptr(omap_i2c_of_match),
1558 },
1559 };
1560
1561 /* I2C may be needed to bring up other drivers */
1562 static int __init
1563 omap_i2c_init_driver(void)
1564 {
1565 return platform_driver_register(&omap_i2c_driver);
1566 }
1567 subsys_initcall(omap_i2c_init_driver);
1568
1569 static void __exit omap_i2c_exit_driver(void)
1570 {
1571 platform_driver_unregister(&omap_i2c_driver);
1572 }
1573 module_exit(omap_i2c_exit_driver);
1574
1575 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1576 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1577 MODULE_LICENSE("GPL");
1578 MODULE_ALIAS("platform:omap_i2c");
Linux with added FPC-III support