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Merge tag 'nios2-v4.19-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/lftan...
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-xiic.c
blob9a71e50d21f1fbae53ebdb2b1831e7f6067a67b9
1 /*
2 * i2c-xiic.c
3 * Copyright (c) 2002-2007 Xilinx Inc.
4 * Copyright (c) 2009-2010 Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 *
16 * This code was implemented by Mocean Laboratories AB when porting linux
17 * to the automotive development board Russellville. The copyright holder
18 * as seen in the header is Intel corporation.
19 * Mocean Laboratories forked off the GNU/Linux platform work into a
20 * separate company called Pelagicore AB, which committed the code to the
21 * kernel.
22 */
23
24 /* Supports:
25 * Xilinx IIC
26 */
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/err.h>
31 #include <linux/delay.h>
32 #include <linux/platform_device.h>
33 #include <linux/i2c.h>
34 #include <linux/interrupt.h>
35 #include <linux/wait.h>
36 #include <linux/platform_data/i2c-xiic.h>
37 #include <linux/io.h>
38 #include <linux/slab.h>
39 #include <linux/of.h>
40 #include <linux/clk.h>
41 #include <linux/pm_runtime.h>
42
43 #define DRIVER_NAME "xiic-i2c"
44
45 enum xilinx_i2c_state {
46 STATE_DONE,
47 STATE_ERROR,
48 STATE_START
49 };
50
51 enum xiic_endian {
52 LITTLE,
53 BIG
54 };
55
56 /**
57 * struct xiic_i2c - Internal representation of the XIIC I2C bus
58 * @base: Memory base of the HW registers
59 * @wait: Wait queue for callers
60 * @adap: Kernel adapter representation
61 * @tx_msg: Messages from above to be sent
62 * @lock: Mutual exclusion
63 * @tx_pos: Current pos in TX message
64 * @nmsgs: Number of messages in tx_msg
65 * @state: See STATE_
66 * @rx_msg: Current RX message
67 * @rx_pos: Position within current RX message
68 * @endianness: big/little-endian byte order
69 */
70 struct xiic_i2c {
71 struct device *dev;
72 void __iomem *base;
73 wait_queue_head_t wait;
74 struct i2c_adapter adap;
75 struct i2c_msg *tx_msg;
76 struct mutex lock;
77 unsigned int tx_pos;
78 unsigned int nmsgs;
79 enum xilinx_i2c_state state;
80 struct i2c_msg *rx_msg;
81 int rx_pos;
82 enum xiic_endian endianness;
83 struct clk *clk;
84 };
85
86
87 #define XIIC_MSB_OFFSET 0
88 #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
89
90 /*
91 * Register offsets in bytes from RegisterBase. Three is added to the
92 * base offset to access LSB (IBM style) of the word
93 */
94 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */
95 #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */
96 #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */
97 #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */
98 #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */
99 #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
100 #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
101 #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */
102 #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
103 #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */
104
105 /* Control Register masks */
106 #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
107 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
108 #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
109 #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
110 #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
111 #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
112 #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
113
114 /* Status Register masks */
115 #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
116 #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
117 #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
118 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
119 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
120 #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
121 #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
122 #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
123
124 /* Interrupt Status Register masks Interrupt occurs when... */
125 #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
126 #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
127 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
128 #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
129 #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
130 #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
131 #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
132 #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
133
134 /* The following constants specify the depth of the FIFOs */
135 #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
136 #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
137
138 /* The following constants specify groups of interrupts that are typically
139 * enabled or disables at the same time
140 */
141 #define XIIC_TX_INTERRUPTS \
142 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
143
144 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
145
146 /*
147 * Tx Fifo upper bit masks.
148 */
149 #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
150 #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
151
152 /*
153 * The following constants define the register offsets for the Interrupt
154 * registers. There are some holes in the memory map for reserved addresses
155 * to allow other registers to be added and still match the memory map of the
156 * interrupt controller registers
157 */
158 #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
159 #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
160 #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
161 #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
162
163 #define XIIC_RESET_MASK 0xAUL
164
165 #define XIIC_PM_TIMEOUT 1000 /* ms */
166 /*
167 * The following constant is used for the device global interrupt enable
168 * register, to enable all interrupts for the device, this is the only bit
169 * in the register
170 */
171 #define XIIC_GINTR_ENABLE_MASK 0x80000000UL
172
173 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
174 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
175
176 static void xiic_start_xfer(struct xiic_i2c *i2c);
177 static void __xiic_start_xfer(struct xiic_i2c *i2c);
178
179 /*
180 * For the register read and write functions, a little-endian and big-endian
181 * version are necessary. Endianness is detected during the probe function.
182 * Only the least significant byte [doublet] of the register are ever
183 * accessed. This requires an offset of 3 [2] from the base address for
184 * big-endian systems.
185 */
186
187 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
188 {
189 if (i2c->endianness == LITTLE)
190 iowrite8(value, i2c->base + reg);
191 else
192 iowrite8(value, i2c->base + reg + 3);
193 }
194
195 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
196 {
197 u8 ret;
198
199 if (i2c->endianness == LITTLE)
200 ret = ioread8(i2c->base + reg);
201 else
202 ret = ioread8(i2c->base + reg + 3);
203 return ret;
204 }
205
206 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
207 {
208 if (i2c->endianness == LITTLE)
209 iowrite16(value, i2c->base + reg);
210 else
211 iowrite16be(value, i2c->base + reg + 2);
212 }
213
214 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
215 {
216 if (i2c->endianness == LITTLE)
217 iowrite32(value, i2c->base + reg);
218 else
219 iowrite32be(value, i2c->base + reg);
220 }
221
222 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
223 {
224 u32 ret;
225
226 if (i2c->endianness == LITTLE)
227 ret = ioread32(i2c->base + reg);
228 else
229 ret = ioread32be(i2c->base + reg);
230 return ret;
231 }
232
233 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
234 {
235 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
236 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
237 }
238
239 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
240 {
241 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
242 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
243 }
244
245 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
246 {
247 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
248 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
249 }
250
251 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
252 {
253 xiic_irq_clr(i2c, mask);
254 xiic_irq_en(i2c, mask);
255 }
256
257 static void xiic_clear_rx_fifo(struct xiic_i2c *i2c)
258 {
259 u8 sr;
260 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
261 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
262 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET))
263 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
264 }
265
266 static void xiic_reinit(struct xiic_i2c *i2c)
267 {
268 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
269
270 /* Set receive Fifo depth to maximum (zero based). */
271 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
272
273 /* Reset Tx Fifo. */
274 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
275
276 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
277 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
278
279 /* make sure RX fifo is empty */
280 xiic_clear_rx_fifo(i2c);
281
282 /* Enable interrupts */
283 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
284
285 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK);
286 }
287
288 static void xiic_deinit(struct xiic_i2c *i2c)
289 {
290 u8 cr;
291
292 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
293
294 /* Disable IIC Device. */
295 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
296 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
297 }
298
299 static void xiic_read_rx(struct xiic_i2c *i2c)
300 {
301 u8 bytes_in_fifo;
302 int i;
303
304 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
305
306 dev_dbg(i2c->adap.dev.parent,
307 "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n",
308 __func__, bytes_in_fifo, xiic_rx_space(i2c),
309 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
310 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
311
312 if (bytes_in_fifo > xiic_rx_space(i2c))
313 bytes_in_fifo = xiic_rx_space(i2c);
314
315 for (i = 0; i < bytes_in_fifo; i++)
316 i2c->rx_msg->buf[i2c->rx_pos++] =
317 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
318
319 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET,
320 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ?
321 IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1);
322 }
323
324 static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
325 {
326 /* return the actual space left in the FIFO */
327 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
328 }
329
330 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
331 {
332 u8 fifo_space = xiic_tx_fifo_space(i2c);
333 int len = xiic_tx_space(i2c);
334
335 len = (len > fifo_space) ? fifo_space : len;
336
337 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
338 __func__, len, fifo_space);
339
340 while (len--) {
341 u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
342 if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) {
343 /* last message in transfer -> STOP */
344 data |= XIIC_TX_DYN_STOP_MASK;
345 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
346 }
347 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
348 }
349 }
350
351 static void xiic_wakeup(struct xiic_i2c *i2c, int code)
352 {
353 i2c->tx_msg = NULL;
354 i2c->rx_msg = NULL;
355 i2c->nmsgs = 0;
356 i2c->state = code;
357 wake_up(&i2c->wait);
358 }
359
360 static irqreturn_t xiic_process(int irq, void *dev_id)
361 {
362 struct xiic_i2c *i2c = dev_id;
363 u32 pend, isr, ier;
364 u32 clr = 0;
365
366 /* Get the interrupt Status from the IPIF. There is no clearing of
367 * interrupts in the IPIF. Interrupts must be cleared at the source.
368 * To find which interrupts are pending; AND interrupts pending with
369 * interrupts masked.
370 */
371 mutex_lock(&i2c->lock);
372 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
373 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
374 pend = isr & ier;
375
376 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n",
377 __func__, ier, isr, pend);
378 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n",
379 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
380 i2c->tx_msg, i2c->nmsgs);
381
382
383 /* Service requesting interrupt */
384 if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
385 ((pend & XIIC_INTR_TX_ERROR_MASK) &&
386 !(pend & XIIC_INTR_RX_FULL_MASK))) {
387 /* bus arbritration lost, or...
388 * Transmit error _OR_ RX completed
389 * if this happens when RX_FULL is not set
390 * this is probably a TX error
391 */
392
393 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
394
395 /* dynamic mode seem to suffer from problems if we just flushes
396 * fifos and the next message is a TX with len 0 (only addr)
397 * reset the IP instead of just flush fifos
398 */
399 xiic_reinit(i2c);
400
401 if (i2c->rx_msg)
402 xiic_wakeup(i2c, STATE_ERROR);
403 if (i2c->tx_msg)
404 xiic_wakeup(i2c, STATE_ERROR);
405 }
406 if (pend & XIIC_INTR_RX_FULL_MASK) {
407 /* Receive register/FIFO is full */
408
409 clr |= XIIC_INTR_RX_FULL_MASK;
410 if (!i2c->rx_msg) {
411 dev_dbg(i2c->adap.dev.parent,
412 "%s unexpected RX IRQ\n", __func__);
413 xiic_clear_rx_fifo(i2c);
414 goto out;
415 }
416
417 xiic_read_rx(i2c);
418 if (xiic_rx_space(i2c) == 0) {
419 /* this is the last part of the message */
420 i2c->rx_msg = NULL;
421
422 /* also clear TX error if there (RX complete) */
423 clr |= (isr & XIIC_INTR_TX_ERROR_MASK);
424
425 dev_dbg(i2c->adap.dev.parent,
426 "%s end of message, nmsgs: %d\n",
427 __func__, i2c->nmsgs);
428
429 /* send next message if this wasn't the last,
430 * otherwise the transfer will be finialise when
431 * receiving the bus not busy interrupt
432 */
433 if (i2c->nmsgs > 1) {
434 i2c->nmsgs--;
435 i2c->tx_msg++;
436 dev_dbg(i2c->adap.dev.parent,
437 "%s will start next...\n", __func__);
438
439 __xiic_start_xfer(i2c);
440 }
441 }
442 }
443 if (pend & XIIC_INTR_BNB_MASK) {
444 /* IIC bus has transitioned to not busy */
445 clr |= XIIC_INTR_BNB_MASK;
446
447 /* The bus is not busy, disable BusNotBusy interrupt */
448 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
449
450 if (!i2c->tx_msg)
451 goto out;
452
453 if ((i2c->nmsgs == 1) && !i2c->rx_msg &&
454 xiic_tx_space(i2c) == 0)
455 xiic_wakeup(i2c, STATE_DONE);
456 else
457 xiic_wakeup(i2c, STATE_ERROR);
458 }
459 if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
460 /* Transmit register/FIFO is empty or ½ empty */
461
462 clr |= (pend &
463 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK));
464
465 if (!i2c->tx_msg) {
466 dev_dbg(i2c->adap.dev.parent,
467 "%s unexpected TX IRQ\n", __func__);
468 goto out;
469 }
470
471 xiic_fill_tx_fifo(i2c);
472
473 /* current message sent and there is space in the fifo */
474 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) {
475 dev_dbg(i2c->adap.dev.parent,
476 "%s end of message sent, nmsgs: %d\n",
477 __func__, i2c->nmsgs);
478 if (i2c->nmsgs > 1) {
479 i2c->nmsgs--;
480 i2c->tx_msg++;
481 __xiic_start_xfer(i2c);
482 } else {
483 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
484
485 dev_dbg(i2c->adap.dev.parent,
486 "%s Got TX IRQ but no more to do...\n",
487 __func__);
488 }
489 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1))
490 /* current frame is sent and is last,
491 * make sure to disable tx half
492 */
493 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
494 }
495 out:
496 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
497
498 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
499 mutex_unlock(&i2c->lock);
500 return IRQ_HANDLED;
501 }
502
503 static int xiic_bus_busy(struct xiic_i2c *i2c)
504 {
505 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
506
507 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;
508 }
509
510 static int xiic_busy(struct xiic_i2c *i2c)
511 {
512 int tries = 3;
513 int err;
514
515 if (i2c->tx_msg)
516 return -EBUSY;
517
518 /* for instance if previous transfer was terminated due to TX error
519 * it might be that the bus is on it's way to become available
520 * give it at most 3 ms to wake
521 */
522 err = xiic_bus_busy(i2c);
523 while (err && tries--) {
524 msleep(1);
525 err = xiic_bus_busy(i2c);
526 }
527
528 return err;
529 }
530
531 static void xiic_start_recv(struct xiic_i2c *i2c)
532 {
533 u8 rx_watermark;
534 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
535
536 /* Clear and enable Rx full interrupt. */
537 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
538
539 /* we want to get all but last byte, because the TX_ERROR IRQ is used
540 * to inidicate error ACK on the address, and negative ack on the last
541 * received byte, so to not mix them receive all but last.
542 * In the case where there is only one byte to receive
543 * we can check if ERROR and RX full is set at the same time
544 */
545 rx_watermark = msg->len;
546 if (rx_watermark > IIC_RX_FIFO_DEPTH)
547 rx_watermark = IIC_RX_FIFO_DEPTH;
548 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);
549
550 if (!(msg->flags & I2C_M_NOSTART))
551 /* write the address */
552 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
553 i2c_8bit_addr_from_msg(msg) | XIIC_TX_DYN_START_MASK);
554
555 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
556
557 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
558 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));
559 if (i2c->nmsgs == 1)
560 /* very last, enable bus not busy as well */
561 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
562
563 /* the message is tx:ed */
564 i2c->tx_pos = msg->len;
565 }
566
567 static void xiic_start_send(struct xiic_i2c *i2c)
568 {
569 struct i2c_msg *msg = i2c->tx_msg;
570
571 xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK);
572
573 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",
574 __func__, msg, msg->len);
575 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
576 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
577 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
578
579 if (!(msg->flags & I2C_M_NOSTART)) {
580 /* write the address */
581 u16 data = i2c_8bit_addr_from_msg(msg) |
582 XIIC_TX_DYN_START_MASK;
583 if ((i2c->nmsgs == 1) && msg->len == 0)
584 /* no data and last message -> add STOP */
585 data |= XIIC_TX_DYN_STOP_MASK;
586
587 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
588 }
589
590 xiic_fill_tx_fifo(i2c);
591
592 /* Clear any pending Tx empty, Tx Error and then enable them. */
593 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK |
594 XIIC_INTR_BNB_MASK);
595 }
596
597 static irqreturn_t xiic_isr(int irq, void *dev_id)
598 {
599 struct xiic_i2c *i2c = dev_id;
600 u32 pend, isr, ier;
601 irqreturn_t ret = IRQ_NONE;
602 /* Do not processes a devices interrupts if the device has no
603 * interrupts pending
604 */
605
606 dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__);
607
608 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
609 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
610 pend = isr & ier;
611 if (pend)
612 ret = IRQ_WAKE_THREAD;
613
614 return ret;
615 }
616
617 static void __xiic_start_xfer(struct xiic_i2c *i2c)
618 {
619 int first = 1;
620 int fifo_space = xiic_tx_fifo_space(i2c);
621 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
622 __func__, i2c->tx_msg, fifo_space);
623
624 if (!i2c->tx_msg)
625 return;
626
627 i2c->rx_pos = 0;
628 i2c->tx_pos = 0;
629 i2c->state = STATE_START;
630 while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) {
631 if (!first) {
632 i2c->nmsgs--;
633 i2c->tx_msg++;
634 i2c->tx_pos = 0;
635 } else
636 first = 0;
637
638 if (i2c->tx_msg->flags & I2C_M_RD) {
639 /* we dont date putting several reads in the FIFO */
640 xiic_start_recv(i2c);
641 return;
642 } else {
643 xiic_start_send(i2c);
644 if (xiic_tx_space(i2c) != 0) {
645 /* the message could not be completely sent */
646 break;
647 }
648 }
649
650 fifo_space = xiic_tx_fifo_space(i2c);
651 }
652
653 /* there are more messages or the current one could not be completely
654 * put into the FIFO, also enable the half empty interrupt
655 */
656 if (i2c->nmsgs > 1 || xiic_tx_space(i2c))
657 xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK);
658
659 }
660
661 static void xiic_start_xfer(struct xiic_i2c *i2c)
662 {
663 mutex_lock(&i2c->lock);
664 xiic_reinit(i2c);
665 __xiic_start_xfer(i2c);
666 mutex_unlock(&i2c->lock);
667 }
668
669 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
670 {
671 struct xiic_i2c *i2c = i2c_get_adapdata(adap);
672 int err;
673
674 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
675 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
676
677 err = pm_runtime_get_sync(i2c->dev);
678 if (err < 0)
679 return err;
680
681 err = xiic_busy(i2c);
682 if (err)
683 goto out;
684
685 i2c->tx_msg = msgs;
686 i2c->nmsgs = num;
687
688 xiic_start_xfer(i2c);
689
690 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
691 (i2c->state == STATE_DONE), HZ)) {
692 err = (i2c->state == STATE_DONE) ? num : -EIO;
693 goto out;
694 } else {
695 i2c->tx_msg = NULL;
696 i2c->rx_msg = NULL;
697 i2c->nmsgs = 0;
698 err = -ETIMEDOUT;
699 goto out;
700 }
701 out:
702 pm_runtime_mark_last_busy(i2c->dev);
703 pm_runtime_put_autosuspend(i2c->dev);
704 return err;
705 }
706
707 static u32 xiic_func(struct i2c_adapter *adap)
708 {
709 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
710 }
711
712 static const struct i2c_algorithm xiic_algorithm = {
713 .master_xfer = xiic_xfer,
714 .functionality = xiic_func,
715 };
716
717 static const struct i2c_adapter xiic_adapter = {
718 .owner = THIS_MODULE,
719 .name = DRIVER_NAME,
720 .class = I2C_CLASS_DEPRECATED,
721 .algo = &xiic_algorithm,
722 };
723
724
725 static int xiic_i2c_probe(struct platform_device *pdev)
726 {
727 struct xiic_i2c *i2c;
728 struct xiic_i2c_platform_data *pdata;
729 struct resource *res;
730 int ret, irq;
731 u8 i;
732 u32 sr;
733
734 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
735 if (!i2c)
736 return -ENOMEM;
737
738 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
739 i2c->base = devm_ioremap_resource(&pdev->dev, res);
740 if (IS_ERR(i2c->base))
741 return PTR_ERR(i2c->base);
742
743 irq = platform_get_irq(pdev, 0);
744 if (irq < 0)
745 return irq;
746
747 pdata = dev_get_platdata(&pdev->dev);
748
749 /* hook up driver to tree */
750 platform_set_drvdata(pdev, i2c);
751 i2c->adap = xiic_adapter;
752 i2c_set_adapdata(&i2c->adap, i2c);
753 i2c->adap.dev.parent = &pdev->dev;
754 i2c->adap.dev.of_node = pdev->dev.of_node;
755
756 mutex_init(&i2c->lock);
757 init_waitqueue_head(&i2c->wait);
758
759 i2c->clk = devm_clk_get(&pdev->dev, NULL);
760 if (IS_ERR(i2c->clk)) {
761 dev_err(&pdev->dev, "input clock not found.\n");
762 return PTR_ERR(i2c->clk);
763 }
764 ret = clk_prepare_enable(i2c->clk);
765 if (ret) {
766 dev_err(&pdev->dev, "Unable to enable clock.\n");
767 return ret;
768 }
769 i2c->dev = &pdev->dev;
770 pm_runtime_enable(i2c->dev);
771 pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT);
772 pm_runtime_use_autosuspend(i2c->dev);
773 pm_runtime_set_active(i2c->dev);
774 ret = devm_request_threaded_irq(&pdev->dev, irq, xiic_isr,
775 xiic_process, IRQF_ONESHOT,
776 pdev->name, i2c);
777
778 if (ret < 0) {
779 dev_err(&pdev->dev, "Cannot claim IRQ\n");
780 goto err_clk_dis;
781 }
782
783 /*
784 * Detect endianness
785 * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not
786 * set, assume that the endianness was wrong and swap.
787 */
788 i2c->endianness = LITTLE;
789 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
790 /* Reset is cleared in xiic_reinit */
791 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET);
792 if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK))
793 i2c->endianness = BIG;
794
795 xiic_reinit(i2c);
796
797 /* add i2c adapter to i2c tree */
798 ret = i2c_add_adapter(&i2c->adap);
799 if (ret) {
800 xiic_deinit(i2c);
801 goto err_clk_dis;
802 }
803
804 if (pdata) {
805 /* add in known devices to the bus */
806 for (i = 0; i < pdata->num_devices; i++)
807 i2c_new_device(&i2c->adap, pdata->devices + i);
808 }
809
810 return 0;
811
812 err_clk_dis:
813 pm_runtime_set_suspended(&pdev->dev);
814 pm_runtime_disable(&pdev->dev);
815 clk_disable_unprepare(i2c->clk);
816 return ret;
817 }
818
819 static int xiic_i2c_remove(struct platform_device *pdev)
820 {
821 struct xiic_i2c *i2c = platform_get_drvdata(pdev);
822 int ret;
823
824 /* remove adapter & data */
825 i2c_del_adapter(&i2c->adap);
826
827 ret = clk_prepare_enable(i2c->clk);
828 if (ret) {
829 dev_err(&pdev->dev, "Unable to enable clock.\n");
830 return ret;
831 }
832 xiic_deinit(i2c);
833 clk_disable_unprepare(i2c->clk);
834 pm_runtime_disable(&pdev->dev);
835
836 return 0;
837 }
838
839 #if defined(CONFIG_OF)
840 static const struct of_device_id xiic_of_match[] = {
841 { .compatible = "xlnx,xps-iic-2.00.a", },
842 {},
843 };
844 MODULE_DEVICE_TABLE(of, xiic_of_match);
845 #endif
846
847 static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev)
848 {
849 struct xiic_i2c *i2c = dev_get_drvdata(dev);
850
851 clk_disable(i2c->clk);
852
853 return 0;
854 }
855
856 static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev)
857 {
858 struct xiic_i2c *i2c = dev_get_drvdata(dev);
859 int ret;
860
861 ret = clk_enable(i2c->clk);
862 if (ret) {
863 dev_err(dev, "Cannot enable clock.\n");
864 return ret;
865 }
866
867 return 0;
868 }
869
870 static const struct dev_pm_ops xiic_dev_pm_ops = {
871 SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend,
872 xiic_i2c_runtime_resume, NULL)
873 };
874 static struct platform_driver xiic_i2c_driver = {
875 .probe = xiic_i2c_probe,
876 .remove = xiic_i2c_remove,
877 .driver = {
878 .name = DRIVER_NAME,
879 .of_match_table = of_match_ptr(xiic_of_match),
880 .pm = &xiic_dev_pm_ops,
881 },
882 };
883
884 module_platform_driver(xiic_i2c_driver);
885
886 MODULE_AUTHOR("info@mocean-labs.com");
887 MODULE_DESCRIPTION("Xilinx I2C bus driver");
888 MODULE_LICENSE("GPL v2");
889 MODULE_ALIAS("platform:"DRIVER_NAME);
Linux with added FPC-III support