| commit | 119c2dc0156d069670870ade931dba0963367575 | |
| author | Filip Kokosinski <fkokosinski@antmicro.com> | |
| Tue, 22 Dec 2020 21:38:21 +0000 (22 16:38 -0500) | ||
| committer | Gabriel Somlo <gsomlo@gmail.com> | |
| Tue, 12 Jan 2021 17:30:24 +0000 (12 12:30 -0500) | ||
| tree | f2243277e765e3980d623765897e424e9535a4dd | treesnapshot (tar.gz zip) |
| parent | 47ea6262467869dfbdf442230fcc692996d26efa | commitdiff |
LiteX: support for VexRiscV interrupt controller
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
FIXME: not updated or tested for 32-bit CSR data width, 64-bit CPU (gls)
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
FIXME: not updated or tested for 32-bit CSR data width, 64-bit CPU (gls)
| arch/riscv/Kconfig | diffblobblamehistory | |
| drivers/irqchip/Kconfig | diffblobblamehistory | |
| drivers/irqchip/Makefile | diffblobblamehistory | |
| drivers/irqchip/irq-litex-vexriscv.c | [new file with mode: 0644] | blob |