| commit | 1d26fe28e13ed261cace13638536d17982d2d1cd | |
| author | Jesse Barnes <jbarnes@virtuousgeek.org> | |
| Wed, 21 Apr 2010 18:39:23 +0000 (21 11:39 -0700) | ||
| committer | Greg Kroah-Hartman <gregkh@suse.de> | |
| Wed, 26 May 2010 21:32:05 +0000 (26 14:32 -0700) | ||
| tree | ff861355e7678ac28a805723df8a421c719ad7f5 | treesnapshot (tar.gz zip) |
| parent | 6129e3835577255a083a32841f11519ffc43051d | commitdiff |
drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy Bridge
commit e552eb7038a36d9b18860f525aa02875e313fe16 upstream.
Since 965, the hardware has supported the PIPE_CONTROL command, which
provides fine grained GPU cache flushing control. On recent chipsets,
this instruction is required for reliable interrupt and sequence number
reporting in the driver.
So add support for this instruction, including workarounds, on Ironlake
and Sandy Bridge hardware.
https://bugs.freedesktop.org/show_bug.cgi?id=27108
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
commit e552eb7038a36d9b18860f525aa02875e313fe16 upstream.
Since 965, the hardware has supported the PIPE_CONTROL command, which
provides fine grained GPU cache flushing control. On recent chipsets,
this instruction is required for reliable interrupt and sequence number
reporting in the driver.
So add support for this instruction, including workarounds, on Ironlake
and Sandy Bridge hardware.
https://bugs.freedesktop.org/show_bug.cgi?id=27108
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>