| commit | 2d91b491d5be13602a73be789bb8a3c28d06b7f2 | |
| author | Jisheng Zhang <jszhang@marvell.com> | |
| Thu, 30 Apr 2015 08:22:29 +0000 (30 16:22 +0800) | ||
| committer | Bjorn Helgaas <bhelgaas@google.com> | |
| Wed, 20 May 2015 20:01:57 +0000 (20 15:01 -0500) | ||
| tree | 9df5767fb59a487d5282aa675cfa7efeb27f0d1e | treesnapshot (tar.gz zip) |
| parent | 63503c87f06e0f2c8c951cada81221c5500188d8 | commitdiff |
PCI: designware: Use iATU0 for cfg and IO, iATU1 for MEM
Most transactions' type are cfg0 and MEM, so the current iATU usage is not
balanced: iATU0 is hot while iATU1 is rarely used.
Refactor the iATU usage so we use iATU0 for cfg and IO and iATU1 for MEM.
This allocation idea comes from Minghuan Lian
<Minghuan.Lian@freescale.com>:
[bhelgaas: use link with Message-ID]
Link: http://lkml.kernel.org/r/1429091315-31891-3-git-send-email-Minghuan.Lian@freescale.com
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
Most transactions' type are cfg0 and MEM, so the current iATU usage is not
balanced: iATU0 is hot while iATU1 is rarely used.
Refactor the iATU usage so we use iATU0 for cfg and IO and iATU1 for MEM.
This allocation idea comes from Minghuan Lian
<Minghuan.Lian@freescale.com>:
[bhelgaas: use link with Message-ID]
Link: http://lkml.kernel.org/r/1429091315-31891-3-git-send-email-Minghuan.Lian@freescale.com
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
| drivers/pci/host/pcie-designware.c | diffblobblamehistory |