| commit | 35817d34bd07b4e1cd597e054fa2bd9c9c111aab | |
| author | Icenowy Zheng <icenowy@aosc.io> | |
| Fri, 16 Mar 2018 14:02:09 +0000 (16 22:02 +0800) | ||
| committer | Linus Walleij <linus.walleij@linaro.org> | |
| Tue, 27 Mar 2018 13:07:49 +0000 (27 15:07 +0200) | ||
| tree | 4e0c17938c4a90cff2b3f1dbe127d5760629b7d8 | treesnapshot (tar.gz zip) |
| parent | 29dfc6bbcc5e1ef7ce1008c4713387efb8f567d2 | commitdiff |
pinctrl: sunxi: change irq_bank_base to irq_bank_map
The Allwinner H6 SoC have its pin controllers with the first IRQ-capable
GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5.
Change the current code that uses IRQ bank base to a IRQ bank map, in
order to support the case that holes exist among IRQ banks.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Allwinner H6 SoC have its pin controllers with the first IRQ-capable
GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5.
Change the current code that uses IRQ bank base to a IRQ bank map, in
order to support the case that holes exist among IRQ banks.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c | diffblobblamehistory | |
| drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | diffblobblamehistory | |
| drivers/pinctrl/sunxi/pinctrl-sunxi.h | diffblobblamehistory |