| commit | 47d64fef1f3ffbdf960d3330b9865fc9f12fdf84 | |
| author | Samuel Holland <samuel@sholland.org> | |
| Sun, 29 Dec 2019 02:59:20 +0000 (28 20:59 -0600) | ||
| committer | Maxime Ripard <maxime@cerno.tech> | |
| Thu, 2 Jan 2020 09:27:47 +0000 (2 10:27 +0100) | ||
| tree | 658d63a7bcb8714cef74ffad52f3bcd3d3962a31 | treesnapshot (tar.gz zip) |
| parent | c7b305267eb77fe47498676e9337324c9653494c | commitdiff |
clk: sunxi-ng: sun8i-r: Fix divider on APB0 clock
According to the BSP source code, the APB0 clock on the H3 and H5 has a
normal M divider, not a power-of-two divider. This matches the hardware
in the A83T (as described in both the BSP source code and the manual).
Since the A83T and H3/A64 clocks are actually the same, we can merge the
definitions.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
According to the BSP source code, the APB0 clock on the H3 and H5 has a
normal M divider, not a power-of-two divider. This matches the hardware
in the A83T (as described in both the BSP source code and the manual).
Since the A83T and H3/A64 clocks are actually the same, we can merge the
definitions.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
| drivers/clk/sunxi-ng/ccu-sun8i-r.c | diffblobblamehistory |