| commit | 691557941af4c12bd307ad81a4d9fa9c7743ac28 | |
| author | Jon Medhurst <tixy@linaro.org> | |
| Fri, 7 Jun 2013 09:35:35 +0000 (7 10:35 +0100) | ||
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | |
| Mon, 17 Jun 2013 09:30:49 +0000 (17 10:30 +0100) | ||
| tree | 7382502cccc9bff1e3ca38f353f335d70a376ded | treesnapshot (tar.gz zip) |
| parent | 509eb76ebf9771abc9fe51859382df2571f11447 | commitdiff |
ARM: 7752/1: errata: LoUIS bit field in CLIDR register is incorrect
On Cortex-A9 before version r1p0, the LoUIS bit field of the CLIDR
register returns zero when it should return one. This leads to cache
maintenance operations which rely on this value to not function as
intended, causing data corruption.
The workaround for this errata is to detect affected CPUs and correct
the LoUIS value read.
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Cc: stable@vger.kernel.org
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
On Cortex-A9 before version r1p0, the LoUIS bit field of the CLIDR
register returns zero when it should return one. This leads to cache
maintenance operations which rely on this value to not function as
intended, causing data corruption.
The workaround for this errata is to detect affected CPUs and correct
the LoUIS value read.
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Cc: stable@vger.kernel.org
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| arch/arm/Kconfig | diffblobblamehistory | |
| arch/arm/mm/cache-v7.S | diffblobblamehistory |