| commit | 69d733e72ddae1680ffd3b5c648ff31cb46d9cc9 | |
| author | Gavin Shan <gwshan@linux.vnet.ibm.com> | |
| Tue, 3 May 2016 05:41:28 +0000 (3 15:41 +1000) | ||
| committer | Michael Ellerman <mpe@ellerman.id.au> | |
| Wed, 11 May 2016 11:54:19 +0000 (11 21:54 +1000) | ||
| tree | 981d4dbb1446aad40de991a25e293420ba987a6d | treesnapshot (tar.gz zip) |
| parent | 23e79425fe7caaa93ddcee18ac4c57069f0fb4b6 | commitdiff |
powerpc/powernv: IO and M32 mapping based on PCI device resources
Currently, the IO and M32 segments are mapped to the corresponding
PE based on the windows of the parent bridge of PE's primary bus.
It's not going to work when the windows of root port or upstream
port of the PCIe switch behind root port are extended to PHB's
apertures in order to support hotplug in subsequent patch.
This fixes the issue by mapping IO and M32 segments based on the
resources of the PCI devices included in the PE, instead of the
windows of the parent bridge of the PE's primary bus.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Currently, the IO and M32 segments are mapped to the corresponding
PE based on the windows of the parent bridge of PE's primary bus.
It's not going to work when the windows of root port or upstream
port of the PCIe switch behind root port are extended to PHB's
apertures in order to support hotplug in subsequent patch.
This fixes the issue by mapping IO and M32 segments based on the
resources of the PCI devices included in the PE, instead of the
windows of the parent bridge of the PE's primary bus.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
| arch/powerpc/platforms/powernv/pci-ioda.c | diffblobblamehistory |