| commit | 8da3ffaafeb6a16ae8abb02b0fdaff772bc686a1 | |
| author | Roger Quadros <rogerq@ti.com> | |
| Mon, 16 Mar 2020 10:27:31 +0000 (16 12:27 +0200) | ||
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| Thu, 2 Apr 2020 13:28:16 +0000 (2 15:28 +0200) | ||
| tree | b9c9b3be4f983bc33877cb3425688c558f96aed4 | treesnapshot (tar.gz zip) |
| parent | aa9e1a3bded80c06ccd54e72ddcc43a5bc911268 | commitdiff |
ARM: dts: omap5: Add bus_dma_limit for L3 bus
commit dfa7ea303f56a3a8b1ed3b91ef35af2da67ca4ee upstream.
The L3 interconnect's memory map is from 0x0 to
0xffffffff. Out of this, System memory (SDRAM) can be
accessed from 0x80000000 to 0xffffffff (2GB)
OMAP5 does support 4GB of SDRAM but upper 2GB can only be
accessed by the MPU subsystem.
Add the dma-ranges property to reflect the physical address limit
of the L3 bus.
Cc: stable@kernel.org
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit dfa7ea303f56a3a8b1ed3b91ef35af2da67ca4ee upstream.
The L3 interconnect's memory map is from 0x0 to
0xffffffff. Out of this, System memory (SDRAM) can be
accessed from 0x80000000 to 0xffffffff (2GB)
OMAP5 does support 4GB of SDRAM but upper 2GB can only be
accessed by the MPU subsystem.
Add the dma-ranges property to reflect the physical address limit
of the L3 bus.
Cc: stable@kernel.org
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| arch/arm/boot/dts/omap5.dtsi | diffblobblamehistory |