| commit | 8e66e134e20b936179ea1535dd4ed19ec4f99dba | |
| author | Alex Deucher <alexander.deucher@amd.com> | |
| Wed, 15 Oct 2014 21:20:55 +0000 (15 17:20 -0400) | ||
| committer | Alex Deucher <alexander.deucher@amd.com> | |
| Thu, 16 Oct 2014 22:34:09 +0000 (16 18:34 -0400) | ||
| tree | 72d79bcfa0252136570760964444792ecfb17a5e | treesnapshot (tar.gz zip) |
| parent | e300180f71037fd9ed1ca967006fd9f3ee466bcd | commitdiff |
drm/radeon: fix vm page table block size calculation
The page offset is 12 bits. For example if we have an
8 GB VM, we'd need 33 bits. The number of bits needed
for PD + PT is 21 (33 - 12 or log2(8) + 18), not 20
(log2(8) + 17).
Noticed by Alexey during code review.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
The page offset is 12 bits. For example if we have an
8 GB VM, we'd need 33 bits. The number of bits needed
for PD + PT is 21 (33 - 12 or log2(8) + 18), not 20
(log2(8) + 17).
Noticed by Alexey during code review.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
| drivers/gpu/drm/radeon/radeon_device.c | diffblobblamehistory |