| commit | 96a2f92bf8a4d0bf4a49bdd6539561a2c3289f37 | |
| author | Gavin Shan <gwshan@linux.vnet.ibm.com> | |
| Fri, 19 Jun 2015 02:26:17 +0000 (19 12:26 +1000) | ||
| committer | Michael Ellerman <mpe@ellerman.id.au> | |
| Mon, 13 Jul 2015 06:12:00 +0000 (13 16:12 +1000) | ||
| tree | ba3fbb6b804232b1b777a6a766adda8a05cbdf87 | treesnapshot (tar.gz zip) |
| parent | e9dc4d7f72a375020ecbc9ca35b098fd9018910b | commitdiff |
powerpc/powernv: Reserve M64 PEs based on BARs
On PHB3, some PEs might be reserved in advance to reflect the M64
segments consumed by those PEs. We're reserving PEs based on the
M64 window of root port, which might contain VF BAR. The PEs for
VFs are allocated dynamically, not reserved based on the consumed
M64 segments. So the M64 window of root port isn't reliable for
the task. Instead, we go through M64 BARs (VF BARs excluded) of
PCI devices under the specified root bus and reserve PEs accordingly,
as the patch does.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
On PHB3, some PEs might be reserved in advance to reflect the M64
segments consumed by those PEs. We're reserving PEs based on the
M64 window of root port, which might contain VF BAR. The PEs for
VFs are allocated dynamically, not reserved based on the consumed
M64 segments. So the M64 window of root port isn't reliable for
the task. Instead, we go through M64 BARs (VF BARs excluded) of
PCI devices under the specified root bus and reserve PEs accordingly,
as the patch does.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
| arch/powerpc/platforms/powernv/pci-ioda.c | diffblobblamehistory | |
| arch/powerpc/platforms/powernv/pci.h | diffblobblamehistory |