| commit | 9a20b09285bbd75ccc2ca78233241f8e31d54a28 | |
| author | Maciej W. Rozycki <macro@linux-mips.org> | |
| Wed, 27 May 2015 13:15:20 +0000 (27 14:15 +0100) | ||
| committer | Ralf Baechle <ralf@linux-mips.org> | |
| Sun, 21 Jun 2015 19:52:41 +0000 (21 21:52 +0200) | ||
| tree | f18914b5a7e902428a14a9b58025d64ff950d64e | treesnapshot (tar.gz zip) |
| parent | 3bcb03f3a7160e411c5f335028a5c70b32f0edb7 | commitdiff |
MIPS: tlb-r3k: Optimise a TLBWI barrier in TLB invalidation
Replace an explicit barrier with a useful processor instruction in TLB
invalidation, following several other such cases elsewhere in
`tlb-r3k.c'.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10196/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Replace an explicit barrier with a useful processor instruction in TLB
invalidation, following several other such cases elsewhere in
`tlb-r3k.c'.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10196/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| arch/mips/mm/tlb-r3k.c | diffblobblamehistory |