| commit | b86d4a024be4bd761b097d83efbae5afafe46bc8 | |
| author | Jesse Barnes <jbarnes@virtuousgeek.org> | |
| Wed, 30 Jun 2010 20:49:37 +0000 (30 13:49 -0700) | ||
| committer | Greg Kroah-Hartman <gregkh@suse.de> | |
| Mon, 2 Aug 2010 17:29:35 +0000 (2 10:29 -0700) | ||
| tree | 7741b2ed73c7264889434217c8a0268b0e1aea74 | treesnapshot (tar.gz zip) |
| parent | 1b68c0ff661af1c4a403727937ae3f33bc278e6b | commitdiff |
drm/i915: don't access FW_BLC_SELF on 965G
commit adcdbc6651a7086b99827cf50623a02d941261f1 upstream.
The register offset for FW_BLC_SELF is a totally different set of bits
on Broadwater (it's actually MI_RDRET_STATE), so don't treat it like
FW_BLC_SELF on 965G chips.
Fixes bug https://bugs.freedesktop.org/show_bug.cgi?id=26874.
Tested-by: Norman Yarvin <yarvin@yarchive.net>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
commit adcdbc6651a7086b99827cf50623a02d941261f1 upstream.
The register offset for FW_BLC_SELF is a totally different set of bits
on Broadwater (it's actually MI_RDRET_STATE), so don't treat it like
FW_BLC_SELF on 965G chips.
Fixes bug https://bugs.freedesktop.org/show_bug.cgi?id=26874.
Tested-by: Norman Yarvin <yarvin@yarchive.net>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| drivers/gpu/drm/i915/i915_debugfs.c | diffblobblamehistory | |
| drivers/gpu/drm/i915/intel_display.c | diffblobblamehistory |