| commit | b9c2470fb150a3cc82a3ee8072da88cb2a73e213 | |
| author | Shardar Shariff Md <smohammed@nvidia.com> | |
| Wed, 4 Sep 2019 04:42:58 +0000 (4 10:12 +0530) | ||
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| Thu, 5 Sep 2019 08:00:03 +0000 (5 10:00 +0200) | ||
| tree | 6d3043b8f583e99a5d378a031c2c150f813a2f89 | treesnapshot (tar.gz zip) |
| parent | 494f79bd2365703e4093efa0ecf4b139d83aba97 | commitdiff |
serial: tegra: flush the RX fifo on frame error
FIFO reset/flush code implemented now does not follow programming
guidelines. RTS line has to be turned off while flushing FIFOs to
avoid new transfers. Also check LSR bits UART_LSR_TEMT and UART_LSR_DR
to confirm FIFOs are flushed.
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Link: https://lore.kernel.org/r/1567572187-29820-4-git-send-email-kyarlagadda@nvidia.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
FIFO reset/flush code implemented now does not follow programming
guidelines. RTS line has to be turned off while flushing FIFOs to
avoid new transfers. Also check LSR bits UART_LSR_TEMT and UART_LSR_DR
to confirm FIFOs are flushed.
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Link: https://lore.kernel.org/r/1567572187-29820-4-git-send-email-kyarlagadda@nvidia.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| drivers/tty/serial/serial-tegra.c | diffblobblamehistory |