| commit | d5efd9cc9cf2e422d064c912c7d5d985f52c1b2c | |
| author | Will Deacon <will.deacon@arm.com> | |
| Fri, 6 Mar 2015 11:54:10 +0000 (6 11:54 +0000) | ||
| committer | Will Deacon <will.deacon@arm.com> | |
| Tue, 24 Mar 2015 15:09:47 +0000 (24 15:09 +0000) | ||
| tree | ec4a29ce1df9016b48597888d55e925f3bdf4ac5 | treesnapshot (tar.gz zip) |
| parent | 71bbf038eaa44a80dd6df0da7c708d4618172fe0 | commitdiff |
arm64: pmu: add support for interrupt-affinity property
Historically, the PMU devicetree bindings have expected SPIs to be
listed in order of *logical* CPU number. This is problematic for
bootloaders, especially when the boot CPU (logical ID 0) isn't listed
first in the devicetree.
This patch adds a new optional property, interrupt-affinity, to the
PMU node which allows the interrupt affinity to be described using
a list of phandled to CPU nodes, with each entry in the list
corresponding to the SPI at the same index in the interrupts property.
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Historically, the PMU devicetree bindings have expected SPIs to be
listed in order of *logical* CPU number. This is problematic for
bootloaders, especially when the boot CPU (logical ID 0) isn't listed
first in the devicetree.
This patch adds a new optional property, interrupt-affinity, to the
PMU node which allows the interrupt affinity to be described using
a list of phandled to CPU nodes, with each entry in the list
corresponding to the SPI at the same index in the interrupts property.
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
| arch/arm64/include/asm/pmu.h | diffblobblamehistory | |
| arch/arm64/kernel/perf_event.c | diffblobblamehistory |