| commit | d9286d9743b6e8cfbf1a13f8db84e9c65c0b09c7 | |
| author | Geert Uytterhoeven <geert+renesas@glider.be> | |
| Mon, 21 Jan 2019 13:07:39 +0000 (21 14:07 +0100) | ||
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | |
| Thu, 24 Jan 2019 15:01:08 +0000 (24 16:01 +0100) | ||
| tree | 4b69ea99bb916242930a53667951e13ccad64f57 | treesnapshot (tar.gz zip) |
| parent | 9d034e151b407cbd2c66bc4c48b423f814533374 | commitdiff |
clk: renesas: r8a774c0: Correct parent clock of DU
According to the RZ/G Series, 2nd Generation Hardware Manual Rev 0.61,
the parent clock of the DU module clocks on RZ/G2E is S1D1.
Fixes: 906e0a4a6d1ef2d3 ("clk: renesas: cpg-mssr: Add r8a774c0 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
According to the RZ/G Series, 2nd Generation Hardware Manual Rev 0.61,
the parent clock of the DU module clocks on RZ/G2E is S1D1.
Fixes: 906e0a4a6d1ef2d3 ("clk: renesas: cpg-mssr: Add r8a774c0 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
| drivers/clk/renesas/r8a774c0-cpg-mssr.c | diffblobblamehistory |