| commit | f2080b9ac3c450c06a380237e6338f1e43468665 | |
| author | Madhavan Srinivasan <maddy@linux.vnet.ibm.com> | |
| Tue, 11 Apr 2017 01:51:10 +0000 (11 07:21 +0530) | ||
| committer | Michael Ellerman <mpe@ellerman.id.au> | |
| Wed, 19 Apr 2017 10:00:23 +0000 (19 20:00 +1000) | ||
| tree | 27b3585fba846cdff8ec63c31bf99eca5466e8aa | treesnapshot (tar.gz zip) |
| parent | d148c94c27a87213f995f0a7519b231719cfb919 | commitdiff |
powerpc/perf: Add Power8 mem_access event to sysfs
Patch add "mem_access" event to sysfs. This as-is not a raw event
supported by Power8 pmu. Instead, it is formed based on
raw event encoding specificed in isa207-common.h.
Primary PMU event used here is PM_MRK_INST_CMPL.
This event tracks only the completed marked instructions.
Random sampling mode (MMCRA[SM]) with Random Instruction
Sampling (RIS) is enabled to mark type of instructions.
With Random sampling in RLS mode with PM_MRK_INST_CMPL event,
the LDST /DATA_SRC fields in SIER identifies the memory
hierarchy level (eg: L1, L2 etc) statisfied a data-cache
miss for a marked instruction.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Patch add "mem_access" event to sysfs. This as-is not a raw event
supported by Power8 pmu. Instead, it is formed based on
raw event encoding specificed in isa207-common.h.
Primary PMU event used here is PM_MRK_INST_CMPL.
This event tracks only the completed marked instructions.
Random sampling mode (MMCRA[SM]) with Random Instruction
Sampling (RIS) is enabled to mark type of instructions.
With Random sampling in RLS mode with PM_MRK_INST_CMPL event,
the LDST /DATA_SRC fields in SIER identifies the memory
hierarchy level (eg: L1, L2 etc) statisfied a data-cache
miss for a marked instruction.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
| arch/powerpc/perf/power8-events-list.h | diffblobblamehistory | |
| arch/powerpc/perf/power8-pmu.c | diffblobblamehistory |