| commit | f544847fbaf099278343f875987a983f2b913134 | |
| author | Jesse Barnes <jbarnes@virtuousgeek.org> | |
| Tue, 14 Apr 2009 21:17:47 +0000 (14 14:17 -0700) | ||
| committer | Eric Anholt <eric@anholt.net> | |
| Thu, 16 Apr 2009 18:13:11 +0000 (16 11:13 -0700) | ||
| tree | 3d0fa173125c6e5725c441d1af27fb38baa07241 | treesnapshot (tar.gz zip) |
| parent | cd97824994042b809493807ea644ba26c0c23290 | commitdiff |
drm/i915: allow tiled front buffers on 965+
This patch corrects a pretty big oversight in the KMS code for 965+
chips. The current code is missing tiled surface register programming,
so userland can allocate a tiled surface and use it for mode setting,
resulting in corruption. This patch fixes that, allowing for tiled
front buffers on 965+.
Cc: stable@kernel.org
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
This patch corrects a pretty big oversight in the KMS code for 965+
chips. The current code is missing tiled surface register programming,
so userland can allocate a tiled surface and use it for mode setting,
resulting in corruption. This patch fixes that, allowing for tiled
front buffers on 965+.
Cc: stable@kernel.org
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
| drivers/gpu/drm/i915/i915_reg.h | diffblobblamehistory | |
| drivers/gpu/drm/i915/intel_display.c | diffblobblamehistory |