| commit | f8870ae6e2d6be75b1accc2db981169fdfbea7ab | |
| author | Adrian Hunter <adrian.hunter@intel.com> | |
| Wed, 14 Feb 2018 13:57:43 +0000 (14 15:57 +0200) | ||
| committer | Ulf Hansson <ulf.hansson@linaro.org> | |
| Tue, 27 Feb 2018 09:03:48 +0000 (27 10:03 +0100) | ||
| tree | 217bd38b934c9516a3007b8c63fd73773ad352b0 | treesnapshot (tar.gz zip) |
| parent | 4a3928c6f8a53fa1aed28ccba227742486e8ddcb | commitdiff |
mmc: sdhci-pci: Fix S0i3 for Intel BYT-based controllers
Tuning can leave the IP in an active state (Buffer Read Enable bit set)
which prevents the entry to low power states (i.e. S0i3). Data reset will
clear it.
Generally tuning is followed by a data transfer which will anyway sort out
the state, so it is rare that S0i3 is actually prevented.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Tuning can leave the IP in an active state (Buffer Read Enable bit set)
which prevents the entry to low power states (i.e. S0i3). Data reset will
clear it.
Generally tuning is followed by a data transfer which will anyway sort out
the state, so it is rare that S0i3 is actually prevented.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| drivers/mmc/host/sdhci-pci-core.c | diffblobblamehistory |