| commit | f8fdf5375e2005f238ce9b430724752a6e3d55cc | |
| author | Steffen Trumtrar <s.trumtrar@pengutronix.de> | |
| Mon, 19 Aug 2013 15:05:59 +0000 (19 17:05 +0200) | ||
| committer | Mark Brown <broonie@linaro.org> | |
| Thu, 22 Aug 2013 10:09:52 +0000 (22 11:09 +0100) | ||
| tree | d53268fb193d587e34f3d86b1b2f73f147c6e413 | treesnapshot (tar.gz zip) |
| parent | cd7f0295aab102acb77c19d6d77eab5f5145364c | commitdiff |
ASoC: fsl-ssi: add SSIEN errata work around
The chip errata for the i.MX35, Rev.2 has the following errata:
ENGcm06222: SSI:Transmission does not take place in bit length early frame sync
configuration
The workaround states, that TX_EN and SSI_EN bits should be set in the same
register write. As the next errata in the document (ENGcm06532) says to always
write RX_EN and TX_EN in the same register write in network mode.
Therefore include the whole write to
CCSR_SSI_SCR_TE and CCSR_SSI_SCR_RE
into the write to
CCSR_SSI_SCR_SSIEN
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
The chip errata for the i.MX35, Rev.2 has the following errata:
ENGcm06222: SSI:Transmission does not take place in bit length early frame sync
configuration
The workaround states, that TX_EN and SSI_EN bits should be set in the same
register write. As the next errata in the document (ENGcm06532) says to always
write RX_EN and TX_EN in the same register write in network mode.
Therefore include the whole write to
CCSR_SSI_SCR_TE and CCSR_SSI_SCR_RE
into the write to
CCSR_SSI_SCR_SSIEN
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
| sound/soc/fsl/fsl_ssi.c | diffblobblamehistory |