| commit | fcc188e7fdddd8b23f900e485e6b3db05e7375f4 | |
| author | Roland Dreier <rolandd@cisco.com> | |
| Mon, 7 Nov 2005 08:58:11 +0000 (7 00:58 -0800) | ||
| committer | Linus Torvalds <torvalds@g5.osdl.org> | |
| Mon, 7 Nov 2005 15:53:26 +0000 (7 07:53 -0800) | ||
| tree | 8da8cac96f2ca884039e31cd6ff9d00e21cc2aea | treesnapshot (tar.gz zip) |
| parent | 2104da90a9aeef31ff6441d171a7d0492088f1d0 | commitdiff |
[PATCH] ppc32: Allow ERPN for early serial to depend on CPU type
The PowerPC 440SPe supports up to 16 GB of RAM, and therefore its IO registers
are at 0x4_xxxx_xxxx instead of being at 0x1_xxxx_xxxx like most other PPC 440
chips. To allow for this, this patch moves the definition of the ERPN used
for mapping UART0 from being hard-coded in the head_44x.S assembly code to
being defined in ibm44x.h.
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Signed-off-by: Matt Porter <mporter@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
The PowerPC 440SPe supports up to 16 GB of RAM, and therefore its IO registers
are at 0x4_xxxx_xxxx instead of being at 0x1_xxxx_xxxx like most other PPC 440
chips. To allow for this, this patch moves the definition of the ERPN used
for mapping UART0 from being hard-coded in the head_44x.S assembly code to
being defined in ibm44x.h.
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Signed-off-by: Matt Porter <mporter@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
| arch/ppc/kernel/head_44x.S | diffblobblamehistory | |
| include/asm-ppc/ibm44x.h | diffblobblamehistory |